An Ultrafast Optical Digital Technology
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1 An Ultrafast Optical Digital Technology Smart Light Stanford University EE380 Corporation
2 Overview Overview Background What and How methodology optical state machines Why smart speed power size cost Historical Perspective Summary
3 Background Overview Background What and How methodology optical state machines Why smart speed power size cost Historical Perspective Summary
4 Background - Starlite Packet Switch Pipelined State Machine Architecture (Batcher / Banyan) 32 inputs each at 100 Mb/s (1982) evolved into AT&T s First Broadband ATM Switch (1987)
5 Background - Free Space Optical Switching / Computing at Bell Labs 4 10 KHz 216 sq. ft. (1984) 48 2 MHz 1 sq. ft. (1985) 4x48 2 MHz 4 sq. ft. (1986) 6x MHz (1987)
6 Technology - Beyond Electronics
7 Sagnac Logic Gate Input A 3 db coupler Input B 50/50 coupler polarization coupler fiber loop Output Y Output X Output C polarization coupler counter propagating pulse streams
8 Sagnac Logic Gate 2.5 Gb/s digital loop (Bell Labs 1993) 1.6 Tb/s digital oscillator (Bell Labs 1993) % transmission Intensity relative delay (ps.) Jitter Tolerance (Bell Labs 1992) Non-linear Transfer Function (Bell Labs 1990)
9 Ultrafast All-Optical Time Division Multiplexing
10 What and How? Overview Background What and How methodology optical state machines Why smart speed power size cost Historical Perspective Summary
11 Methodology - Device Application State Machine Device Introduction to VLSI Systems by Mead and Conway
12 Device Sagnac Logic Gate Input A 3 db coupler Input B 50/50 coupler polarization coupler fiber loop Output Y Output X Output C polarization coupler counter propagating pulse streams
13 Methodology State Machines Application State Machine Device
14 Optical State Machine electronic optical
15 Pipelined WDM Optical State Machine
16 Pipelined WDM Relay-Logic Optical State Machine
17 Plumbing Simulations
18 Logic Simulations
19 Logic, plumbing, and juggling PSPICE model
20 Example: Analog Simulation of Optical Memory Loop power supply A D X B D Y 600mV 500mV 500mV 400mV 400mV 300mV 300mV 200mV 200mV 100mV 100mV 0V 0V -100mV 0s 5ns 10ns 15ns 20ns 25ns 30ns 35ns 40ns 45ns 50ns V(Sagnac1:out_pwr) Time -100mV 0s 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns V(Sagnac1:out_pwr) V(ABM12:OUT) Time
21 Example: Analog Simulation of Sagnac Divide by 4 Circuit
22 L coupler L splitter L circulator L coupler L splitter L circulator D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D circulator D splitter D coupler D fiber_loop D coupler D splitter D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 D delay_d0 How? Power vs. Time design methodology Hetch Hetchy Hydraulical Map Minard Napoleon s Moscow Campaign (The Visual Display of Quantitative Information, Tufte) L isolator L mux L circulator L splitter L coupler L fiber_loop input A dependent loss L demux L mux L circulator L splitter L coupler L fiber_loop input B dependent loss noise ASE optical power P source_laser input λ 0 L demux L mux L circulator L splitter L coupler L fiber_loop feedback variable C dependent loss L coupler L L splitter circulator G OR_amp λ 1 λ 2 L demux λ 3 λ 8 λ 9 λ 10 input variable A input variable B input variable C L mux output (λ 0 λ 1 λ 2 λ 3 ) (λ 8 λ 9 λ 10 ) noise ASE D isolator D mux D circulator D splitter D coupler D fiber_loop D coupler D D splitter circulator D demux D mux D circulator D splitter D coupler D fiber_loop D coupler D splitter D circulator D demux D mux D circulator D splitter or or fiber_loop D D coupler D coupler D splitter D circulator or D demux D mux D OR_amp D delay D jitter tolerance jitter tolerance delay jitter tolerance D delay D source_module D AND_module D AND_module D AND_module D OR_module Power vs. Time diagram for an interlaced optical state machine optical power L circulator Lsplitter L coupler L fiber_loop Lcoupler Lsplitter P clock_laser input (λ0 λ1 λ2 λ3) (λ8 λ9 λ10) noise ASE dependent loss L delay input l clock input (λ 0 λ 1 λ 2 λ 3 ) (λ 8 λ 9 λ 10 ) noise ASE output variable S output variable C jitter tolerance D clock_module D OR_module D LCAD_module
23 Methodology Applications Application State Machine Device
24 How? matching the speed of electronics to optics interlacing
25 How? Optical Buffer algorithm P P P M M M S1 S0 HD FIFO Element S1 S0 HD FIFO Element... S1 S0 HD FIFO Element B C input output A D
26 Logic Simulations
27 Multiplexer and Demultiplexer t 0 λ 0 Multiplexer t 1 t n λ 1 λ n λ n t n λ 1 t 1 λ 0 t 0 λ T t n λ T λ T t 1 t 0 t 0 t 1 λ 0 λ 0 λ T data out λ 1... λ 1 t n λ n λ n frame sync shutter Sagnac wavelength to delay converter wavelength converter Sagnac λ 0 λ 0 λ 0 t n t 1 t 0 t n t 1 t 0 t n Demultiplexer λ T λ T λ T λ 1 t n t 1 t 0 λ 1 t n t 1 t 0 λ 1 t 1 λ n λ n λ n t n t 1 t 0 λ 0 t n t 1 t 0 t n t 1 t 0 t 0 λ 0 λ 0 t n λ 1... λ 1 λ 1 t 1... λ n λ n λ n t 0 data in wavelength converter Sagnac delay to wavelength converter fram e sync shutter Sagnac
28 Why? Overview Background What and How methodology optical state machines Why smart speed power size cost Historical Perspective Summary
29 Why? Smart State Machines = Logic + Delay = Logic + Memory
30 Why? Speed Greater than 1 Tb/s electronics 50 Gb/s optics 1,250 Gb/s optics = 25 x electronics 1.28 Tbit/s-70km OTDM transmission using third- and fourth-order simultaneous dispersion compensation with a phase modulator, M. Nakazawa, T. Yamamoto, and K.R. Tamura, Electronics Letters, vol. 36, no. 24, pp. 2027, Nov. 23, 2000.
31 Why? Power, Size, and Cost are independent of the data rate energy energy 10 Gb/s 1 sec 1 sec Power consumption of a Sagnac gate The power consumption of the Sagnac gates, passive components, and optical amplifiers are independent of the data rate. 100 Gb/s The size of the Sagnac gates, passive components, and optical amplifiers are independent of the data rate. The cost of the Sagnac gates, passive components, and optical amplifiers are independent of the data rate. 400 Gb/s
32 Why? Electronics vs. Optics optics vs. electronics optics power electronics optics power bits / sec bits / sec size electronics size bits / sec optics bits / sec cost electronics cost bits / sec optics bits / sec
33 How? Power as a function of data rate and percent of electronics Optical crossbar with electronic control (10% optical & 90% electronic) (1999) power data rate Add / Drop Packet Ring (30% optical & 70% electronic) (2001) power data rate Optical state machines (100% optical) (2005) power data rate
34 Historical Perspective Overview Background What and How methodology optical state machines Why smart speed power size cost Historical Perspective Summary
35 Historical Perspective Enabling Experiments 2.5 Gb/s digital loop (Bell Labs 1993) 1.6 Tb/s digital oscillator (Bell Labs 1993) % transmission Intensity relative delay (ps.) Jitter Tolerance (Bell Labs 1992) Non-linear Transfer Function (Bell Labs 1990)
36 Historical Perspective Methodology and Tools Application logic State Machine Device plumbing & timing methodology plumbing tools
37 Historical Perspective Optical Time Domain Multiplexing Bell Labs 1990 not 2.5 Gb/s British Telcom 1995 not wireless NTT 2000 not WDM
38 Historical Perspective Technological Evolution optical state machines physics EE CS
39 Historical Perspective Paradigm Shifts control electronic > optical multiplexing wavelength division > time division switching circuit > packet granularity circuit > bit representation analog > digital data rate / bandwidth electronic > optical
40 Historical Perspective 20 / 20 Hindsight Electrons (fermions) are for control while photons (bosons) are for communications (incorrect inference) There is no such thing as optical memory (closed minded) Wavelength division multiplexing (WDM) is superior to time division multiplexing (TDM) (lack of perspective) Optics is analog while electronics is digital (ignorance) In an optical switch the same photon must come out the other end (ignorance) There is no need to go faster than electronics since all the inputs are electronic (lack of imagination)
41 Summary Overview Background What and How methodology optical state machines Why smart speed power size cost Historical Perspective Summary
42 Summary Technological Advantages Smart logic and memory Speed > 1.0 Tb/s Power is independent of the Clock Rate Size is independent of the Clock Rate Cost is independent of the Clock Rate
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