An Optical Parallel Adder Towards Light Speed Data Processing

Transcription

1 An Optical Parallel Adder Towards Light Speed Data Processing Tohru ISHIHARA, Akihiko SHINYA, Koji INOUE, Kengo NOZAKI and Masaya NOTOMI Kyoto University NTT Nanophotonics Center / NTT Basic Research Laboratories Kyushu University

2 History of OpEcal CompuEng Opt. computers Based on optical filters Intensively studied in 970 s, but CMOS computers are much more superior to the optical computers Based on optical transistors Shadowgram Tanida, Ichioka, JOSA 73, 800 (983) Hard to miniaturize SEED (Bell Labs.) Miller et al. OQE 22, S6 (990) Lower performance than CMOS Opt. interconnect Electronics computation Optics communication In 2000 s, optical interconnects got into computers Intel, IBM, PETRA lead investigation (Si photonics) System in Package Only for interconnect? CPU Optical interconnect 2

3 Beyond OpEcal CommunicaEon Chip-to-chip interconnect DRAM Intra-rack optical interconnect Inter-rack optical interconnect CPU/GPU Network-on-Chip Our focus in this talk NoC Optical accelerator Optical accelerator Optical accelerator Optical Interface Optical data-path Functional Unit CMOS CPU Optical accelerator Optical accelerator RAM Functional Unit 3 3

4 Photonic Chrystal OpEcal Pass Gate Electrical Voltage Control : pass / 0: cross Targeting 00 µm or less ~ ps Optical signal Optical signal Directional Coupler Photo Detector p-inp Electrical Voltage : pass / 0: block P n-in 8 µm.55 µm light L =.7 µm n-inp p-inp : block / 0: pass InAlAs < ps L =.3 µm C = 0.6 ff 4

5 Why OpEcal PG for Data Path? Good at data path operation CMOS Delay FO4 ü Light speed operation Good at serial connection (light speed) ~ ps NOT good at cascade connection ( & switching delay involved) ~ 25 ps 0 ps ü Good at pass/cross propagations (XOR and MUX) XOR MUX B B A A B A B All optical XOR A B π A B A B S S A+S B S A+S B 5

6 OpEcal Parallel Adder Example Computation can be done by just passing the optical signal through the pass gates Electrical control signal X Optical input signal Optical input Optical input 2 Optical output Optical output 2 Y Optical pass gate Carry propagation CI 0 CI CI 2 CI3 Optical signal NOT XOR S 0 st digit Electrical signal NOT XOR Electrical signal S NOT XOR Electrical signal S 2 2 nd digit 3 rd digit 6

7 ArithmeEc OperaEon with OPG XOR/MUX-dominant data-path operation ü Parallel Adder, Multiplier, and Barrel Shifter etc. Full Adder (AOI logic) Full Adder (modified) Full Adder (OPG logic) X Y CI CO S X Y CI MUX CO S X Y CI π not MUX CO S ü Parallel adder as a first step Ø Can be constructed with serial connections only 7

8 OpEcal Full Adder Library Cells in OptiSPICE simulator ( O p t o e l e c t r o n i c circuit simulator) X Y Full Adder (AOI logic) CI MUX CO S X Y CI Full Adder (OPG logic) MUX π not CO S : through 0:cross All optical XOR X Y X Y (Electrical) X i π π Phase shifter Y i X MUX conversion Y splitter C i 99 X MUX C i+ X coupler C i 99 XOR C i+ S i 8

9 Design and EvaluaEon: 6-bit Adder π : through 0:cross Phase shifter conversion X i Y i C i 99 π Light propagation X Y (O) X Y (E) X (O) X (O) Single Stage C i+ Y splitter C i+ X coupler C i 99 S i X 0 Y 0 X Y X n- Y n- C 0 C C 0 C FA S 0 FA C 2 C 2 C n- C n- FA S S n- 9

10 OpESPICE SimulaEon Results Ø Optoelectronic Circuit Simulator (HSPICE engine) Ø Light-speed parallel adder operation confirmed Per digit delay: ~ps, Initial and switching delay: ~25ps Output Power [µw] Y X st digit Y Input signal st digit SUM st digit X Input signal LSB 20 ps 6 th digit SUM Time [ps] 0

11 6-bit CMOS Adder as Comparison 6 nm High Performance CMOS Technology PTM X 0 Y 0 CO X Y CO X 5 Y 5 CO Output Voltage [V] CI st digit SUM S ps S Single digit carry propagation delay =2.7 ps X 0 input wave form 6 th digit SUM Time [ps] CI S 5

12 Comparison 6-bit parallel adder is designed with OPG Light-speed operation is confirmed Per digit delay: OPG ~ ps, CMOS 22 ps 6-bit total delay: OPG ~40 ps, CMOS 350 ps Per digit delay C 0 X 0 Y 0 CMOS 22 ps OPG ~ ps C X Y C 0 C FA S 0 FA C 2 C 2 S 6-bit total delay C 5 C 5 X 5 Y 5 FA CMOS 350 ps OPG ~40 ps S 5 2

13 Wavelength Division Multiplexing Exploit WDM for reducing the circuit size λ represents carry, λ 2 represents carry bar X i π X Y (optical) X Y (electrical) if (X Y=) Y i l or C i+ or C i+ C i 99 Only λ 2 is given to the st digit carry input l 2 X X or or Wavelength selective splitter S i if (X+Y=0) 3

14 OpESPICE SimulaEon Results Ø Different wavelengths for carry and carry bar This structure reduces RC delay in electric control signal Per digit delay: ~ps, Initial and switching delay: ~25ps Output Power [µw] Y X st digit Y Input signal st digit SUM st digit X Input signal LSB 20 ps wave becomes steeper 6 th digit SUM Time [ps] 4

15 Related Work Parallel adder based on shared BDD T. Asai, Y. Amemiya, and M. Kosiba, A Photonic-Crystal Logic Circuit Based on the Binary Decision Diagram," in Proc. of IWPECS,T4-4, March % loss per digit x 3 C 3 S 3 S 2 S S 0 x 3 Max fan-out = 4 Large power loss y 3 y 3 x 2 y 2 y 2 C 2 C y 3 y 3 x 2 y 2 y 2 C 2 C X 2 y 2 y 2 Serial connections = # digits x 2 Large power loss x y y x 0 y 0 C 0 x y y x 0 y 0 y 0 C 0 X y y x 0 y

16 Summary 6-bit parallel adder is designed with OPG Light-speed WDM operation confirmed Per digit delay: OPG ~ ps, CMOS 22 ps 6-bit total delay: OPG ~40 ps, CMOS 350 ps Power loss is an issue to be resolved Per digit power loss ~20% Future work Extend this to more complicated functions 6

17 Acknowledgement This work is partly supported by CREST (Core Research for Evolutional science and Technology) of JST (Japan Science and Technology Corporation) 7

18 Backup 8

19 Results of OpESPICE SimulaEon Ø Optoelectronic Circuit Simulator (HSPICE engine) Ø Light-speed parallel adder operation confirmed Per digit delay: ~ps, Initial and switching delay: ~0ps 8-bit CMOS adder with 6nm HP PTM: 74 ps Normalized Power.0 carry 0 th digit carry carry 7 th digit Input signal 0 th digit Carry bar 7 th digit Time [ps]

20 Power Loss in Adder OperaEon Power halves every 2 digits π X Y (O) X Y (E) % loss in carry Power splitter loss X i Y i C i 99 X X Pass gate insertion loss C i+ C i+ db loss 99% loss in sum C i X 0 Y 0 99 X Y S i X n- Y n- C 0 C C 0 C FA S 0 FA C 2 C 2 C n- C n- FA S S n- 20