Behavior of Phase-Locked Loops
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1 Phase-Locked Loops Behavior of Phase-Locked Loops Ching-Yuan Yang National Chung-Hsing University Department of Electrical Engineering
2 Mathematical Model of VCOs 6-
3 Phase of Signals V0 = Vmsin 0t V = Vmsin (t) V = Vmsin (t) The frequency can be defined as the derivative of the phase with respect to time: d dt dt 0 6-
4 Binary frequency modulation (Frequency shift keying) 6-3
5 Mathematical Model of VCOs VCO transfer function: For a VCO, out = 0 + KVCO Vcont, we have Vout (t ) Vm cos (t ) Vm cos 0t K VCO Vcont dt 0 The term, K VCO Vcont dt, is called excess phase, ex. That is, the VCO operates as an ideal integrator, providing a transfer function: ex K (s ) VCO Vcont s A VCO can operate as a frequency modulator: = 0 + KVCOV = 0 + KVCOV 6-4
6 Assume Vcont = Vmcos mt, we have Vout (t ) V0 cos 0t KVCO Vcont dt V V V0 cos 0t cos KVCO m sin mt V0 sin 0t sin KVCO m sin mt m m If Vm is small enough that KVCOVm/ m <<, then Vout (t ) V0 cos 0t V0 sin 0t K VCO V0 cos 0t Vm m sin mt K VCOVmV0 cos( 0 m )t cos( 0 m )t m sidebands When a VCO operates in the steady state, the control voltage experiences very little variation. It reveals that the variation of the control voltage with time may create unwanted components at the output. 6-5
7 Jitter/Noise in PLLs 6-6
8 Jitter in PLLs Ideal waveform Jittery waveform 6-7
9 Jitter in PLLs (cont d) Slow-jitter waveform Fast-jitter waveform Effect of input jitter out n (s ) in s n s n out n ( s z ) (s ) in s n s n Low-pass characteristic. Slow jitter at the input propagates to the output unattenuated but fast jitter does not. Effect of VCO jitter out s (s ) in s n s n High-pass characteristic. Slow jitter components generated by the VCO are suppressed but fast jitter components are not. 6-8
10 Jitter in PLLs (cont d) Transfer functions of jitter from input and VCO to the output Effect of VCO jitter: If VCO changes slowly (e.g., the oscillation period drifts with temperature), then the comparison with in = 0 (i.e., a perfectly periodic signal) generates a slowly varying error that propagates through the LPF and adjusts the VCO frequency, thereby counteracting the change in VCO. If VCO varies rapidly, (e.g., high-frequency noise modulates the oscillation period), then the error produced by the phase detector is heavily attenuated by the poles in the loop, failing to correct for the change. In summary, depending on the application and environment, one or both sources may be significant, requiring an optimum choice of the loop bandwidth. 6-9
11 Noise in PLLs Phase noise n(t) x(t) = A cos( ct + n(t)] If the input signal or the building blocks of a PLL exhibit noise, then the output signal will also suffer from noise. Phase noise at input Low-pass filter out n ( s / z ) (s) in s n s n 6-0
12 Noise in PLLs (cont d) Phase noise of VCO out s (s) VCO s n s n The VCO phase noise experiences a high-pass transfer function as it appears at the output of a PLL. Thus, increasing the bandwidth of the PLL can lower the contribution of the VCO phase noise. High-pass filter 6-
13 Noise sources of the PLL vco o phase noise Kvco s d N Loop Filter PFD/CP Main Divider x VCO KPD Reference Divider ZLF(s) current noise R ref inp voltage noise Vnf pd The rms phase noise power density of the loop s output signal is denoted o(fm). o ( f m ) olp ( f m ) ohp ( fm ) The output phase noise power density: Low-pass transfer function 6- High-pass transfer function
14 - Total phase noise at the output of the PLL Total phase noise noise power spectral density: o ( f m ) N eq ( f m ) H ( j f m ) vco ( f m ) lf ( f m ) THP ( j f m ) (Low pass) rad / Hz (High pass) Typical phase noise spectral plot for PLL: S out( ) Power (dbm) Phase noise of the output VCO only Input only c Phase Noise in dbc/hz log ( ) 6-3 Loop Bandwidth Frequency
15 - General bandwidth requirements Low PLL System Jitter Wide Loop Bandwidth Large Input Jitter Reduction Narrow Loop Bandwidth Fast Locking Wide Loop Bandwidth Phase Fluctuation Tracking Adaptive Loop Bandwidth Control There are Trade-offs: No single good solution for All 6-4
16 More attenuation of unwanted spurs with the 3 th-order filter ip Z LF (s) R R3 C Z LF ( s ) V cont s z s(c C )( s p ) Z LF ( s ) sc 3 Z LF ( s ) Z LF ( s ) R3 sc 3 C3 C Assume C 0C3, we have The added attenuation from the low-pass filter: ATTEN 0 log[( f ref p 3 ) ] z p3 ATTEN 0 0 f ref c ( p p 3 ) tan m ( p p 3 ) ( p p 3 ) p p 3 c ( p p 3 ) p p 3 tan m ( p p 3 ) where p 3 R3C 3 (low-pass pole) C p z K pd K vco ( ) c z c N ( c p )( c C C z p 6-5 and R z p 3 ) C (similar to the nd-order filter)
17 - Derivation of C Z LF (s ) sc 3 The impedance of the loop filter: Z LF (s ) Z LF (s ) R3 sc 3 and Z LF (s ) s z s(c C )( s p ) Knowing that C 0C3 and p3 = R3C3 Open-loop gain: K K j z p (s )G (s ) s j PD vco C N j p z j p 3 ( ) tan ( z ) tan ( p ) tan ( p 3 ) 80 (A) Assume z < < p < p3, we have p p3 z m,max: d 0 d ( z ) ( p ) ( p 3 ) z p p3 0 ( z ) (B) ( p p 3 ) p p 3 ( p p 3 ) p p 3 ( p p 3 ) Substituting (B) into (A) gives tan p p 3 tan 0 ( p p 3 ) p p 3 ( p p 3 ) p p 3 Taking the negative root z tan m ( p p 3 ) ( p p 3 ) p p 3 c ( p p 3 ) p p 3 tan m ( p p 3 ) 6-6
18 Phase-Locked Loops Behavior Simulation 6-7
19 Phase detector : PFD three-state PD A A A State I State II State III QA = QB = 0 QA = 0 QB = 0 QA = 0 QB = B B B State diagram A A B B QA QA QB QB A A B B QA QA QB QB Timing diagram 6-8
20 Linear model of 3rd-order PLLs ZLF(s) Loop Filter ip Phase Detector & Charge Pump REF VCO Vcont KVCO s RP KPD C VCO CP Div N s z with z = RP CP and p = RP (CP + C ). Z LF ( s ) s (C P C )( s p ) Divider Loop filter: Open-loop transfer function: GH ( s ) Crossover frequency C Gain margin Phase margin GH ( s ) s j I P KVCO s Z N s (C P C ) ( s P ) I P RP KVCO CP N C P C I K ( j Z ) P VCO N (C P C ) ( j P ) ( ) 80 tan ( Z ) tan ( P ) 6-9
21 Linear model of 4rd-order PLLs Loop Filter Phase Detector & Charge Pump REF ip R3 Vcont VCO C3 KVCO s RP KPD C VCO CP Div N Assume Cp >> C >> C3, Loop filter: Divider s Z with z = RP CP, P RC and P R3C3. Z LF ( s ) sc P ( s P ) ( s P ) Open-loop transfer function: GH ( s ) Gain margin Phase margin I P KVCO s Z N s C P ( s P ) ( s P ) I P RP KVCO N I K ( j Z ) GH ( s ) s j P VCO N C P ( j P ) ( j P ) Crossover frequency sr C ZLF(s) 3 s RR3CCC3 s [RC(C C3) R3(C C)C3] s(c C C3) C ( ) 80 tan ( Z ) tan ( P ) tan ( P ) 6-0
22 Linear model of 4rd-order PLLs ZLF(s) Loop Filter Phase Detector & Charge Pump REF ip R3 Vcont VCO C3 KVCO s RP KPD C VCO CP Div N Divider Design the extra pole p on the top of p by taking p = p. p = R3 C3 =( R3) (C3 / ) with > 0. Crossover frequency Gain margin Phase margin I P RP KVCO N I K ( j Z ) GH ( s ) s j P VCO N C P ( j P ) C ( ) 80 tan ( Z ) tan ( P ) 6-
23 Bode diagram of 3rd-order and 4rd-order PLLs Choose C = 00 Krad/s and pm = 67.5o N = 50, Kv = 50 MHz/V, IP = 00 A, R = 3.4 K, C = 37 pf, C = 6 pf. 6-
24 Simulink behavior simulation of 3rd-order and 4rd-order PLLs 6-3
25 Transient of 3rd-order and 4rd-order PLLs fref = 0 MHz fvco: MHz 3rd-order-order PLL 4rd-order-order PLL 6-4
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