Outline. Introduction Delay-Locked Loops. DLL Applications Phase-Locked Loops PLL Applications
|
|
- Oliver Melton
- 5 years ago
- Views:
Transcription
1 Introduction Delay-Locked Loops DLL overview CMOS, refreshg your memory Buildg blocks: VCDL PD LF DLL analysis: Lear Nonlear Lock acquisition Charge sharg DLL Applications Phase-Locked Loops PLL Applications Outle Delay-Locked Loops 1
2 Clock skew control Clock skew control Why Delay-Locked Loops? IC Int. CLK The DLL automatically nulls the skew between these two pots Q Output pad Ext. CLK Clock pad DLL clock re Clock buffers and terconnects troduce delay External clock DLL delay + Clock buffers + Clock re delay = Clock period Phases 0 and 2π are distguishable Internal clock Phase aligned Output data Output data registers delay Paulo.Moreira@cern.ch Delay-Locked Loops 2
3 DLL Block Diagram 1 st order Delay-Locked Loop functional blocks Voltage Controlled Delay Le (VCDL): Takes the reference clock as an put and delays it by some amount D. The delay D is function of a control voltage D(V control ). Sometimes the control quantity can be a current. In this case we have a Current Controlled Delay Le (CCDL) We will assume that the higher the voltage (or the current) the shorter will be the propagation delay through the delay le. Phase Detector (PD): Compares the phase of the signal at the put and put of the VCDL. Dependg on the type, produces an error signal that: It is proportional to the phase difference between the put and put phases; It just gives an dication on the sign of the phase error (bang-bang detector). Loop filter (LF): Elimates the high frequency components of the error signal: It can be implemented as: An RC low-pass filter An active low pass filter A charge-pump and a capacitor Paulo.Moreira@cern.ch Delay-Locked Loops 3
4 DLL Buildg Blocks We will describe details and possible implementations of the DLL buildg blocks: Voltage Controlled Delay Le (VCDL) Phase-Detector (PD) Loop Filter (LF) All the circuits we will discuss are CMOS circuits. Before proceedg to the circuit details, we need to refresh the basic concepts on the operation of a MOS transistor from the circuit pot of view. CMOS: C: complementary: N and P type transistors M: Metal gate: Polysilicon modern technologies O: Silicon dioxide dielectric S: Semiconductor NMOS: Charge carried by electrons Turned on by gate voltages positive relation to the source PMOS: Charge carried by holes Turned on by gate voltages negative relation to the source Paulo.Moreira@cern.ch Delay-Locked Loops 4
5 CMOS Transistors Simple Model In saturation: Gate-to-source capacitance Voltage controlled current generator between source and dra Lear region: A gate capacitance Voltage controlled resistor between the source and dra Cutoff region: Gate capacitance Infite resistance between source and dra Circuit: Dra of a transistor is loaded by the gate of the next Next gate represents a capacitance to the previous transistor. Dra current used to charge (or discharge) the gate capacitance of the followg transistor I ds C W μ ox V 2 L gs T ( V ) 2 In saturation D G I ds D G V ds V gs C gs I V ds V gs S S S S Paulo.Moreira@cern.ch Delay-Locked Loops 5
6 The Voltage Controlled Delay Le (VCDL) Clock Voltage Controlled Delay Le Clock Phase Detector Error Signal 1 st order f Delay Control Paulo.Moreira@cern.ch Delay-Locked Loops 6
7 Intrsic Delay CMOS Circuits Ideal MOS Time it takes to discharge C from V dd to V dd /2 VIN VGS I (VGS-VT) 2 C Δt = C I V 2 dd μ C C V ox Assumg V T 0 Assumg V T 0 dd L W V dd VIN 0 t VOUT V dd delay 50% level 0 t Paulo.Moreira@cern.ch Delay-Locked Loops 7
8 Common-source configuration: CMOS Inverter NMOS can only discharge (pull-down); PMOS can only charge (pull-up); V dd Both P and N transistors are thus needed. CMOS verter: No static power consumption. Mobility electrons > mobility holes: PMOS transistors are weaker than NMOS. To compensate: C L W p /W n = μ n /μ p 3/1 (for L n = L p, typically mimum length digital circuits). What s the best way to control the verter delay: V dd? C L? None of the two! Paulo.Moreira@cern.ch Delay-Locked Loops 8
9 The Starved Inverter V dd I up Controllg I up controls the chargg time Δt up = C I up V 2 dd Switchg transistor not limitg C L Controllg I down controls the dischargg time Δt down = C I down V 2 dd I down Delay as short as possible: I up = I down = max Switchg transistors limitg. Δt = C I V 2 dd C μ C V ox dd L W Paulo.Moreira@cern.ch Delay-Locked Loops 9
10 Biasg the Starved Inverter V dd 1:N I up I bias = I up /N C L V control I down Paulo.Moreira@cern.ch Delay-Locked Loops 10
11 Makg Sure it Will Work Can we run the starved verter fitely slow?. No, must have: trise = tfall < m(pulse width) V dd put Pulse too short put Filtered by the starved verter I up C L Pulse wide enough put 1 0 V control I m put 1 0 Pulse appears delayed at the put I m prevents t rise and t fall from becomg too long Paulo.Moreira@cern.ch Delay-Locked Loops 11
12 Voltage Controlled Delay Le V dd In In a a real real implementation implementation these these nodes nodes troduce troduce poles poles the the VCDL VCDL transfer transfer function. function. Care Care must must be be taken taken so so they they are are at at high high frequencies frequencies not not to to disturb disturb the the DLL DLL dynamic dynamic behavior. behavior. I up V control I m t d t f(v control ) = vcdl V control d = f(v control ) = K vcdl V control (lear approximation valid around the workg pot) (lear approximation valid around the workg pot) Paulo.Moreira@cern.ch Delay-Locked Loops 12
13 Differential Delay Cell Advantages: Insensitive to common-mode; Signal and the Inverted signal available. Constant power consumption: low switchg noise Disadvantages: Consumes static power; Half of the tail current used to charge/discharge the load; Differential to sgle ended converter required to terface with CMOS logic V dd I up V control I m 1 2 Paulo.Moreira@cern.ch Delay-Locked Loops 13
14 The Phase Detector (PD) Clock Voltage Controlled Delay Le Clock Phase Detector Error Signal 1 st order f Delay Control Paulo.Moreira@cern.ch Delay-Locked Loops 14
15 XOR: A Simple Phase Detector put Output lags the put by π/2 (T/4) VCDL put signal VCDL put signal error put error Φ err = <Phase-detector put> Φ err = <Phase-detector put> <error> = ½ V dd Output lags the put by π/4 (T/8) put put error <error> = ¼ V dd put Output lags the put by 3π/4 (3T/8) The The phase-error phase-error or or phase phase difference difference is is not not the the stantaneous stantaneous value value of of the the phase phase detector detector put put but but its its average average value. value. That That is is one one of of the the reasons reasons why why the the loop-filter loop-filter is is required. required. put error <error> = ¾ V dd Paulo.Moreira@cern.ch Delay-Locked Loops 15
16 XOR Uncertaty VCDL put signal VCDL put signal error Output lags the put by π/4 (T/8) put Output lags the put by 3π/4 (3T/8) put put error Output leads the put by π/4 (T/8) put put error Output leads the put by 3π/4 (3T/8) put put error put error The phase detector can not distguish between these two conditions. Neither between these two conditions. Delay-Locked Loops 16
17 Non-Lear and Limited Range <error> [Volts] K pd dv = < 0 dφ ½V dd V dd K pd dv = > 0 dφ <phase error> [rad] 0 π ¾ π 2π Output phase Leads 0 π/2 Output phase Lags Slope: K pd, [V/rad] or [V/s]; Slope sign depends on the operation region: Negative ga Positive feedback; Positive ga Negative feedback; Ga version occurs at teger multiples of π; XOR phase detector must work with a static phase difference of π/2; For the XOR, a phase difference equal to π/2 is zero error phase ; The type of phase detector dictates the static phase difference. Paulo.Moreira@cern.ch Delay-Locked Loops 17
18 XOR Non-Idealities XOR ripple is at twice the operation frequency: Advantage for RC filterg; A problems if a charge-pump filter is used. error XOR drawback: sensitive duty-cycle; Different duty-cycles Same phase difference error Different averages Paulo.Moreira@cern.ch Delay-Locked Loops 18
19 More Non-Idealities error error error Ga saturation (for 25% duty-cycle) 0 π Duty-cycle distortion also causes saturation of the phase detector transfer function Paulo.Moreira@cern.ch Delay-Locked Loops 19
20 The DFF Phase Detector VCDL put signal D Q error Sign formation only: No phase error magnitude formation; It distguishes early or late only; VCDL put signal It is called a bang-bang phase detector. Output lags the put put Loop operation: When lock the phase change occurs virtually every clock cycle and the average phase error becomes zero. Its advantages are: put error simplicity of operation; Operation possible at the maximum FF operation frequency; Mimum pulse width 1/f; Output leads the put put The phase range spans from π to +π. Insensitive to duty-cycle distortion the CK put (however: duty-cycle distortion on the D put creates asymmetry the transfer function) put v dd error π 0 π Paulo.Moreira@cern.ch Delay-Locked Loops 20
21 DFF PD Implementation Carefully design one. SR2 Dummy gate SR3 To avoid phase errors and Metastability: Internal nodes same fan; Gates the same drivg capability; Every two gates the same latch same fan-; The latch SR1 is critical should reach its fal state as fast as possible; Decision a fraction of the reference clock period Otherwise creased jitter. D Lay is critical for operation: Device matchg; Dummy gate SR1 Large area devices; Lay as symmetrical as possible; Keepg the wire loadg identical on correspondg nodes. Paulo.Moreira@cern.ch Delay-Locked Loops 21
22 The Loop Filter (LF) Clock Voltage Controlled Delay Le Clock Phase Detector Error Signal 1 st order f Delay Control Paulo.Moreira@cern.ch Delay-Locked Loops 22
23 A simple loop filter: RC Low-pass VCDL put signal VCDL put signal VCDL control voltage V control = K pd <phase error> V control = K pd <phase error> K pd = V dd /π [V/rad] K pd = V dd /π [V/rad] The simplest possible filter is an RC low-pass filter; Output voltage controls the VCDL. Filter bandwidth: a few or several decades lower than f ref ; In steady state conditions, the filter DC put voltage is proportional to the phase error. Advantage: Simplicity Disadvantage: Corrective action can only be achieved at the price of a phase offset. The phase offset value depends on the phase detector ga: Small ga K d large phase offset! Phase detector ga is dictated by V dd Paulo.Moreira@cern.ch Delay-Locked Loops 23
24 Fite DC Ga is a Disadvantage T 1 π/2 T 2 > π/2 T 2 < T 1 <V control > = ½ V dd <V control > > ½V dd VCDL for a reference signal with period T 1. propagation delay T 1 /4 achieved exactly at V dd /2; Reference period changed to T 2 < T 1 To run with a shorter propagation delay a higher VCDL control voltage is necessary; With the RC filter, higher voltage can only be obtaed at a cost of an extra phase lag; This is undesirable it troduces an error the VCDL propagation delay. The error can be reduced by creasg the open-loop ga: K = K pd K lf K vcdl. (K lf is the filter ga, 1 for the passive RC filter). Paulo.Moreira@cern.ch Delay-Locked Loops 24
25 Improvg the RC Filter Increasg the open-loop ga reduces the phase offset: Increasg Vdd creases K pd (K pd = V dd /π): Not a practical solution; The ga crease would be small. More effective: Add a ga stage between the filter and the VCDL: Increase the ga of the VCDL (K vcdl ) Draw backs: Small V cnt fluctuations converted large variations of the VCDL propagation delay (jitter); Secondary poles might result a badly behaved transient response or even stability. The XOR phase detector and the passive RC filter are thus not the favorite choice for tegrated DLLs VCDL G To To reduce reduce the the phase phase offset, offset, add add ga ga or or crease crease K vcdl vcdl Paulo.Moreira@cern.ch Delay-Locked Loops 25
26 Capacitor: A Current Integrator Consider what happens when a current is fed to a capacitor: The voltage across the capacitor (V) is simply the time tegral of the current (I) beg fed to the capacitor: V t 1 = C () t I() t dt + V0 0 We can thus easily tegrate the phase error if we feed to a capacitor a current that is proportional to the phase error measured by the phase detector: t Φ 0 err t I ( t) Φ ( t) 1 C () dt I() t t 0 err dt I V Paulo.Moreira@cern.ch Delay-Locked Loops 26
27 Active Loop-filter: Charge-Pump + Capacitor I cp VCDL D Q late V control V control VCDL early I cp V cap error Late = lag sign(φ err ) = 1 Early = lead sign(φ err ) = -1 V t Icp ( t) = Vcap( t) = sign( Φerr ( t)) dt V C control Paulo.Moreira@cern.ch Delay-Locked Loops 27
28 Charge-Pump for Bang-Bang Detector M1: current sk, M2: current source; M3 and M4: switches: Alternatively closed and opened: V dd Current always flows to or of the filter capacitor (never directly between V dd and ground); M2 Reference leads: M4 closed, M3 opened Control voltage creases. VCO leads: error M4 V control M3 closed, M4 opened Control voltage decreases Keep sk and source currents well matched: M3 C mimize static phase error; Charge sharg effects need be controlled (discussed later). I cp M1 Paulo.Moreira@cern.ch Delay-Locked Loops 28
29 The Delay-Locked Loop Clock Voltage Controlled Delay Le Clock Phase Detector Error Signal 1 st order f Delay Control Paulo.Moreira@cern.ch Delay-Locked Loops 29
30 Bang - Bang Operation Overview D Q Late Q Early V control Early Late Late Late Early Late Paulo.Moreira@cern.ch Delay-Locked Loops 30
31 Bang-Bang Operation Tradeoffs Trackg jitter: The loop trackg behavior troduces jitter: In lock put phase constantly oscillates back and forward around the phase of the reference signal: It is a result of no phase error magnitude formation. Possible to reduce the loop trackg jitter to significant levels; Other jitter sources: Thermal and shot noise; Substrate noise; Power supply noise. Tradeoffs: Optimization for low-jitter: Increase the loop-capacitor C; Decrease: I cp and K vcdl. Optimization for fast-lock: Decrease the loop-capacitor C; Increase: I cp and K vcdl. Optimization for low-jitter and fastlock: It is possible to optimize for both: Use a large I cp durg lock-acquisition; Use a small I cp after lockg. Optimization agast substrate and power supply noise: Same as for fast-lock; Paulo.Moreira@cern.ch Delay-Locked Loops 31
32 DLL: lear analysis Loop filter: Charge-pump + capacitor. Phase detector: Considered Lear signal proportional to the phase error. Phase detector put: Pulse of duration proportional to the phase error (e.g. ΔT(high)-ΔT(low) an XOR phase detector). Contuous time approximation: Valid for bandwidths a decade or more below the operatg frequency. (Keep md that DLLs are fact nonlear devices.) A sgle pole is present the loop filter: The DLL is a 1 st order network. Combation charge-pump and loopcapacitor: Acts as a perfect tegrator; Modeled as an tegrator. VCDL PD dt Paulo.Moreira@cern.ch Delay-Locked Loops 32
33 DLL Modelg Choice of variables: DLL response formulated terms: Input delay; Output delay; Output delay: The VCDL delay: D O (t) or D O (s) Input delay: The delay to which the phase detector compares the put delay: D I (t) or D I (s) Note that D I (t): It is phase detector dependent; It s frequency dependent; Δt DI ( s) DO ( s) D O (s) PD = T Δt T T Phase detector put is active durg this fraction of the reference period dt V cont Δt = T Icp s C D O ( s) = K V ( s) vcdl VCDL cont (s) V cont Paulo.Moreira@cern.ch Delay-Locked Loops 33
34 DLL Transfer Function D O (s) PD 1 s Phase error D O ( s ) = [ D ( s ) D ( s )] I T O I cp s C K vcdl Charge pump Duty-cycle Control voltage VCDL propagation delay H ( s ) = D D O I ( s ) ( s ) = 1 1 s + ω n The The closed closed loop loop transfer transfer function function is is 1 1 st st order order It It is is characterized characterized by by the the natural natural frequency frequency ω n n ω n = I cp T K C vcdl Paulo.Moreira@cern.ch Delay-Locked Loops 34
35 The DLL is a 1 st Order System ω n = I cp T K ω n naturally tracks the reference frequency. C vcdl D fal d D( t) dt t =0 = D fal τ Designg a DLL it is equivalent to choose its natural frequency ω n : Choose I cp and C. K vcdl fixed by the VCDL design and technology parameters (some degree of control but not much). T is fixed by the operation frequency/frequencies. Sce the system is 1 st order it is herently stable: Make sure the higher order (unwanted but unavoidable poles) are at least 10 times higher that ω n. τ = 1 ω n The closed-loop behavior is similar to that of a 1 st order low-pass RC filter: Settlg to 2% t 4τ Settlg to 0.1% t 7τ Fast settlg requires large ω n : Trades off agast low trackg jitter. ω n might start approachg the higher order poles. t Paulo.Moreira@cern.ch Delay-Locked Loops 35
36 DLL Design The parameters: I cp C ω n = K vcdl are technology, temperature and supply voltage dependent ω n would track the operation I cp T K C frequency (i.e. proportional to 1/T) if the other parameters were absolutely constant: Self-biasg techniques can make ω n track the operation frequency over several decades: see Maneatis 1996 vcdl Example: F = 100 MHz T = 10 ns I cp = 1 μa C = 100 pf K vcdl = 2 ns/v This leads to: ω n = 2 krad/s τ = 0.5 ms Notice that: The DLL bandwidth is many orders of magnitude lower than the operation frequency. When locked to a low jitter clock signal this PLL will display low trackg jitter. A VCDL, when subjected to substrate or power supply noise, will generate jitter. Under such circumstances, a DLL with such a low bandwidth will be effective trackg the put phase and thus suppressg its own jitter. Paulo.Moreira@cern.ch Delay-Locked Loops 36
37 Bang-Bang DLL Nonlear Analysis When a DLL uses a DFF as the phase detector, the contuous time approximation can not be used. Simple expressions can be found for: The response to a period step; The trackg jitter. Phase step: The new period is 2/3 T i < T f < 2 T i : DLL will rega lock to the new phase; The VCDL delay will ramp to the new value. The new period is side the above bounds: The Phase-Detector will give the wrong phase formation and the DLL will lose phase lock. Period T itial d D( t) dt = K Reference The DLL will try to catch the new period at a rate given by: dv dt control vcdl = Units: [rad/s] or [s/s] VCDL K vcdl I C cp T fal t Example: Usg the previous example the trackg slope is: 20 ns/ms Paulo.Moreira@cern.ch Delay-Locked Loops 37
38 Frequency Step f 2 > f 1 T 1 The DLL is locked to the reference signal (period T 1 ) T 2 < T 1 Phase is detected late, the VCDL delay is gog to be decreased. Immediately after the frequency step (period T 2 < T 1 ) the VCDL delay is too big and the PD will activate the late signal until the de VCDL propagation delay becomes equal to T 2 VCDL put period VCDL propagation delay VCDL D Q Late Q Early C.P. Paulo.Moreira@cern.ch Delay-Locked Loops 38
39 Frequency Step f 1 > f 2 T 1 The DLL is locked to the reference signal (period T 1 ) T 2 > T 1 Immediately after the frequency step (period T 1 < T 2 ) the VCDL delay is too short and the PD will activate the early signal until the de VCDL propagation delay becomes equal to T 2 Phase is detected early, the VCDL delay is gog to be creased. VCDL D Q Late VCDL put period VCDL propagation delay Q Early C.P. Paulo.Moreira@cern.ch Delay-Locked Loops 39
40 Frequency Step: Limit Values T 1 T 1 T 2 T 2 If T 2 < 2 / 3 T 1 the phase detector will activate the early put stead of the late. The delay will crease stead of decreasg. If T 2 > 2 T 1 the phase detector will activate the late put stead of the early. The delay will decrease stead of creasg. Paulo.Moreira@cern.ch Delay-Locked Loops 40
41 T Bang-Bang Trackg Jitter Jitter: Uncertaty on the position of the fallg and risg edges. Seen a scope as thick traces on the risg and fallg positions. Jitter Ideally every clock cycle the phasedetector should alternate between an early and a late decision. In practice, due to charge-pump unbalance or jitter, it is very likely that the PD decision will be frequently mataed durg two consecutive clock cycles to either side. The mimum P-P trackg jitter is thus given by: d D( t) 4 T = 4 K dt vcdl I cp C T late early I ΔVcont = 4 C cp T ΔV cont Example: Usg the trackg slope from the previous example: J pp = 4 (20 ns/ms) (10 ns) J pp = 0.8 ps The trackg jitter can be thus made to be very small. The jitter is likely to be domated by thermal, supply and substrate noise. Paulo.Moreira@cern.ch Delay-Locked Loops 41
42 DLL Lock Acquisition Typical Bang-Bang DLL startup procedure: 1. Set the VCDL to its mimum value (maximum control voltage) 2. Force the VCDL delay to crease until the phase detector gives a consistent early dication (e.g. 32 consecutive early detections) 3. Once the PD consistently dicates early, pass the control of the loop to the phase detector which will fally take the DLL to lock. 1 st phase VCDL set to its mimum delay Here the PD wrongly dicates late 2 nd phase Here, due to jitter, the PD sometimes gives the correct and sometimes the wrong dication 3 rd phase Paulo.Moreira@cern.ch Delay-Locked Loops 42 The PD is now a safe zone, it correctly and consistently dicates early.
43 Charge Sharg Charge-pumps perform almost like ideal tegrators however charge sharg might degrade their performance. This node charges to V dd when M4 is open V dd M2 When M4 closes V control jumps of: ΔV cont Cd 2 = C + C d 2 ( V dd V cont ) late M4 M3 C d2 V control C When M3 closes V control jumps of: ΔV cont Cd1 = C + C d1 V cont Notice that: The voltage jump is proportional to the control voltage itself; proportional to C d1 and C d2; verse proportional to C; (usually C>> C d1 or C d2 ): I cp M1 C d1 Example: If C = 100 pf, C d1 = 10 ff and V control = 1V: ΔV control = -100 μv Compare with: I cp T/C = 100 μv This node discharges to gnd when M3 is open Paulo.Moreira@cern.ch Delay-Locked Loops 43
44 Charge Sharg Control V dd Charge sharg is elimated. I cp M2 M4 Clock feed-through is present through C gd of M5 and M6. However the voltage swg at the gate of these transistors is relatively small M6 late V control I cp M3 M1 M5 C Voltage Voltage on on this this node node never never rises rises much much above above V dd -V th. So turn-on is relatively fast. dd -V th. So turn-on is relatively fast. Voltage Voltage on on this this node node never never drops drops much much below below V th. So turn-on is relatively fast. th. So turn-on is relatively fast. RC time constant Paulo.Moreira@cern.ch Delay-Locked Loops 44
45 Delay cha feed through Parasitic C dg troduces ripple on the control les. In lock the raisg and fallg edges effects cancel each other. V dd I up To mata symmetry, buffer the dummy cell control les. V control I m Paulo.Moreira@cern.ch Delay-Locked Loops 45
Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)
1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full rail-to-rail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationVLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI UNIT - III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large
More informationChapter 2 MOS Transistor theory
Chapter MOS Transistor theory.1 Introduction An MOS transistor is a majority-carrier device, which the current a conductg channel between the source and the dra is modulated by a voltage applied to the
More informationIntroduction to Phase Locked Loop (PLL) DIGITAVID, Inc. Ahmed Abu-Hajar, Ph.D.
Introduction to Phase Locked Loop (PLL) DIGITAVID, Inc. Ahmed Abu-Hajar, Ph.D. abuhajar@digitavid.net Presentation Outline What is Phase Locked Loop (PLL) Basic PLL System Problem of Lock Acquisition Phase/Frequency
More informationDC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575-604 yrpeng@uark.edu Pass Transistors We have assumed source is
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationSwitched-Capacitor Circuits David Johns and Ken Martin University of Toronto
Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationEE115C Digital Electronic Circuits Homework #4
EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationMotivation for CDR: Deserializer (1)
Motivation for CDR: Deserializer (1) Input data 1:2 DMUX 1:2 DMUX channel 1:2 DMUX Input clock 2 2 If input data were accompanied by a well-synchronized clock, deserialization could be done directly. EECS
More informationEE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
More informationIntroduction to Switched Capacitor Circuits
Microprocessor Laboratory Asian ourse on Advanced LSI Design Techniques usg a Hardware Description Language Manila, The Philippes 25 November 13 December 2002 Introduction to Switched apacitor ircuits
More informationLecture 9: Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM
Lecture 9: Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM Mark McDermott Electrical and Computer Engineering The University of Texas at Austin 9/27/18 VLSI-1 Class Notes Why Clocking?
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " D-Latch " Timing Constraints! Dynamic Logic " Domino
More informationTopics to be Covered. capacitance inductance transmission lines
Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of
More informationSample-and-Holds David Johns and Ken Martin University of Toronto
Sample-and-Holds David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 18 Sample-and-Hold Circuits Also called track-and-hold circuits Often needed in A/D converters
More informationDesign of Analog Integrated Circuits
Design of Analog Integrated Circuits Chapter 11: Introduction to Switched- Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis - Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
More informationSpiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp
2-7.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 2-7.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
More informationHigh-to-Low Propagation Delay t PHL
High-to-Low Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (n-channel) immediately switches from cutoff to saturation; the p-channel pull-up switches from triode to
More informationEE247 Lecture 16. Serial Charge Redistribution DAC
EE47 Lecture 16 D/A Converters D/A examples Serial charge redistribution DAC Practical aspects of current-switch DACs Segmented current-switch DACs DAC self calibration techniques Current copiers Dynamic
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationClock Strategy. VLSI System Design NCKUEE-KJLEE
Clock Strategy Clocked Systems Latch and Flip-flops System timing Clock skew High speed latch design Phase locked loop ynamic logic Multiple phase Clock distribution Clocked Systems Most VLSI systems are
More informationSystem on a Chip. Prof. Dr. Michael Kraft
System on a Chip Prof. Dr. Michael Kraft Lecture 3: Sample and Hold Circuits Switched Capacitor Circuits Circuits and Systems Sampling Signal Processing Sample and Hold Analogue Circuits Switched Capacitor
More informationTiming Issues. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić. January 2003
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić Timing Issues January 2003 1 Synchronous Timing CLK In R Combinational 1 R Logic 2 C in C out Out 2
More informationGMU, ECE 680 Physical VLSI Design 1
ECE680: Physical VLSI Design Chapter VII Timing Issues in Digital Circuits (chapter 10 in textbook) GMU, ECE 680 Physical VLSI Design 1 Synchronous Timing (Fig. 10 1) CLK In R Combinational 1 R Logic 2
More informationCPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville
CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationMOS Inverters. Digital Electronics - INEL Prof. Manuel Jiménez. With contributions by: Rafael A. Arce Nazario
MOS Inverters igital Electronics - INE 407 Prof. Manuel Jiménez With contributions by: Rafael A. Arce Nazario Objectives: Introduce MOS Inverter Styles Resistor oad Enhancement oad Saturated / ear epletion
More informationDesign of CMOS Adaptive-Bandwidth PLL/DLLs
Design of CMOS Adaptive-Bandwidth PLL/DLLs Jaeha Kim May 2004 At Samsung Electronics, Inc. Adaptive-Bandwidth PLL/DLL PLL/DLLs that scale their loop dynamics proportionally with the reference frequency
More informationWhere Does Power Go in CMOS?
Power Dissipation Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More informationE40M Capacitors. M. Horowitz, J. Plummer, R. Howe
E40M Capacitors 1 Reading Reader: Chapter 6 Capacitance A & L: 9.1.1, 9.2.1 2 Why Are Capacitors Useful/Important? How do we design circuits that respond to certain frequencies? What determines how fast
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 17, 2018 I/O Circuits, Inductive Noise, CLK Generation Lecture Outline! Packaging! Variation and Testing! I/O Circuits! Inductive
More informationTopic 4. The CMOS Inverter
Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Topic 4-1 Noise in Digital Integrated
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More information24.2: Self-Biased, High-Bandwidth, Low-Jitter 1-to-4096 Multiplier Clock Generator PLL
24.2: Self-Biased, High-Bandwidth, Low-Jitter 1-to-4096 Multiplier Clock Generator PLL John G. Maneatis 1, Jaeha Kim 1, Iain McClatchie 1, Jay Maxey 2, Manjusha Shankaradas 2 True Circuits, Los Altos,
More informationMiscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an N-Switch, the
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling
More informationLecture 12 CMOS Delay & Transient Response
EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology
More informationCMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators
IsLab Analog Integrated ircuit Design OMP-21 MOS omparators כ Kyungpook National University IsLab Analog Integrated ircuit Design OMP-1 omparators A comparator is used to detect whether a signal is greater
More informationMODULE 5 Chapter 7. Clocked Storage Elements
MODULE 5 Chapter 7 Clocked Storage Elements 3/9/2015 1 Outline Background Clocked Storage Elements Timing, terminology, classification Static CSEs Latches Registers Dynamic CSEs Latches Registers 3/9/2015
More informationLecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Outline Power and Energy Dynamic Power Static Power 6.2 Power and Energy Power is drawn from a voltage source attached to the V DD
More informationIntroduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline
Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and
More informationCOMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos Combinational vs. Sequential Logic In Logic
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
More informationECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI Contents Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort Delay
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
More informationEEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationMOSIS REPORT. Spring MOSIS Report 1. MOSIS Report 2. MOSIS Report 3
MOSIS REPORT Spring 2010 MOSIS Report 1 MOSIS Report 2 MOSIS Report 3 MOSIS Report 1 Design of 4-bit counter using J-K flip flop I. Objective The purpose of this project is to design one 4-bit counter
More informationECEN 610 Mixed-Signal Interfaces
ECEN 610 Mixed-Signal Interfaces Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 014 S. Hoyos-ECEN-610 1 Sample-and-Hold Spring 014 S. Hoyos-ECEN-610 ZOH vs. Track-and-Hold V(t)
More informationHomework Assignment 08
Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationInterconnects. Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. ECE 261 James Morizio 1
Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 James Morizio 1 Introduction Chips are mostly made of wires called interconnect In stick diagram,
More informationDigital Integrated Circuits A Design Perspective
Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures
More informationDigital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman
Digital Microelectronic Circuits (361-1-301 ) Presented by: Adam Teman Lecture 4: The CMOS Inverter 1 Last Lectures Moore s Law Terminology» Static Properties» Dynamic Properties» Power The MOSFET Transistor»
More informationDigital Integrated Circuits
Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Short-circuit current The CMOS inverter :
More informationLecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics
Lecture 23 Dealing with Interconnect Impact of Interconnect Parasitics Reduce Reliability Affect Performance Classes of Parasitics Capacitive Resistive Inductive 1 INTERCONNECT Dealing with Capacitance
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engeerg Department of Electrical Engeerg and Computer Sciences Elad Alon Homework # Solutions EECS141 PROBLEM 1: VTC In this problem we will analyze the noise
More informationObjective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components
Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics
More informationEEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationNext, we check the race condition to see if the circuit will work properly. Note that the minimum logic delay is a single sum.
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on May 1, 2003 by Dejan Markovic (dejan@eecs.berkeley.edu) Prof. Jan Rabaey EECS
More informationCMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar
More informationLecture 14 - Digital Circuits (III) CMOS. April 1, 2003
6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #9 EECS141 PROBLEM 1: TIMING Consider the simple state machine shown
More informationLecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1
Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 321 LECTURE 32 IMPROVED OPENLOOP COMPARATORS AND LATCHES LECTURE ORGANIZATION Outline Autozeroing Hysteresis Simple es Summary CMOS Analog
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Designing Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
More informationMaster Degree in Electronic Engineering. Analog and Telecommunication Electronics course Prof. Del Corso Dante A.Y Switched Capacitor
Master Degree in Electronic Engineering TOP-UIC Torino-Chicago Double Degree Project Analog and Telecommunication Electronics course Prof. Del Corso Dante A.Y. 2013-2014 Switched Capacitor Working Principles
More informationCMOS Transistors, Gates, and Wires
CMOS Transistors, Gates, and Wires Should the hardware abstraction layers make today s lecture irrelevant? pplication R P C W / R W C W / 6.375 Complex Digital Systems Christopher atten February 5, 006
More informationCMOS Digital Integrated Circuits Lec 13 Semiconductor Memories
Lec 13 Semiconductor Memories 1 Semiconductor Memory Types Semiconductor Memories Read/Write (R/W) Memory or Random Access Memory (RAM) Read-Only Memory (ROM) Dynamic RAM (DRAM) Static RAM (SRAM) 1. Mask
More informationChapter 11. Inverter. DC AC, Switching. Layout. Sizing PASS GATES (CHPT 10) Other Inverters. Baker Ch. 11 The Inverter. Introduction to VLSI
Chapter 11 Inverter DC AC, Switching Ring Oscillator Dynamic Power Dissipation Layout LATCHUP Sizing PASS GATES (CHPT 10) Other Inverters Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky;
More informationCHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS
CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power
More informationLecture 21: Packaging, Power, & Clock
Lecture 21: Packaging, Power, & Clock Outline Packaging Power Distribution Clock Distribution 2 Packages Package functions Electrical connection of signals and power from chip to board Little delay or
More informationEEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission
More information