MOS Inverters. Digital Electronics - INEL Prof. Manuel Jiménez. With contributions by: Rafael A. Arce Nazario
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1 MOS Inverters igital Electronics - INE 407 Prof. Manuel Jiménez With contributions by: Rafael A. Arce Nazario Objectives: Introduce MOS Inverter Styles Resistor oad Enhancement oad Saturated / ear epletion Complementary (CMOS Perform C analysis of the circuits
2 Ideal Inverter MOS evices Operation regions (Enhancement GS < :cutoff, GS >, S > GS - : saturation GS >, S < GS - : lear
3 MOS evices Operation regions GS < :cutoff, 0 I Kdevice transconductance λ channel-length modulation GS >, S <( GS - : lear [ ] I ( GS S S GS >, S >( GS - : saturation I I ( ( GS GS (1 + λ S
4 Static Parameters OH M O M OH max put voltage when put is 1 O m put voltage when put is 0 I max put voltage which can be terpreted as 0 IH m put voltage which can be terpreted as 1 I IH
5 MOS Inverter - Resistor oad OH R - IN OU M O M OH GS < device is open circuit I IH GS > device conducts with resistance R ON
6 MOS Inverter - Resistor oad : Parameters OH OH O I ( l ( O I R O 1+ R ( O Assumption: Must verify latter R O
7 MOS Inverter - Resistor oad : Parameters - I ( d d GS 1 R d d di d d di I d d di d d d di d di d 1 + R d di ( ( 1 1 d d d di ( R R 1 1 R
8 MOS Inverter - Resistor oad : Parameters - IH d d d d [ ( ] IH di d di d GS ( d di substitute (1 ( IH IH d di S [ ] IH GS R solve quadratic expression by IH S S R (1 1.0 IH R
9 M ( ( ( ( M M M M M S R GS S R R R R R R R I I MOS Inverter - Resistor oad : Parameters - M
10 Effect of R on C As R creases But puttg a larger resistance would also mean: larger resistor length greater switchg delays ma disadvantage of resistor load: occupies to much chip area (10s or 100s times the area of a sgle transistor!
11 Usg enhancement transistors as load devices Justification: Sce SI resistors occupy to much chip space use transistor either saturation or lear region stead of resistor GG OU
12 Saturated enhancement load Enhancement NMOS with GS S while OU < the transistor will be saturation because GS > & S > GS - If OU tries to go above -, transistor goes cutoff (because GS <
13 Saturated enhancement load - C OU OH - ( OH Slope K R K R ( W / ( W / verter load Slope -1 O IN I IH ( + φ φ 0 + SB F γ F
14 ear enhancement load GG Enhancement NMOS with GG > + sce S - OU and GS GG - OU > + OU S < GS - OU sce GS > : the load is always on lear region
15 ear enhancement load - C Pro: OH isadvantage: Additional voltage source K R must be even larger than for saturated load for decent slope
16 epletion load epletion NMOS with GS 0 GS > : always conductg Good: OH no additional source Bad: addit. fab. process steps
17 Complementary MOSFE verter Features: Complementary MOS (CMOS Inverter analysis maes use of both NMOS and PMOS transistors the same logic gate. + All static parameters of CMOS verters are superior to those of NMOS verters + CMOS is the most widely used digital circuit technology comparison to other logic families. lowest power dissipation highest pacg density -Increased process complexity (to provide isolated transistors of both polarity types
18 Complementary MOSFE (CMOS verter S S Intuitively: IN 0 NMOS open ct. ( GSn < n PMOS conductg ( GSp > p OU OH (Good! IN NMOS conductg PMOS open ct. OU 0 O 0 (Great!
19 CMOS verter - C 1. PMOS lear, NMOS off. PMOS lear, NMOS sat 3. PMOS, NMOS both sat 4. PMOS sat, NMOS lear 5. PMOS off, NMOS lear
20 CMOS verter Region Region IN n + OH M 1 3 PMOS lear, NMOS saturation - p 4 5 O 0 n M - p OH
21 CMOS verter Param. Calculation Example NMOS lear, PMOS saturation I I n p d d d d IH Calculate IH n ( IH n p ( GSp p [ ] di n OU p OU n + di d ( n + n IH p + ( OU ( p 1+ ( di / p p OU n / OU d di ( n IH n n 1 p Substitute (1, then solve for OU, fally obta IH (1 P 1
22 CMOS verter Param. Calculation Example Calculate M NMOS & PMOS saturation I I n p n ( n M p ( ( GSn GSp n n p p ( M p.. Solve for M
23 Summary CMOS verter most used, smallest, lowest power dissipation, best verter characteristics. base for more complex logic gates Calculation of static parameters: IH, I, OH, O, M. Important: educe the region of operation of the transistors (verify later IH, I slope -1, use cha rule to simplify calculations C affected by R, K R
24 Recordatorio Buscar copias de r. Jimenez en Reproducciones ($1-$ igital circuits usg MOS transisitors
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