Assessment.mcd. Comparison frequency at phase detector. Margin sought compared to ideal phase detector noise floor, db

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1 U029 PLL Synthesizer Phase Noise PLL Synthesizer Phase Noise FLO ω n 2π3000 Nominal loop natural frequency ζ 0.8 F ref 0 5 K v 2π K d 2π Nominal loop damping factor Comparison frequency at phase detector VCO tuning sensitivity Phase detector gain, A/rad Margin db 4 Margin sought compared to ideal phase detector noise floor, db N nom floor FLO F ref N nom = Phase Detector Noise Floor 2 L pd F pd, F in 20log ( N nom ) L pd F ref, FLO = L pd F ref, FLO + 20log F in 0log F pd = 57 Phase detector noise floor, Fout + Margin db Loop Parameters C R 2 ω n N nom 2ζ ω n C K d K v C = R = Phase Detector Noise Floor L pdx L pd ( F ref, FLO) L pdx =

2 U029 PLL Synthesizer Phase Noise 2 VCO Parameters for Leeson s Model F 4 Q L 5 R floor f corner k L vco ( f) 0log FkT 2P o 8ω n 2π F o FLO 0R 000 C 2 f corner 2 π R T 290 P o 0.00 F o 2Q L f R 2 = Corner frequency for LPF into VCO 2 C 2 = PLL Architecture for Loop Filter R > VCO C3 R C2 C = = = = = L vco 0000 L vco 000 L vco L vco L vco Internal node capacitance (estimate) looking into VCO Tune Port adds to C2 C 2 C 2 Want C3 to act with R R2 to mimic a zero-order sample hold response for best speed performance. Also, in speed-up mode with LMX2332, loop bandwidth is doubled so this needs to be reflected in stability considerations. T ref F ref T ref C 3 R x 4 R x R R 2 R + R 2 R x = C 3 = G OL ( s, N ) K d K v N s R 2 sr 2 C ( + sr 2 C 2 ) + + sr 2 C 3 + sr C

3 U029 PLL Synthesizer Phase Noise 3 Examine open-loop gain function ii ii fw ii 0 R = C = C 3 = C 2 = R 2 = jx w s 2π F ref sw ii jx fw ii 2π ksum GStar ii ksum G OL sw ii + jx ksum w s, N nom G ii G OL ( sw ii, N nom ) 2 GMag ii 0log GStar ii GAng ii 80 arg GStar ii π

4 U029 PLL Synthesizer Phase Noise 4 Open-Loop Gain and Phase 00 Open Loop Gain and Phase 50 Gain (db) / Phase (deg) Frequ ency, H z G ii T fii T dbfii 0log T fii + G ii 2 Closed-Loop Transfer Functions T 2fii T 2dBfii 0log T 2fii + G ii 2

5 U029 PLL Synthesizer Phase Noise 5 Closed-Loop Gain Functions for Stability Investigation 0 Closed-Loop Gains 0 0 Gain, db Frequ ency, H z Predict Phase Noise Performance of PLL External Reference Phase Noise (SSD200 0 MHz Std) kt F xo 0000 L xo F 48 Lxokt log F xokt

6 U029 PLL Synthesizer Phase Noise 6 F tcxo 00 6 L tcxo ( f) linterp F Lxo, L xo, log ( f ) k Boltzman T 290 Temperature L refii 20 log F tcxo L tcxo fw ii F ref + 20log ( N nom ) L refii 0 log 0 0. L 0.L refii pdx + 0 Add noise from Phase Detector floor and Reference TCXO P dbii L refii + T dbfii 0.P dbii P fii 0 30 Plot of Phase Noise Spectrum Due to Reference Noise at PLL Output Main PLL Ref N oise Contribu tion Phase Noise, dbc/ Hz Frequ ency Offset, H z

7 U029 PLL Synthesizer Phase Noise 7 P 2dBfii L vco ( fw ii ) + T 2dBfii 0.P 2dBfii P 2fii 0 Phase Noise Contribution from VCO Self-Noise to PLL Output Spectrum 60 Main PLL VCO N oise Contribu tion Phase Noise, dbc/ Hz Frequ ency Offset, H z

8 U029 PLL Synthesizer Phase Noise 8 Compute Phase Noise Arising from R in PLL Y ( s) Z a ( s) Z b ( s) R + Y ( s) + sc 3 sc R 2 + sc 2 pn ii 4k Z b ( jx 2 πfw ii ) Z a jx 2 πfw ii TR Z a jx 2 πfw ii + K v + jx 2πfw ii R 2 C 2 jx 2πfw ii G ii 2 2 P 3dBfii 0log pn ii + T dbfii P 3fii 0 0.P 3dBfii R = R 2 = K v 2π = Phase Noise Contribution at PLL Output Due to R 80 Main PLL R Contribution at Output Phase Noise, dbc/ Hz Frequ ency Offset, H z

9 U029 PLL Synthesizer Phase Noise 9 Compute Phase Noise Arising from R2 in Loop Filter Z x ( s) pn2 ii R + sc 4k TR 2 + sc 3 jx 2 π fw ii C ( ) 2 jx 2 π fw ii C ( ) 2 + R 2 + Z x jx 2 πfw ii K v jx 2πfw ii G ii 2 2 P 4dBfii 0log pn2 ii + T dbfii 0.P 4dBfii P 4fii 0 Phase Noise Contribution at PLL Output Due to R2 80 Main PLL R2 Contribution at Output Phase Noise, dbc/ Hz Frequ ency Offset, H z

10 U029 PLL Synthesizer Phase Noise 0 PSDx ii 0log P fii + P 2fii + P 3fii + P 4fii (,, 500) = (,, 000) = (,, 2000) = (,, 3000) = = linterp fw, PSDx, 4000 = linterp fw, PSDx, 5000 (,, 7000) = (,, 0000) = (,, 5000) = (,, 8750) = 83.3 = linterp fw, PSDx, = linterp fw, PSDx, 3250 (,, 43500) = (,, 50000) = (,, 75000) = (,, 00000) = = linterp fw, PSDx, = 3.45 linterp fw, PSDx,

11 U029 PLL Synthesizer Phase Noise Composite Phase Noise Output Spectrum for Output 50 Main Synthesizer Phase N oise Phase Noise, dbc/ Hz Frequ ency Offset, H z Spectrum, dbc/ Hz Reference Contribu tion VCO Contribu tion R Contribution R2 Contribution

12 U029 PLL Synthesizer Phase Noise 2 ku ku 200 Fx ku 0 S outku linterp fw, PSDx, Fx ku LogFx ku log Fx ku Integrated Phase Noise Out to FH Offset: F H PhaseNoise F L df ( F H F L ) N 80 π 2 0 ix = 0 df F L + ix+ F L + ix df 0 0. linterp LogFx, S out, log ( fx ) dfx PhaseN oise( 5000) =.668 degrees rms Phase Change Over Time PhaseAccu m u lation ( τ) df N 80 π 8 0 ix = 0 2τ 2τ + ( ix+ ) df + ix df 0 0. linterp LogFx, S out, log ( fx ) sin ( πfxτ) 2 dfx PhaseAccumulation = degrees rms Dat S ku, outku Dat Fx ku, 0 ku

13 U029 PLL Synthesizer Phase Noise 3 Residual FM ResidualFM F L, F H df ( F H F L ) N 2 0 ix = 0 df F L + ix+ F L + ix df fx 2 0.linterp 0 LogFx (, S out, log ( fx ) ) dfx Resid u alfm ( 00, 00000) = Hertz rms

14 U029 PLL Synthesizer Phase Noise 4 Basic Type-II PLL Parameters Phase error at phase detector (radians) output due to a frequency step change θ pd t, ω n, ζ, F step ζω 2πF n t step e if ζ sinh ω n ζ 2 t ω,, sinω n ζ 2 t n ζ 2 Peak phase error for a frequency-step input occurs for T fstep ( ω n, ζ) ω n ζ 2 atan2 ζ, ζ 2 3 db Closed-Loop Bandwidth, Hz BW 3dBClosed ( ω n, ζ) ω n 2π + 2ζ ζ 4 + ζ db Open-Loop Band Bandwidth, Hz BW 0dBOpen ( ω n, ζ) ω n 2π 2ζ 2 + 4ζ 4 + System Phase Margin PhaseMargin ω n, ζ atan 2 BW 0dBOpen ( ω n, ζ) 2 ω n π Peak Frequency Overshoot with Frequency Step Input 2π ω error t, ω n, ζ, F F e ζ ω n t cos ζ 2 ω n t ζ ζ 2 sin ζ 2 ω n t