Electronic Devices and Circuits Lecture 15  Digital Circuits: Inverter Basics  Outline Announcements. = total current; I D


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1 Electronic Devices and Circuits Lecture 15  Digital Circuits: Inverter asics  Outline Announcements Handout  Lecture Outline and Summary The MOSFET alpha factor  use definition in lecture, not text ["1" is missing in Eq ] Review  Linear equivalent circuits Notation: i D = I D i d (t) where i D = total current; I D = bias; i d (t) = increment LECs: the same for npn and pnp; the same for nmos and pmos; all parameters depend on bias, so maintaining a stable bias is critical Digital building blocks  inverters A generic inverter MOS inverter options Digital inverter performance metrics Transfer characteristic: logic levels and noise margins Power dissipation Switching speed Fanout, fanin Manufacturability Comparing the MOS options And the winner is. Clif Fonstad, 10/03 Lecture 15  Slide 1
2 LEC for the pn junction diode: A a IS qa g d C d b g d = q kt I S e qv A / kt ª q I D kt C d = C dp C df, where C dp (V A ) = A C df (V A ) = q I D kt [ w p  x p ] 2 qe Si N Ap ( ) 2 f b V A and [ ] 2 = g d t d with t d w  x p p 2D e 2D e (Note: The capacitance expressions assume an n p diode) Clif Fonstad, 10/03 Lecture 15  Slide 2
3 Linear equivalent circuit for the JT in F.A.R: qc qe i IS C E bfi b e g p v p  Cp C m g m v p g o c e g m ª q I C kt g o ª l I C Ê or ª I ˆ C Á Ë V A g p = g m C p = g m t b  E depletion capacitance, where t b = C m =  C depletion capacitance b o w 2 2 D minority.in base Clif Fonstad, 10/03 (Note: The LEC is the same for npn and pnp JTs. Lecture 15  Slide 3
4 Linear equivalent circuit for the MOSFET in saturation: D qd g C gd d G qg id v gs s   C gs g m v gs qs S b g m ª 2K I D Ê g o ª l I D or ª I ˆ D Á Ë V A v bs C sb C db v ds g mb v bs g o  s C gb g mb = h g m = h 2K I D with h = 1 * C ox e Si qn A qf p V S C gs = 2 3 W LC * ox C sb, C gb, C db : depletion region capacitances * C gd = W C gd * where C gd is the gate  to  drain fringing and overlap capacitance per unit gate width Clif Fonstad, 10/03 (Note: The LEC is the same for n and pchannel MOSFETs. Lecture 15  Slide 4
5 Circuit symbols: C E JT: MOSFET: D D npn E S C pnp (usual circuit orientation) S G G G G S Enhancement mode Depletion mode Enhancement mode Depletion mode nchannel S pchannel (usual circuit orientation) Clif Fonstad, 10/03 Lecture 15  Slide 5 D D
6 uilding locks for Digital Circuits: inverters A basic inverter Switch: on or off Lo (0) Hi (1) Hi (1) Lo (0) Performance metrics Transfer characteristic Logic levels Noise margins Power dissipation Switching speed Fanin/Fanout Manufacturability Logic gates Memory cell NOR: v A v v A v NAND: v A v Clif Fonstad, 10/03 Lecture 15  Slide 6 v A v Flipflop
7 Transfer characteristic Node equation : i PD = Ï 0 Ô Ô when < V T,PD Ô K i PD = PD ( V T,PD ) 2 2 Ì Ô when 0 < [ V T,PD ] < Ô K PD ( V T,PD  2) Ô Ó when 0 < < [ V T,PD ] : Depends on the specific pull up device used. i PD V HI V M V LO V OUT Logic levels, Noise margins V LO V 1L V M V 1H V HI V IN NM L NM H Switching times HI to LO OFF LO to HI Charging cycle: i Charge = C L ON LO to HI i PD Discharging cycle: = i PD P Total = P Static P Dynamic Static Static: : P Static = 1 2,on Dynamic: : 2 P Dynamic = C L f Clif Fonstad, 10/03 Lecture 15  Slide 7 HI to LO C L Power
8 MOS inverters Generic inverter C L Resistor pullup R L V GG (>> ) nchannel, emode pullup on gate V GG on gate nchannel, dmode pullup pchannel, emode pullup (CMOS) Clif Fonstad, 10/03 Lecture 15  Slide 8
9 Switching transients HI to LO OFF LO to HI i Charge C L ON LO to HI i PD HI to LO C L Charging cycle: i Charge = Discharging cycle: = i PD i Charge The charging currents with various pullups Clif Fonstad, 10/03 I ON nch, emode on gate CMOS, I ON = 0 nch, dmode resistor and nch, emode w. V GG on gate Lecture 15  Slide 9
10 Switching transients The discharging currents with various pullups Note: The discharge current is the difference between the upper curve and the appropriate lower curve. I ON nch, emode on gate nch, dmode resistor and nch, emode w. V GG on gate ( = 0) CMOS ON LO to HI i PD HI to LO C L Clif Fonstad, 10/03 Lecture 15  Slide 10
11 Switching transients: summary of charge/discharge currents Resistor and E mode pullup (V GG on gate) R L V GG (>> ) i Charge i Charge Emode pullup ( on gate) i Charge Dmode pullup (called "nmos") i Charge CMOS Clif Fonstad, 10/03 Lecture 15  Slide 11
12 Electronic Devices and Circuits Lecture 15  Digital Circuits: Inverter asics  Summary Digital building blocks  inverters A generic inverter  Switch = pulldown device, Load = pullup device MOS inverter options  down: nchannel, emode (faster than pchannel) up: 1. resistor; 2. nchannel, emode w. and w.o. gate bias; 3. nchannel, dmode; 4. pchannel, emode (CMOS) Digtial inverter performance metrics Transfer characteristic Logic levels: V HI, V LO Noise margins: NM HI (high), and NM LO (low) Design variables: choice of pullup device pullup and pulldown thresholds device sizes (absolute and relative) Power dissipation: standby power and switching dissipation Switching speed: capacitive load charge and discharge currents critical Fanout, fanin: minimal issue in MOS; more so with JT logic Manufacturability: small, fast, lowpower, reliable, and cheap Comparing the MOS options And the winner is.cmos Clif Fonstad, 10/03 Lecture 15  Slide 12
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