Parallel Multipliers. Dr. Shoab Khan

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1 Parallel Multipliers Dr. Shoab Khan

2 String Property 7=111=8-1= = =32-1 Or =32-1=31 Replace string of 1s in multiplier with In a string when ever we have the least significant 1, we put a bar on it We go to the end of the string We replace all the 1(s) with 0 We put a 1 where the string ends

3 Example String String String String Hence the number of 1(s) has reduced from 14 to 6. Both have the same value.

4 Booth Recoding Algorithm Booth recoding makes use of the string property.

5 Modified Booth Recoding Two Basic Operations in Multiplying generation of partial products accumulation of partial products Two Ways of Speed-Up accelerate the accumulation Partial product reduction technique reduce the number of partial products modified Booth recoding

6 Basic Idea Radix-2 partial product = (multiplicant) x {0, 1} Radix-4 partial product = (multiplicant) x {00, 01, 10, 11} x x + +

7 Why are we doing this? We have a 3 which is difficult to be handled Simple shifting can t be performed to handle it Numbers are required to be in this form (-2, -1, 0, +1, +2) Because if we get 3, it means 2+1 hence resulting in 2 partial products

8 Modified Booth Recoding The modified Booth recoding algorithm exploits the string property This technique reduces number of pps into half Partitioning the multipliers in groups of two and generating one row of pp for each group to achieve this reduction From left to right each pair is observed for string property along with the higher order bit of the previous pair For the first pair a zero is appended at left As the string property is applied on three bits, there are eight possibilities:

9 : no string. The group is coded with a 0. Booth Recoding 0 0 1: end of string is coded as : start and end of a string at bit 0, coded as = : an end of string at bit location 0, coded as 2 1 = : a start of a string at bit location 1; coded as -2 1 = : a start of a string at bit location 1 and an end of string at high bit location of the previous pair, = -1

10 Booth Recoding Table

11 Basic Idea Instead of multiplying with a single bit We multiply with two bits hence making the partial products half in No.

12 A= B= For these two bits Booth s algorithm restricts the value to be (-2, -1, 0, +1,+2) +2 means Shift left A by one +1 means Copy A in the answer 0 means copy all 0 s -1 means 2 s complement and then copy -2 means 2 s complement and then shift left

13 Example! X So the partial products have been reduced from 8 to 4 in number

14 Example!

15 0 b0 b1 b 2 b3 b 4 b 5 b 6 b7 Booth Recoder BR 0 BR 1 BR 2 BR 3 a 0-2a ā 2 a 0-2a ā 2 a 0-2a ā 2 a 0-2a ā 2 a Adder 5:1 5:1 5:1 5:1 Partial Product Reduction Tree

16 Task A procedure which can be called from Verilog behavioral code task name; input arguments; output arguments; inout arguments; declarations; begin statement; end endtask

17 Task Task definition occurs inside a module Task is called only from initial and always blocks and other tasks in that module Task contains any behavioral statements, including time control Order of input, output, and inout definitions determines binding of arguments input argument may not be reg output arguments must be reg

18 Functions (FIO) Implement combinational behavior No timing controls or tasks May call other functions with no recursion No output or inout allowed Implicit register having name and range of function

19 Functions Syntax: function_declaration function [range or type] function_identifier; function_call function_identifier (expression {, expression}) Example:

20 Multiplication by Constant In many algorithms a large percentage of multiplications are by constants Complexity of a general purpose multiplier is not required Generate pps only for 1s in the constant muliplier The number of pps can be further reduced using canonic sign digit format

21 Example In an FIR filter all coefficients are constant For a fully parallel implementation, we don t put general purpose multipliers since the flexibility of this kind of a multiplier is not required We know precisely where we need a partial product Convert all the coefficients in canonic form and generate partial products.

22 Multiplication by a Constant Encoding a number such that it contains the fewest number of non-zero bits is called Canonic Signed Digit (CSD) representation of a number Following are the properties of CSD No 2 consecutive bits in a CSD number are nonzero Contains minimum possible number of nonzero bits CSD representation of a number is unique

23 CSD is obtained using string property CSD bits: { -1, 0, 1} Example a Q1.7 format number = = Worst-case CSD has 50% non-zero bits. Encoding: Iterative transform technique Example: k = Kx = x2 0 - x2-3 - x2 7

24 Multiplication by constant

25 FIR filter The equation for the computation of an N-taps FIR filter is:

26 Example If N=5 y[0]= h 0 x 0 + h 1 x -1 + h 2 x -2 + h 3 x -3 +h 4 x -4 y[1]= h 0 x 1 + h 1 x 0 + h 2 x -1 + h 3 x -2 +h 4 x -3 y[2]= h 0 x 2 + h 1 x 1 + h 2 x 0 + h 3 x -1 +h 4 x -2 y[3]= h 0 x 3 + h 1 x 2 + h 2 x 1 + h 3 x 0 +h 4 x -1 y[4]= h 0 x 4 + h 1 x 3 + h 2 x 2 + h 3 x 1 +h 4 x 0 y[5]= h 0 x 5 + h 1 x 4 + h 2 x 3 + h 3 x 2 +h 4 x 1

27 Conversion of FIR Coefficient in CSD Only one nonzero CSD digit is required for approximately each 20 db of stopband attenuation

28 Example: CSD Representation Keeping only 4 non-zero bits and throwing away the LSB, we have: Performing Shift Right (Dividing)

29 CSD multiplier xn as it is 1 s s s Shift xn by 3 Take 1 s complement Add a 1 to the LSB, sign extension 1 s s s s s s s Shift xn by 7 Take 1 s complement, Add a 1 to the LSB, sign extension

30 xn CSD Multiplier in an FIR filter Xn-1 Xn-2 Xn-3 Xn-4 N N N N N REG REG REG REG h 0 h 1 h 2 h 3 h 4

31 An Optimal Direct Form FIR Filter Architecture

32 Example: CSD Representation

33 CSD FIR paper

35 Transpose Direct Form FIR Filter x n h 0 h 1 h 2 h 3 h 4 X X X X X x n h 0 x n h 1 x n h 2 x n h 3 x n h Critical Path

36 Filter implementation x(n) h N-2 + h N h z z 1 z 1 1 z z 1 z 1 y(n) Pipeline Register

37 Pipeline Filter Implementation x(n) h N-2 + h N h z z 1 z 1 1 z z 1 z 1 y(n)

38 Example: Recursive Flow Graph x N n N 1 N 2 X X + b 1 a 1 X X b 2 a 2

39 Example: Recursive Flow Graph Optimal Mapping GCV 3:2 5:2 CPA 4:2 8:2 a 1 8:2 4:2 A Fully Dedicated Architecture a 2 8:2 8:2

40 Example 3: x n X h 0 h 1 X X h y n + + x n h 1

41 Example 3: Optimal Mapping 4:2 4:2 4:2 4:2 4:2 5:2 4:2 CPA

What s the Deal? MULTIPLICATION. Time to multiply

What s the Deal? MULTIPLICATION Time to multiply Multiplying two numbers requires a multiply Luckily, in binary that s just an AND gate! 0*0=0, 0*1=0, 1*0=0, 1*1=1 Generate a bunch of partial products