Professor Fearing EECS150/Problem Set Solution Fall 2013 Due at 10 am, Thu. Oct. 3 (homework box under stairs)

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Shawn Dickerson
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1 Professor Fearing EECS50/Problem Set Solution Fall 203 Due at 0 am, Thu. Oct. 3 (homework box under stairs). (25 pts) List Processor Timing. The list processor as discussed in lecture is described in RT Language as:. X Memory[NUMA], NUMA NEXT ; 2. NEXT Memory[NEXT], SUM SUMX; Due to routing in Xilinx, wider data paths can have greater delays. Assume delays: clk-to-q ns, setup time ns, 8 bit Mux 3 ns, 6 bit Mux 4 ns, 8 bit adder 8 ns, 6 bit adder 0 ns, NextZero 2 ns, memory 20 ns. Consider the data path below. a. Draw a timing diagram showing the critical path for both states. Width Assumptions: X - 8, NEXT - 8, NUMA - 8, SUM - 6. Also assuming that the adder has been structure such that the tools can recognize when an 8 vs. a 6-bit number is being added (though this does not affect the critical path). FSM output is clk-to-q based on assumption of One-Hot encoding. Signal refers to the input of register Signal. Time is not to scale, all times are in reference to the most recent clock edge. X Memory[NUMA]: Clock A SEL NUMA A D X Delay Clk2Q Mux8 Mem Mux8 Setup Clk2Q Time 0ns ns 4ns 24ns 27ns 28ns ns

2 NEXT Memory[NEXT]: Clock A SEL NEXT A D NEXT Delay Clk2Q Mux8 Mem Mux8 Setup Clk2Q Time 0ns ns 4ns 24ns 27ns 28ns ns b. Assume the finite state machine controller requires NextZero to be settled 2 ns before the rising edge of the clock. What is the maximum clock frequency? If you find the clock frequency based on the NextZero path, the maximum frequency is /(2ns setup 2ns combinational ns clk-to-q) = /5ns 67MHz. If you assume the clock frequency is limited by the full datapath above, the maximum frequency is /(27ns combinational ns setup) = /28ns 36MHz. 2. (25 pts) Infinite impulse response filtering. Consider a digital signal processor with input and output y[n]. For an all-pole IIR filter, the general form is y[n] = N a k y[n k] b. k= For this problem, let N = 3, then the IIR filter is given by y[n] = a y[n ] a 2 y[n 2] a 3 y[n 3] b. In RT Language, the IIR filter can be described as: Y b a 3 Y3 a 2 Y2 a Y, Y3 Y2, Y2 Y; a. Draw a block diagram for the IIR data path described by the RT Language. y[n-] Y Y2 Y3 b a a 2 a 3 2

3 b. Given delays T mult, T add, T D to Q, T setup find the critical path and estimate the maximum operation frequency. Assuming T add refers to a 2-input adder: F max = T D to Q T mult 2 T add T setup c. Can pipelining improve the clock rate of the IIR filter? If yes, show by modifying the block diagram from part a., otherwise explain why not. For this design, the IIR cannot be improved by pipelining. The circular dependency on output values prevents this. 3. (30 pts) Finite impulse response filtering. Consider a digital signal processor with input and output y[n]. For an all-zero FIR filter, the general form is y[n] = N k=0 b k x[n k]. For this problem, let N = 4, then the FIR filter is given by y[n] = b 0 b x[n ] b 2 x[n 2] b 3 x[n 3]. In RT Language, the FIR filter can be described as: Y b o b 3 X3 b 2 X2 b X, X3 X2, X2 X, X ; a. Draw a block diagram for the FIR data path described by the RT Language. X X2 X3 b 0 b b b 2 3 Y y[n-] b. Given delays T mult, T add, T D to Q, T setup find the critical path and estimate the maximum operation frequency. Assuming T add refers to a 2-input adder: F max = T D to Q T mult 2 T add T setup c. Show how pipelining can improve the clock rate of the FIR filter, by modifying the block diagram from part a. 3

4 b 0 X X2 X3 b b 2 b 3 P P2 P3 P4 P5 P6 Y y[n-] Critical path is now F max = T D to Q max(t mult,t add )T setup. d. Write RT Language for the FIR filter with pipelining. X3 X2, X2 X, X, P b 0, P2 b X, P3 b 2 X2, P4 b 3 X3, P5 P P2, P6 P3 P4, Y P5 P6; 4. (20 pts) Serial Multiplier. A serial multiplier is shown below. The A and B registers are 4 bits, with initial values 4 b0 and 4 b00 respectively. Complete the table for all operation steps. From the pseudocode controller in lecture 8 slides: repeat n c y c l e s { // outer ( i ) loop repeat n c y c l e s { // i n n e r ( j ) loop shifta, selectsum, s h i f t H I } shiftb, s h i f t H I, shiftlow, r e s e t } We ve included the loop index variable for references, they aren t necessary in the solution. 4

5 step i j B A HI LOW sum carry

EECS150 - Digital Design Lecture 11 - Shifters & Counters. Register Summary

EECS150 - Digital Design Lecture 11 - Shifters & Counters. Register Summary EECS50 - Digital Design Lecture - Shifters & Counters February 24, 2003 John Wawrzynek Spring 2005 EECS50 - Lec-counters Page Register Summary All registers (this semester) based on Flip-flops: q 3 q 2