Pipelining and Parallel Processing

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1 Pipelining and Parallel Processing Pipelining ---reduction in the critical path increase the clock speed, or reduce power consumption at same speed Parallel Processing ---multiple outputs are computed in parallel in a clock period effective sampling speed is increased reduction of power consumption 1

2 Pipelining and Parallel Processing (cont d) a n b(n) x n + + y(n) (a) A data path a n b(n 1) x n + y(n 1) + (b) 2-level pipelining a 2k b(2k) x 2k y(2k) + + a 2k + 1 b(2k + 1) x 2k + 1 y(2k + 1) + + (c) 2-level parallel processing 2

3 3-Tap FIR Filter x n h(0) h(1) h(2) + + y(n) T sample T M + 2T A 1 f sample T M + 2T A 3

4 Pipelined FIR Filter x n h(0) h(1) h(2) pipeline latches y(n 1) + + critical path= T M + T A increase in latency 4

5 Feed-forward Cutset Pipeline latches can only be placed across any feed-forward cutset of the graph Cutset: a set of edges of a graph such that if these edges are removed, the graph becomes disjoint. Feed-forward Cutset: ata move in the forward direction on all edges of the cutset. 5

6 ata-broadcast Structure Transposition theorem : flow reversal preserves the functionality of the system. x n h(2) h(1) h(0) + + y(n) critical path = T M + T A 6

7 Fine-Grain Pipelining x n m 1 m 1 m 1 m 2 m 2 m y(n 1) 7

8 Parallel Processing pipelining Parallel Processing duals of each other Both exploit concurrency available in the computation in different ways pipelining : independent sets of computations are computed in an interleaved manner parallel processing : use duplicate hardware 8

9 Block Processing x n SISO y(n) x 3k y(3k) x 3k + 1 y(3k + 1) MIMO x 3k + 2 y(3k + 2) Sequential System 3-Parallel System 9

10 3-Parallel 3-tap FIR Filter x 3k + 2 x 3k + 1 x 3k a b c + + y 3k + 2 x 3k 1 c a b + + y(3k + 1) : block delay T clk T M + 2T A x 3k 2 T itr = T sample = 1 L T clk 1 3 (T M + 2T A ) b c a + + y(3k) 10

11 Complete Parallel Processing System x(n) Serial-Parallel T/L converter x Lk + L 1 x Lk y Lk clock T MIMO system y Lk + L 1 clock T/L Parallel-Serial converter y(n) 11

12 Serial-Parallel Converter x(n) T x Lk + L 1 x Lk + 1 x(lk) 12

13 Parallel-Serial Converter y Lk + L 1 y Lk + 1 y(lk) T T T y(n) 13

14 Pipelining vs. Parallel Processing Chip 1 O/P pad Chip 2 I/P pad If critical path < I/O delay I/O bottleneck communication bound pipelining can no longer increase the speed. 14

15 Power issipation Propagation delay T pd = C chargev 0 k(v 0 V T ) 2 C charge : capacitance to be charged/discharged, i.e. capacitance along the critical path V 0 : supply voltage V T : threshold Power Consumption P = C total V 0 2 f C total : total capacitance of the circuit V 0 : supply voltage f: clock frequency 15

16 Pipelining for Low Power Pipelining reduces the critical path to 1 M capacitance C charge M If f is maintained, supply voltage can be reduced to βv 0 (0 < β < 1) P pip = C total β 2 V 0 2 f = β 2 P seq T seq = C chargev 0 k(v 0 V T ) 2 C charge T pip = M βv 0 k(βv 0 V T ) 2 M(βV 0 V T ) 2 =β(v 0 V T ) 2 16

17 Parallel Processing for Low Power L-parallel system increases the throughput L-times The clock period is increased to LT seq There is more time to charge the same capacitance The supply voltage can be reduced to βv 0 LT seq = C charge βv 0 k βv 0 V T 2 L βv 0 V T 2 =β(v 0 V T ) 2 P par = LC charge (βv 0 ) 2f L = β2 P seq 17

18 Combining Pipelining and Parallel Processing Pipelining reduces the capacitance to be charged/discharged in 1 clock period Parallel processing increases the clock period for charging/discharging the original capacitance. Propagation delay of the parallel-pipelined system LT pd = (C charge/m)βv 0 k(βv 0 V T ) 2 = LC chargev 0 k(v 0 V T ) 2 LM(βV 0 V T ) 2 =β(v 0 V T ) 2 18

19 Retiming Change the location of delay elements in a circuit without affecting the inputoutput characteristics. applications reduce the clock period reduce the number of registers reduce the power consumption 19

20 Retiming does not change the number of delays in a cycle. does not alter the iteration bound in a FG (1) (1) (2) 2 (2) critical path=3u.t. (1) 1 (2) (1) 4 (2) critical path=2u.t. 20

21 Cutset Retiming If cutset is removed, 2 disconnected subgraphs are created, which are labeled G 1, G 2 Add k delays to each edge from G 1 to G 2 Remove k delays from each edge from G 2 to G 1 21

22 Pipelining Special case of cutset retiming where there are no edges in the cutset from G 2 to G 1 Pipelining applies to graphs without loops These cutsets are referred to as feed-forward cutsets. 22

23 Slow-own Replace each delay in the FG with N delays to create N-slow version of the FG. N 1 null operations (or 0 samples) must be interleaved after each useful signal sample to preserve the functionality of the algorithm. 23

24 Retiming to Reduce the Clock Period stage lattice 101T A +2T M 2-slow version critical path 2 retimed version 2(2T A +2T M ) 24

25 Retiming for Register Minimization registers 7 registers 25

26 Exercise Consider the 4th-order FIR filter y n = h 0 x n + h 2 x n 2 + h 4 x(n 4). raw a topology for this filter such that the clock period is limited by 1 multiply-add time. Neither a broadcast structure nor new latches should be used. 2. An IIR filter y n = ay n 1 + x(n) can be rewritten as y n = a ay n 2 + x(n 1) + x n = a 2 y n 2 + ax n 1 + x(n). raw FGs for the two filters, and compare their iteration bounds. Retime the latter FG so that its iteration bound becomes minimum. 26

27 Exercise 12 (cont.) 3. For the filter below, a. What is the loop bound and the iteration bound? b. What is the critical path? c. Pipeline or retime the filter to achieve a critical path equal to the iteration bound. + a

Pipelining and Parallel Processing

Pipelining and Parallel Processing ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 010 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines