Retiming. delay elements in a circuit without affecting the input/output characteristics of the circuit.

Transcription

1 Chapter Retiming NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 1 Retiming & A transformation techniques used to change the locations of delay elements in a circuit without affecting the input/output characteristics of the circuit. w(n)=ay(n-1)+by(n-2) y(n)=w(n-1)+x(n) =ay(n-2)+by(n-3)+x(n) w 1 (n)=ay(n-1) w 2 (n)=by(n-2) y(n)=w 1 (n-1)+w 2 (n-1)+x(n) =ay(n-2)+by(n-3)+x(n) NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 2

2 & Application Retiming (cont d) t Reducing the clock period of the circuit (3 2) t Reducing the number registers in the circuit ( 5) t Reducing the power consumption of the circuit t Logic synthesis & Critical path t The longest path between any two latches (1) 1 a w(n) 2 3 (1) (2) (1) 1 (a) b (2) a (1) 2 w 3 (2) 1 (n) 2 2 w 2 (n) (b) b (2) NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 3 Retiming (cont d) & Quantitative description of retiming t Map circuit G Gr t Retiming can be presented with r(v), V is one of the nodes in the circuit t For each edge U V e V estination Source w r ( e) = w( e) + r( V ) r( U ) w(e): weight (delay) of the edge e in the origin circuit wr(e): weight of the edge e in the retimed circuit NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai

3 Retiming (cont d) & Example retiming Origin FG Retimed FG with r(1)=0 r(2)=1 r(3)=0 r()=0 e e w ( 3 2) = w(3 2) + r(2) r(3) = = 1 r e e w ( 2 1) = w(2 1) + r(1) r(2) = = 0 r A retiming solution is feasible if W r ( e) 0 e G NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 5 & Properties of Retiming Retiming (cont d) t The weight of the retimed path given by t Retiming does not change the number of delays in a cycle i.e., w r (p)= w(p) t Retiming does not alter the iteration bound in a FG Since the number of delays in a cycle does not change t Adding the constant value j to the retiming value of each node does not alter the number of delays in the edges of the retimed graph is NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 6

4 & Retiming Retiming (cont d) t The procedure to transform an SFG to an equivalent and temporal localized form. & Cut-set Retiming Procedure t The redistribution of timing t Rule 1: Timing Scaling α t Rule 2: elay Transfer Cut-set principle +k +k -k NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 7 Retiming (cont d) = = NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 8

5 Retiming Techniques & Retiming techniques t Cutset retiming t Pipelining G G 2 (a) (b) (c) Fig.. (a) The unretimed FG with a cutset shown as a dashed line. (b) The 2 graphs G 1 and G 2 formed by removing the edges in the cutset. (c) The retimed graph found using cutset retiming with k=1. & Cutset t A set of edges that can removed from the graph to create 2 disconnected subgraphs (G 1 &G 2 ). t Only affect the weights of the edges in the cutset t Adding k delays to each edge from G 1 to G 2, and removing k delays from each edge from G 2 to G 1. NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 9 & Cutset (cont d) Retiming Techniques (cont d) t Subgraph G 2 is a single node and G 1 is the reset of the graph NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 10

6 & Pipeline Retiming Techniques (cont d) t Applies to graphs without loops, feed-forward cutset NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 11 & Pipeline (cont d) Retiming Techniques (cont d) Fig..7 In each of the 3 filters in this figure, the critical path is shown with dotted lines, and addition and multiplication are assumed to take 1 and 2 u.t., respectively. (a) A 100-stage lattice filter with minimum sample period of 105 u.t. (b The 2-slow version of the circuit. (c) A retimed version of the 2-slow circuit with critical path of 6 u.t. and minimum sample period of 12 u.t. t Cutsetretiming is a special case of retiming, and pipelingis a special case of cutset retiming. NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 12

7 & Computation Task Array Processor t Compute-bounded computations The total number of operations is larger than the total number of input and output operations t I/O-bounded computations & Speed-up t Systolic array By replacing a single processor by a 1 or 2 array of processors, a higher computation throughput can be achieved without increasing memory bandwidth. NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 13 Array Processor (cont d) t Memory bandwidth epends on technology. & efinition of Systolic Arrays t A systolic array is computing network possessing the following features: Synchrony Synchrony: The data are rhythmically computed (timed by a global clock) and passed through the network NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 1

8 Array Processor (cont d) & efinition of Systolic Arrays t Features (cont d) Modularity and regularity: The array consists of modular processing units with homogeneous interconnections. Moreover, the computing network may be extended indefinitely. Spatial locality and temporal locality: The array manifests a locally-communicative interconnection structure, I.e., spatial locality. There is at least one unit-time delay allotted so that single transactions from one node to the next can be completed. i.e., temporal locality. Therefore, if an SFG, G=<V,E,(E)>, represents a systolic design then (e) 1 for all edges, e. NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 15 Array Processor (cont d) & efinition of Systolic Arrays t Features (cont d) Pipelinability(i.e. O(M) execution-time speedup): The array exhibits a linear rate pipelinability, i.e., it should achieve an O(M) speedup, in terms of processing rate, where M is the number of processing elements (PE s). Here the efficiency of the array is measured by the following s speedup fa ctor = Tp where T s is the processing time in a single processor, and T p is the processing time in the array processor. T NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 16

9 Array Processor (cont d) NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 17 Array Processor (cont d) & Properties of Systolic Architectures t Simple and regular design t Concurrency and communication t Balancing computation with I/O partitioning t Clock distribution H-tree NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 18

10 & esign Method Array Processor (cont d) t Stage 1: erive a G from the algorithm t Stage 2: Map the G to an SFG array t Stage 3: Transform the SFG to a systolic array Ł every edge of the resulted SFG will have one or more delay elements. t Systolic array = SFG array + pipeline retiming NCU EE -- SP VLSI esign. Chap. Tsung-Han Tsai 19