Final presentations May 8, 1-5pm, BWRC Final reports due May 7, 8pm Final exam, Monday, May :30pm, 241 Cory

Transcription

1 EE241 - Spring 2008 Advanced Digital Integrated Circuits Lecture 28: Latch-Based iming Conclusion Announcements Wrapping-up the class: Final presentations May 8, 1-5pm, BWRC Final reports due May 7, 8pm Final exam, Monday, May :30pm, 241 Cory Presentations 12 minutes (max 10 slides) + 3 minutes for Q & A 2 1

2 Agenda Latch based timing Wrap-up 3 Latch-Based iming 2

3 Skew-olerant Domino General Reference: Harris, Horowitz, Skew-tolerant domino circuits ISSCC 97, JSSC 11/97 Also slides from D. Harris s Web site: 5 Latch timing t D-Q D Q When data arrives to transparent latch Latch is a soft barrier Clk t Clk-Q When data arrives to closed latch Data has to be re-launched 6 3

4 Single-Phase Clock with Latches φ Latch Unger and an rans. on Comp. 10/86 Logic skl skl skt skt In Chapter 10: = + sk skl skt Clk PW P 7 Preventing Late Arrivals Clk Clk P PW SU Data must arrive Clk-Q LM SU SU Clk PW D-Q LM SU 8 4

5 Preventing Late Arrivals skl + skt + SU + clk QM PW, P max + D QM LM Or: P clk QM + LM + SU + skl + skt PW P D + QM LM 9 Preventing Premature Arrivals Clk PW H Clk-Q Lm wo cases, reduce to one: Lm skl + skt + H + PW Clk Qm 10 5

6 Single-Latch iming Bounds on logic delay: φ skl + skt + SU + clk QM PW, P max + LM D QM Latch Lm skl + skt + H + PW Clk Qm Logic Either balance logic delays or make PW short 11 Latch-Based Design L1 latch is transparent L2 latch is transparent when f = 0 when f = 1 f L1 Latch Logic L2 Latch Logic 12 6

7 Latch-Based iming As long as transitions are within the assertion period of the latch, no impact of position of clock edges 13 Latch Design and Hold imes 14 7

8 Latch-Based iming Longest path P D QM LHM Independent of skew Short paths LLM CLLm SK + H Clk Qm CLHm SK + H Clk Qm Same as register-based design but holds for both clock edges 15 Latch-Based iming φ Static logic Skew L1 Latch Logic L2 Latch L1 latch φ = 1 L2 latch Logic Long path φ = 0 Can tolerate skew! Short path 16 8

9 Soft-Edge Properties of Latches Slack passing logical partition uses left over time (slack) from the previous partition ime borrowing logical partition utilizes a portion of time allotted to the next partition Makes most impact in unbalanced pipelines Bernstein et al, Chapter 8, Chandrakasan (Partovi), Chap Slack-Passing and Cycle Borrowing For N stage pipeline, overall logic delay should be < N cl 18 9

10 Slack Passing Example Edge riggered: = 125 nsec Latch-based: = 100 nsec 19 Latches with Dynamic Logic Phase1-domino evaluates Phase2-domino precharges Clock evaluates logic and opens subsequent latch: L2 latch φ = 0 L1 latch Static signals driving dynamic logic must be either non-inverting or stable before evaluation φ = 1 Phase2-domino evaluates Short path Phase1-domino precharges 20 10

11 Domino Logic with Latches ime available to logic is P 2 D-Q 21 Clock Skew ime penalty: L = P (2 D-Q + 2 sk ) 22 11

12 Non-Balanced Phase Delays ime penalty: L = P (2 D-Q + 2 sk ) - imbal 23 Skew-olerant Domino Overlap clocks: x evaluates before y precharges implicit latch between φ1 and φ2 no need for latch between domino phases From [Harris] 24 12

13 Multiple Phases 25 ime Borrowing 26 13

14 echnology Strategy / Roadmap Plan A: Extending Si CMOS R D Plan B: Subsytem Integration R D Plan C: Post Si CMOS Options R R&D Plan Q: Quantum Computing R.C. Chen, Where Si-CMOS is going: rendy Hype vs. Real echnology, ISSCC 06 D 27 Next Lecture Finish timing Asynchronous design 28 14