TAU 2015 Contest Incremental Timing Analysis and Incremental Common Path Pessimism Removal (CPPR) Contest Education. v1.9 January 19 th, 2015

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1 TU 2015 Contest Incremental Timing nalysis and Incremental Common Path Pessimism Removal CPPR Contest Education v1.9 January 19 th, Contents 1 Introduction 2 2 Static Timing nalysis ST Timing Propagation Interconnect Modeling Circuit Element Modeling Common Path Pessimism Removal CPPR 9 4 CPPR Example 11 5 Timing-driven Operations 13 6 Updates 14 1

2 1 Introduction The goal of the TU 2015 Contest is to have participants perform incremental timing analysis with common path pessimism removal CPPR capabilities. mong timing analysis applications, timing-driven operations are imperative for the success of optimization flows, such as placement, routing, logic synthesis, and physical synthesis. Optimization transforms change the design, and therefore have the potential to significantly affect timing information. s such, timing must be kept current to ensure slack integrity and timing closure, and updating timing information quickly and accurately is crucial for reasonable turnaround time and performance. This document outlines the technical concepts related to the TU 2015 Incremental Timing and CPPR Contest, including timing calculation and propagation and common path pessimism removal. For contest file formats, including input files and deliverables, please refer to contest file formats.pdf, which is posted on the contest website above. For contest logistics, deadlines and any other updates, please refer to the contest website. The remainder of this document is structured as follows. Section 2 introduces static timing analysis ST. Section 3 provides a conceptual understanding of common path pessimism removal CPPR, with an illustrated example in Section 4. Section 5 introduces the relevant commands to be supported in this contest. 2 Static Timing nalysis ST Primary Inputs Primary Outputs Input Slew s i d Y Output Slew s oy circuit Interconnect Circuit Element Input Slew s ib B d B Y Y Figure 1: Generic circuit left and delay model representation of a circuit element right. Timing analysis computes the amount of time signals propagate in a circuit from its primary inputs PIs to its primary outputs POs through various circuit elements and interconnect. Signals arriving at an input of an element will be available at its outputs at some later time; each element therefore introduces a delay during signal propagation. Furthermore, assume that signal transitions are characterized by their input slew and their output slew, 2

3 which is defined as the amount of time required for a signal to transition from high-to-low or low-to-high. 1 For example, as shown in Figure 1 right, the delay across the circuit element from input to output Y is designated by d Y, the input slew at by s i, and the output slew at Y by s oy. Here, both the delay and the output slew are functions of input slew. Section 2.1 will outline timing propagation, while Sections 2.2 and 2.3 will describe delay modeling. 2.1 Timing Propagation Starting from the primary inputs, we quantify the instant that a signal reaches an input or output of a circuit element as the arrival time at. Similarly, starting from the primary outputs, we quantify the limits imposed for each arrival time to ensure proper circuit operation as the required arrival time rat. Given an arrival time and a required arrival time, we define the slack at a circuit node to a measurement of how well timing constraints are met. That is, a positive slack means the required time is satisfied, and a negative slack means the required time is in violation. To account for multiple sources of within-chip variation, such as manufacturing variations, temperature fluctuation, voltage drops, and electromigration, the timing analysis is typically done using an early/late split, where each circuit node has an early lower bound and a late upper bound on its time. 2 By convention, if the early or late mode is not explicitly stated, both modes will be need to be considered. For example, a generic output slew s o that is a function of input slew s i implies that the early mode s early o is a function of early mode s early i, and the late mode s late o is a function of late mode s late ctual arrival time. Starting from the primary inputs, arrival times at are computed by adding delays across a path, and performing the minimum in early mode or maximum in late mode of such accumulated times at a convergence point. That is, in early mode, we are concerned with computing the earliest time instant that a signal transition can reach any given circuit node. For example, let at early and at early B in Figure 1 right. Then the early mode arrival time at the output pin Y will be at early Y = min i. to be the early arrival times at pins and B at early + d early Y, atearly B + d early B Y Conversely, in late mode, we are concerned with computing the latest time instant that a signal transition can reach any given circuit node. Following the same example in Figure 1 right, the late mode arrival time at Y will be at late Y = max at late + d late Y, at late B + d late B Y Required arrival time. Starting from the primary outputs, required arrival times rat are computed by subtracting the delays across a path, and performing the maximum in early mode or minimum in late mode of such accumulated times at a convergence point. That is, in early mode, we are concerned with computing the earliest time instant that a signal 1 Here, a low high signal is defined as 10% 90% of the voltage. 2 This is typically done by derating an existing delay value, e.g., by ±5%. For the purposes of this contest, we will base the delays on early and late input slews see Sections 2.2 and

4 transition must reach any circuit node. For example, in Figure 2 left, the early mode required arrival time at the input pin Z will be rat early Z = max rat early T 1 d early Z T 1, rat early T 2 d early Z T 2 3 Conversely, in late mode, we are concerned with computing the latest time instant that a signal transition must reach any given circuit node. Following the same example in Figure 2 left, the late mode required arrival time at the input pin Z will be rat late Z = min rat late T 1 d late Z T 1, rat late T 2 d late Z T 2 Slacks. For proper circuit operation, the following conditions must hold: 4 at early rat early 5 at late rat late 6 To quantify how well timing constraints are met at each circuit node, slacks slack can be computed based on Equations 5 and 6. That is, slacks are positive when the required times are met, and negative otherwise. slack early = at early rat early 7 slack late = rat late at late 8 Slew propagation. s circuit element delays and interconnect delays are a function of the input slew s i, the subsequent output slew s o must be propagated. In this contest, we will assume worst-slew propagation, where we propagate the smallest largest slew in early late mode. Following the example in Figure 1 right, the early mode and late output slew at output pin Y are, respectively: s early oy = min s early oy searly i, searly oby searly ib 9 s late oy = max s late oy s late i, s late oby s late ib 10 Transitions. For each timing arc, delay and output slew values will propagate only for transitions that exist. For example, suppose there two timing arcs in serial, where the first timing arc propagates rise-to-rise R R and fall-to-fall F F, and the second timing arc propagates fall-to-rise F R. fter timing analysis, the only valid output transition at the second timing arc will be rise R. The delay through both the timing arcs is the sum of the delay for the F F transition in first arc plus the delay for the second arc for the F R transition in the second arc. Note that the delay for the R R delay from the first arc is not used, and the fall arrival time for the second arc is undefined. For this contest, an undefined early late arrival time is set as , and an undefined early late required arrival time is set as

5 Port Taps Input Slew s iz Output Slew s ot1 C 1 1 R R C T 1 C 4 Z T 1 d Z T1 T 1 Z R R B 3 C 3 T 2 Z d Z T2 Output Slew s ot2 T 2 2 T 2 C 2 R E C 5 Figure 2: Generic interconnect left, its timing model center and RC network right. 2.2 Interconnect Modeling The basic instance of interconnect wire is a net, which is assumed to have an input pin P ort and one or more output pins T aps, as illustrated in Figure 2 left. Parasitic RC trees only contain grounded capacitors and floating resistors we will not include the discussion of coupling capacitors or grounded resistors. elay. The computation of port-to-tap delays can be accurately performed through electrical simulation. However, and for the sake of simplicity and speed, we will assume the simpler Elmore delay model [1], where the delay is approximated by the symmetric of the value of the first moment of the impulse response. To compute the delay of RC tree networks, we summarize the topological method provided in [4]. In an RC network, consider any two nodes e and k. Let C k be the lumped capacitance at node k, and let R k e be the total resistance of the common path between the paths from P ort to e and P ort to k. For example, in Figure 2 right, the resistance between nodes 1 and T 2 R 1 T2 is R, as that is the only common resistor between the paths Z to 1 and Z to T 2. The Elmore delay at node e is d e = k N R k e C k 11 where N is the set of all nodes in the RC network. For the example net illustrated in Figure 2 right, the delay at node T 2 tap is visiting in order nodes 1, T 1, 3, 2, T 2 : d T2 = R C 1 + R C 3 + R C 4 + R + R B C 2 + R + R B + R E C 5 12 = R C 1 + C 3 + C 4 + R + R B C 2 + R + R B + R E C 5 Output slew. The value of the output slew s o on any given tap node T can be approximated by a two-step process. First, compute the output slew of the impulse response on T, which was observed [1, 2] to be well-approximated by 2 ŝ ot 2β T d T 13 5

6 where β T is the second moment of the input response at node T, and d T is the corresponding Elmore delay from Equation 11. Second, compute the slew of the response to the input ramp by the expression given in [3] s ot s i2 + ŝ 2 ot 14 where s i is the input slew. 1 T 1 Z C 1 d 1 R R B 3 R C R C 3 d 3 C 4 d 4 C 2 d 2 2 R E T 2 C 5 d 5 Figure 3: Modified RC network for output slew calculation. The value of β T can be computed through the efficient path-tracing algorithm for moment computation proposed in [5], which is a generalization of the algorithm proposed in [1]. To calculate β T, first replace all capacitance values C k in the RC network by C k d k, where d k is the Elmore delay from Equation 11 see Figure 3. Second, follow the same procedure as before for finding β T β T = R k T C k d k 15 k N Following the example in Figure 3, at node T 2, we have β T2 = R C 1 d 1 + C 3 d 3 + C 4 d 4 + R + R B C 2 d 2 + R + R B + R E C 5 d Circuit Element Modeling For delay and output slew calculations between two pins, the information will be given in the.lib file as two-dimensional tables. To find the corresponding timing information, extrapolation or interpolation will be necessary. If the table contains a single value, i.e., a 1x1 table Figure 4 left, no interpolation is necessary. That is, regardless of input x and y, the corresponding value is constant. If the table is one-dimensional, i.e., a 1xn table or a mx1 table Figure 4 center, then the value will depend only on the non-scalar dimension. For example, consider the 1x4 table in Figure 4. If y < y1, then the corresponding output z value will be the linear extrapolation between z 1 and z 2. If y 2 y y 3, then z will be the linear interpolation between z 2 and z 3. If y 4 < y, then z 6

7 y x z x x 1 x 2 x 3 y 1 z 1 y 1 z 11 z 21 z 31 x x 2 x 3 y 2 z 2 y 2 z 12 z 22 z 32 y z 1 z 2 z 3 y 3 y 4 z 3 z 4 y 3 y 4 z 13 z 14 z 23 z 24 z 33 z 34 1x1 Table 3x1 Table 1x4 Table 3x4 Table Figure 4: Illustration of different tables: scalar, one-dimensional, and two-dimensional. will be the linear extrapolation between z 3 and z 4. z 1 y 1 y z 2 z 1 y 2 y 1 if y < y 1 17 z 1 if y = y 1 18 z 1 + y y 1 z 2 z 1 y 2 y 1 if y 1 < y < y 2 19 z 2 if y = y 2 20 z 2 + y y 2 z 3 z 2 y 3 y 2 if y 2 < y < y 3 21 z 3 if y = y 3 22 z 3 + y y 3 z 4 z 3 y 4 y 3 if y 3 < y < y 4 23 z 4 if y = y 4 24 z 4 + y y 4 z 4 z 3 y 4 y 3 if y > y 4 25 If the table is two-dimensional, perform linear interpolation on the x values first, then perform linear interpolation on the y values. For example, consider the 3x4 table in Figure 4. If x 2 < x < x 3 and y 2 < y < y 3, then i determine z first by linear interpolation on z 22 and z 32, ii determine z second by linear interpolation on z 23 and z 33, and then iii determine z by linear interpolation using z first and z second. Combinational elements. For a given combinational cell, e.g., OR gate, let the delay d and output slew s o for a input/output pin-pair see Figure 5 be calculated by non-linear delay model interpolation/extrapolation. These delay and output slew tables are stored in the.lib, and are referenced by the input slew x and driving load y. C L denotes the equivalent downstream capacitance seen from the output pin of the cell. Several sophisticated models have been proposed for computing C L. For simplicity, the application of such models is considered to be out of the scope of the present contest, and a simple model is adopted. C L is assumed to be the sum of all the capacitances in the parasitic RC tree, including the cell pin capacitances at the taps of the interconnect network. 7

8 Input Slew s i d Y Output Slew s oy B Y Input Slew s ib B d B Y Y B C I C IB Y C L Figure 5: Combinational OR gate left, its timing model center and capacitances right. Sequential elements. Sequential circuits consist of combinational blocks interleaved by registers, usually implemented with flip-flops FFs. Typically, sequential circuits are composed of d several stages, where a register captures data from the outputs of a combinational block from d a previous stage, and injects itd Y B into the inputs of the combinational block in the next stage. Register operation is synchronized by clock signals generated by one or multiple clock sources. Clock signals that reach distinct flip-flops, e.g., sinks in the clock tree, are delayed from the clock source by a clock latency l. flip-flop is a storage element that captures a given logic value at its input data pin, when a given clock edge is detected at its clock pin CK, and subsequently presents the captured value and its complement at the output pins Q and Q. The flip-flop also enables asynchronous preset set and clear reset of the output pins through the respective S and R input pins. 3 FF 1 Combinational Logic FF 2 Q Q Q Setup Hold Setup Hold d CK Q d comb Setup Hold d CK Q CK CLOCK l i CK l o CK Figure 6: Generic flip-flop and its timing model left, and two FFs in series and their timing models right. Setup and hold constraints. Proper operation of a flip-flop requires the logic value of the input data pin to be stable for a specific period of time before the capturing clock edge. This period of time is designated by the setup time t setup. dditionally, the logic value of the input data pin must also be stable for a specific period of time after the capturing clock edge. This period of time is designated by the hold time t hold. The flip-flop timing models are depicted in 3 The complement, preset and clear signals are stated here for completeness. For the purposes of the contest, their behavior will be ignored. 8

9 Figure 6 left. The test time are given in the.lib as two-dimensional tables, and are referenced by the clock-side input slew x and the data-side input slew y. Signal propagation. Consider the standard signal transition between two flip-flops as illustrated in Figure 6 right. ssuming that the clock edge is generated at the source at time 0, it will reach the injecting launching flip-flop F F 1 at time l i, making the data available at the input of the combinational block d CK Q time later. If the propagation delay in the combinational block is d comb, then the data will be available at the input of the capturing flip-flop F F 2 at time l i + d CK Q + d comb. Let the clock period to be a constant T. Then the next clock edge will reach F F 2 at time T + l o. For correct operation, the data must be be available at the input pin of F F 2 t setup time before the next clock edge. Therefore, at the data input pin of F F 2, we have the following: at late rat setup = rat late = li late + d CK Q + d late comb 26 = T + lo early t setup 27 similar condition can be derived for ensuring that the hold time is respected. The data input pin of F F 2 must remain stable for at least t hold time after the clock edge reaches the corresponding CK pin. Therefore, at the data input pin of F F 2, we have the following: at early rat hold = rat early = l early i + d CK Q + d early comb 28 = lo late + t hold 29 Note that when computing the required arrival times in Equations 27 and 29, the value l o is specific to Figure 6. In the general case, l o should be replaced with at C. The previous arrival times and required arrival times induce setup and hold slacks, which can be computed from Equations 7 and 8. For the clock pins of the flip-flop, the required arrival time is derived from the test slack. For early mode, the slack at the clock pin is the setup or late test slack, and for late mode, the slack at the clock pin is the hold or early test slack. From the corresponding test slack and arrival time, the clock required arrival time can be derived, and appropriately propagated. 3 Common Path Pessimism Removal CPPR The early-late split-timing analysis has greatly enabled timers to effectively account for any within-chip variation effects. However, this dual-mode analysis inherently embeds unnecessary pessimism, which can lead to an over-conservative design. Consider the example in Figure 7, where we analyze the slack of a typical hold setup test. When we perform our dual-mode analysis, we compare the early late data s arrival time against the late early clock s arrival time. However, along the physically-common portion of the data path and clock path in the clock tree, the signal cannot simultaneously experience the effects accounted for during early and late mode operation, e.g., the signal cannot be both at high voltage and low voltage. s a result, this unnecessary pessimism can lead to tests being marked as failing having negative slack, when in actuality, they should be passing having positive slack. Therefore, this unnecessary pessimism should not be included when reporting final timing results. 9

10 Q Launching FF Capturing FF t H t S CK CLOCK Combinational Logic ata Path Common Point Clock Path Figure 7: Inherent but unnecessary pessimism introduced by the early/late timing split. To the first order, the amount of pessimism for a given test can be approximated by the difference in the early and late arrival times at the common point see Figure 7. However, the common point is found by backwards tracing from the data and clock for the path with the worst slack. In the general case, there can be multiple paths converging at the data input of a flip-flop, and every path will have its own amount of undue pessimism. Therefore, to find the correct credit or slack, we need to take the minimum credit found across all paths. Hold tests. For tests that compare the data point against the clock point for the same cycle, e.g., where data must be stable after the clock signal arrives at the capturing flip-flop, the total pessimism incurred is the difference between the early and late arrival times at the common point. That is, any on-chip variation incurred is spatially and temporally the same. For a hold test T hold that has one data path that share common elements and common edges, the amount of credit given back is credit hold = at late cp at early cp 30 where cp is the last point before the data path and clock path diverge see Figure 7. Setup tests. For tests that compare the data point against the clock point in subsequent cycles, e.g., where the data must be stable before the clock signal arrives at the capturing flip-flop, the total pessimism incurred is the summation of the difference of early and late delays up through the common point. While the data and clock path share the same physical components, they are launched at different clock cycles. Therefore, if some on-chip variation, e.g., temperature fluctuation occurs when the data is launched, but does not occur when the data is captured, the pessimism was now necessary, and cannot be removed. For a setup test T setup that has one data path sharing common elements and common edges, the amount of credit given back is credit setup = p P V,E d late p d early p 31 where P V, E is the physically-common path between the data and clock paths. Here, V is the set of all common circuit elements, and E is the set of all common interconnect. Following the example in Figure 7, the amount of credit for the setup test is credit setup = d late w 1 d early w 1 +d late d early +d late w 2 d early w 2 +d late B 2 d early B 2 +d late w 3 d early w 3 32 Total test credit. s removing pessimism for each test could require investigating multiple paths, the amount of credit per test will be defined as the difference between the post- and 10

11 pre-cppr test slack. For this contest, we will only consider hold and setup tests. credit setup test = slack setup post CP P R slacksetup pre CP P R 33 credit hold test = slackpost CP hold P R slackpre CP hold P R 34 When analyzing CPPR credit, only consider the credit that comes from paths with nonpositive slack. 4 CPPR Example Consider the following sample circuit in Figure 8, where two data paths feed a common latch F F 3. Using the following timing information, we will determine the CPPR credit for the setup test at F F 3. Please note that this example is used for conceptual understanding only. Your implementation should leverage runtime improvements. ssume that all wire delays are zero, and all arrival times are zero. d early = 20 d late = 25 d late OR2: OR:Y = d late OR2:B OR:Y = 50 d early B 2 = 10 d late B 2 = 30 d late F F 1 :CK F F 1 :Q = d late F F 2 :CK F F 2 :Q = 40 d early = 10 d late = 45 T CLOCK = 120 d early B 4 = 10 d late B 4 = 30 t setup F F 3 = 30 First, we find the data path slacks at F F 3 :. We do this by comparing the late data arrival time and the late required arrival time at F F 3 :. Using Equation 27 in Equation 35, we obtain slack late F F 3 : = rat late F F 3 : at late F F 3 : 35 slack F F3 : = T CLOCK + at early F F 3 :CK tsetup F F 3 at late F F 3 : 36 We now find the pre-cppr slacks for each path. Consider ata Path 1 P 1, where its timing is determined by going through the path Using Equations 36 and 26, we obtain: CLOCK B 2 F F 1 OR2 F F 3 slackf late F 3 : P1 = T CLOCK + d early + d early + d early B 4 t setup d late OR2: OR2:Y + d late F F 1:CK F F 1:Q + d late B 2 + d late = = 15 Similarly, for ata Path 2 P 2, its path 11

12 IN 1 FF 1 Q Clock Path ata Path 1 ata Path 2 B 2 CK OR2 B Y FF 3 Setup Hold Q OUT IN 2 FF 2 Q CK CLOCK CK B 4 Figure 8: Example sequential circuit. has pre-cppr path slack CLOCK F F 2 OR2 F F 3 slackf late F 3 : P2 = T CLOCK + d early + d early + d early B 4 t setup d late OR2:B OR2:Y + d late F F 2:CK F F 2:Q + d late + d late = = 30 We now compute the CPPR credit for each path Equation 33. Without loss of generality, we will process paths in order of criticality, i.e., most negative to least negative. Starting with P 2, its common portion with the clock path contains and. Therefore, its credit is credit setup P2 = d late d early + d late d early = = 40 Similarly for P 1, its CPPR credit can be computed by finding the common portion, i.e., : credit setup P1 = d late d early = = 5 The post-cppr path slacks for P 1 and P 2 are: slackf late F 3 : post CP P R P 1 = slackf late F 3 : P1 + credit setup P1 = = 10 slackf late F 3 : post CP P R P 2 = slackf late F 3 : P2 + credit setup P2 = = 10 12

13 From this example, we make two observations. i The most critical path pre-cppr is not necessarily reflective of the true critical path. This emphasizes the importance of CPPR analysis, and highlights its impact on chip performance. ii uring CPPR, analyzing the single-most critical path can be insufficient. In our example, if we only applied credit according to P 2, the most critical pre-cppr path, we would assume the test slack would be positive, i.e., passing. In actuality, the next-most critical path is still failing. 5 Timing-driven Operations This section lists the expected supported set of operations from contestants. For a detailed explanation of each command and syntax, please refer to contest file formats.pdf. insertion and removal of a gate insertion and removal of a net re-analyze timing 13

14 6 Updates 01/19/2015 [v1.9]: corrected the derivation for slack at the clock pin. 01/13/2015 [v1.8]: clarified to only consider CPPR credit if the associated path is failing non-positive slack. 01/06/2015 [v1.7]: corrected Equation 25 to be y > y 4 instead of y < y 4. 12/16/2014 [v1.6]: changed newly-added text from updates to be blue. 12/15/2014 [v1.5]: add text to clarify the computation of C L for combinational delay and output slew calculations Section 2.3[Combinational elements]. 12/12/2014 [v1.4]: add text to clarify clock pin calcuations for sequential elements Section 2.3[Sequential elements]. 11/12/2014 [v1.3]: corrected Equation 13 to be the difference of two terms, not sum. 10/01/2014 [v1.2]: release version. 14

15 References [1] W. C. Elmore, The Transient Response of amped Linear Networks with Particular Regard to Wide-band mpliers, Journal of pplied Physics, , pp [2] R. Gupta, B. Tutuianu and L. T. Pileggi, The Elmore elay as a Bound for RC Trees with Generalized Input Signals, IEEE Transactions on Computer-aided esign of Integrated Circuits and Systems, , pp [3] C. V. Kashyap, C. J. lpert, F. Liu and. evgan, Closed-form Expressions for Extending Step elay and Slew Metrics to Ramp Inputs for RC Trees, IEEE Transactions on Computer-aided esign of Integrated Circuits and Systems, , pp [4] P. Penfield Jr. and J. Rubinstein, Signal elay in RC Tree Networks, Proc. esign utomation Conference, 1981, pp [5] C. L. Ratzlaff and L. T. Pillage, RICE: Rapid Interconnect Circuit Evaluation Using WE, IEEE Transactions on Computer-aided esign of Integrated Circuits and Systems, , pp

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