DIVISION BY DIGIT RECURRENCE

Size: px
Start display at page:

Download "DIVISION BY DIGIT RECURRENCE"

Transcription

1 DIVISION BY DIGIT RECURRENCE 1 SEVERAL DIVISION METHODS: DIGIT-RECURRENCE METHOD studied in this chapter MULTIPLICATIVE METHOD (Chapter 7) VARIOUS APPROXIMATION METHODS (power series expansion), SPECIAL METHODS SUCH AS CORDIC (Chapter 11) AND CONTINUED PRODUCT METHODS. IMPLEMENTATIONS: SEQUENTIAL COMBINATIONAL 1. PIPELINED 2. NONPIPELINED COMBINATIONAL/SEQUENTIAL

2 DEFINITION AND NOTATION 2 DIVIDEND x DIVISOR d QUOTIENT q REMAINDER rem rem < d ulp INTEGER QUOTIENT: ulp = 1, x = q d + rem FRACTIONAL QUOTIENT: ulp = r n TWO TYPES OF DIVISION OPERATION: and sign(rem) = sign(x) 1. INTEGER DIVISION, WITH INTEGER OPERANDS AND RESULT USUALLY REQUIRES AN EXACT REMAINDER 2. FRACTIONAL DIVISION TO AVOID QUOTIENT OVERFLOW: x < d QUOTIENT ROUNDED, WHICH CAN RESULT IN A NEGATIVE REMAIN- DER

3 FRACTIONAL DIVISION - ASSUMPTIONS 3 OPERANDS/RESULT IN SIGN-AND-MAGNITUDE FORMAT = CONSIDER MAGNITUDES ONLY 1/2 d < 1; x < d; 0 < q < 1 FOR SIMPLER SELECTION: q j D a = { a, a+1,..., 1, 0, 1,...,a 1,a} REDUNDANCY FACTOR ρ = a r 1, 1 2 < ρ 1

4 RECURRENCE 4 QUOTIENT AFTER j STEPS: q[j] = q[0] + j i=1 q i r i FINAL QUOTIENT: q = q[n] = q[0] + n i=1 q i r i FINAL QUOTIENT ERROR BOUND: 0 ǫ q = x d q < r n ERROR AT STEP j: ǫ[j] = x d q[j] ǫ[n] + n FOR CONVERGENCE: ǫ[j] ρr j i=j+1 max(q i)r i = ǫ[n] + FOR SIMPLER SELECTION, ALLOW NEGATIVE ERRORS a r 1 (r j r n ) ǫ[j] = x d q[j] ρr j ELIMINATE DIVISION FROM ERROR BOUND: x dq[j] ρdr j DEFINE RESIDUAL (PARTIAL REMAINDER): w[j] = r j (x dq[j]) RESIDUAL RECURRENCE: w[j + 1] = rw[j] dq j+1 w[0] = x

5 cont. 5 BOUND ON w[j]: w[j] ρd SELECT QUOTIENT DIGIT TO KEEP w[j + 1] BOUNDED: q j+1 = SEL(rw[j], d) REDUNDANCY IN QUOTIENT-DIGIT SET ALLOWS q j+1 = SEL(ŷ, d) WHERE ŷ IS TRUNCATED rw[j], etc.

6 IMPLEMENTATION OF DIVISION STEP 6 1. ONE DIGIT ARITHMETIC LEFT-SHIFT OF w[j] TO PRODUCE rw[j]; 2. DETERMINATION OF THE QUOTIENT DIGIT q j+1 BY THE QUOTIENT-DIGIT SELECTION FUNCTION; 3. GENERATION OF THE DIVISOR MULTIPLE d q j+1 ; and 4. SUBTRACTION OF dq j+1 from rw[j]. 5. UPDATE OF THE QUOTIENT q[j] TO q[j + 1] BY THE ON-THE-FLY CONVERSION q[j + 1] = CONV (q[j],q j+1 )

7 7 w[j] - present residual ARITHMETIC LEFT SHIFT d - divisor rw[j] - shifted residual y d SEL q j+1 selection dq j+1 subtraction rw[j] q j+1 DIVISOR MULTIPLE GENERATION SUBTRACTION dq j+1 quotient update (on-the-fly) recurrence step time (b) w[j+1] - next residual QUOTIENT CONVERSION q j+1 (a) q[j+1] Figure 5.1: (a) COMPONENTS OF A DIVISION STEP. (b) TIMING.

8 MAIN FACTORS AFFECTING COST AND EXECUTION TIME 8 RADIX r QUOTIENT-DIGIT SET 1. CANONICAL: 0 q j r 1 2. REDUNDANT: q j D a = { a, a + 1,..., 1, 0, 1,...,a 1, a} REDUNDANCY FACTOR: ρ = a r 1, ρ > 1 2 REPRESENTATION OF RESIDUAL: 1. NONREDUNDANT (e.g., 2 s complement) 2. REDUNDANT: carry-save, signed-digit QUOTIENT-DIGIT SELECTION FUNCTION

9 INITIALIZATION AND TERMINATION 9 Initialization: w[0] = x dq[0] and w[0] ρd. Options: Make q[0] = 0 and For ρ = 1 we make w[0] = x/2. For 1/2 < ρ < 1 we make w[0] = x/4 Compensated in the termination step Make q[0] = 1 and w[0] = x d. Applicable for ρ < 1 because q > 1 +ρ not allowed. Termination: QUOTIENT: q = q[n] if w[n] 0 q[n] r N if w[n] < 0 N number of iterations If dividend shifted in initialization - shift quotient (extra iteration)

10 ON-THE-FLY QUOTIENT CONVERSION 10 j MS DIGITS OF CONVERTED QUOTIENT UPDATE Q[j] = j i=1 q ir i Q[j + 1] = Q[j] + q j+1 r (j+1) SINCE q j+1 CAN BE NEGATIVE: Q[j + 1] = Q[j] + q j+1 r (j+1) if q j+1 0 Q[j] r j + (r q j+1 )r (j+1) if q j+1 < 0 DISADVANTAGE: SUBTRACTION Q[j] r j REQUIRES THE PROPAGATION OF A BORROW SLOW

11 ON-THE-FLY CONVERSION (cont.) 11 DEFINE ANOTHER FORM QM[j] QM[j] = Q[j] r j NEW CONVERSION ALGORITHM IS Q[j + 1] = Q[j] + q j+1 r (j+1) if q j+1 0 QM[j] + (r q j+1 )r (j+1) if q j+1 < 0 SUBTRACTION REPLACED BY LOADING THE FORM QM[j] UPDATE FORM QM[j] AS FOLLOWS: QM[j + 1] = Q[j + 1] r (j+1) = ALL ADDITIONS ARE CONCATENATIONS Q[j] + (q j+1 1)r (j+1) if q j+1 > 0 QM[j] + ((r 1) q j+1 )r (j+1) if q j+1 0

12 ON-THE-FLY CONVERSION ALGORITHM 12 Q[j + 1] = QM[j + 1] = (Q[j],q j+1 ) if q j+1 0 (QM[j], (r q j+1 )) if q j+1 < 0 (Q[j],q j+1 1) if q j+1 > 0 (QM[j], ((r 1) q j+1 )) if q j+1 0 INITIAL CONDITIONS Q[0] = QM[0] = 0 (for a positive quotient)

13 EXAMPLE OF RADIX-2 CONVERSION 13 j q j Q[j] QM[j]

14 IMPLEMENTATION OF THE CONVERSION 14 Q 2-1 MUX QM load select q Q REG Q QM 2-1 MUX Q in load select LOAD & SHIFT-IN CONTROL q j+1 QM REG QM in QM Q QM Figure 5.2: Implementation of on-the-fly conversion. shift Q with insert (Q in ) if C shiftq = 1 shift QM with insert (Q in ) if C loadq = 1 shift QM with insert (QM in ) if C shiftqm = 1 shift Q with insert (QM in ) if C loadqm = 1

15 cont. 15 Q in = QM in = q j+1 if q j+1 0 r q j+1 if q j+1 < 0 q j+1 1 if q j+1 > 0 (r 1) q j+1 if q j+1 0 REGISTER CONTROL SIGNALS: C loadq = C shiftq and C loadqm = C shiftqm

16 EXAMPLE OF RADIX-4 CONVERSION 16 q j+1 Q in C shiftq Q[j + 1] QM in C shiftqm QM[j + 1] (Q[j], 3) 2 0 (Q[j], 2) (Q[j], 2) 1 0 (Q[j], 1) (Q[j], 1) 0 0 (Q[j], 0) (Q[j], 0) 3 1 (QM[j], 3) (QM[j], 3) 2 1 (QM[j], 2) (QM[j], 2) 1 1 (QM[j], 1) (QM[j], 1) 0 1 (QM[j], 0)

17 x 17 INITIAL STEP w[0] d q[j+1] RESIDUAL REG w[j] RECURRENCE STEP w[j+1] w[n] TERMINAL STEP x INITIAL STEP w[0] RESIDUAL REG w[ik] d (a) q x INITIAL STEP w[0] REC. STEP w[1] REC. STEP w[2] q 1 q 2 COMBINATIONAL ON-THE-FLY CONVERTER & TERMINAL STEP d q ik+1 REC. STEP w[ik+1] q ik+2 REC. STEP w[ik+2] q (i+1)k REC. STEP w[(i+1)k] (c) w[n] COMBINATIONAL ON-THE-FLY CONVERTER & TERMINAL STEP q q N REC. STEP w[n] (b) q Figure 5.3: DIVISION IMPLEMENTATION: (a) TOTALLY SEQUENTIAL. (b) TOTALLY COMBINATIONAL. (c) COMBINED IMPLEMENTATION.

18 EXAMPLES OF ALGORITHMS AND IMPLEMENTATIONS 18 CELLS: delay function of the load; delay and area in terms of 2-NAND. DEGREE OF OPTIMIZATION: the same modules have been used in all designs. INTERCONNECTIONS NOT INCLUDED: not considered the delay, area nor load of interconnections. EXECUTION TIME AND THE AREA FOR 53-BIT OPERANDS AND RE- SULT INCLUDED DELAY AND AREA OF REGISTERS

19 SCHEMES COMPARED 19 r2 Scheme Radix-2 with carry-save residual. r4 Scheme Radix-4 with a = 2 and carry-save residual. r8 Scheme Radix-8 with a = 7 and carry-save residual. r16over Scheme Radix-16 with two overlapped radix-4 stages. r512 Scheme Radix-512 with a = 511, carry-save residual, scaling, and quotientdigit selection by rounding.

20 20 2-input MUX 3-input MUX: Delay: 1.6 Area: input MUX: Delay: 1.8 Area: 5.6 [3:2] MODULE (FULL ADDER) g a b c p a b c HA g p HA* Delay: 1.4 Area: 3.0 (a) vci+1 vsi Delays: BUFFER Delay: 1.8 Area:2.6 (b) REGISTER CELL SET D Q CK Delay: 4.0 Area: 4.0 vci+1 vsi (c) a,b to vsi: 4.2 c to vsi: 2.2 a,b to vci+1 : 3.8 c to vci+1: 2.0 Area: 6.7 [4:2] MODULE a b c d a b b c c a a b c d t i+1 [4:2] Module t i vc i vc i+1 vs i Delays: to ti+1: 1.6 t i+1 d 0 1 MUX t i to vci+1: 5.6 vc i to vsi: 6.0 Area: 15.5 vc i+1 (d) vs i Figure 5.4: Basic modules: (a) Multiplexers. (b) Buffer and register cell. (c) Full-adder. (d) [4:2] module.

21 RADIX-2 DIVISION WITH CS RESIDUAL 21 REDUNDANT RESIDUAL w[j] = (W C[j], W S[j]) 1. [Initialize] WS[0] x/2; WC[0] 0; q 0 0;Q[-1]=0 2. [Recurrence] for j = 0... n + 1 (n + 2 iterations because of initialization and guard bit) q j+1 SEL(ŷ); (WC[j + 1], WS[j + 1]) CSADD(2WC[j], 2WS[j], q j+1 d); Q[j] CONV ERT(Q[j 1], q j ) end for 3. [T erminate] If w[n + 2] < 0 then q = 2(CONV ERT(Q[n + 1], q n+2 1)) else q = 2(CONV ERT(Q[n + 1], q n+2 ))

22 RADIX-2 ALGORITHM (cont.) 22 n is the precision in bits, SEL is the quotient-digit selection function: 1 if 0 ŷ 3/2 q j+1 = SEL(ŷ) = 0 if ŷ = 1/2 1 if 5/2 ŷ 1 The estimate ŷ has four bits (three integer bits and one fractional bit) of the shifted residual in carry-save form, CSADD is carry-save addition q j+1 d is in 2 s complement form, and CON V ERT on-the-fly quotient conversion function

23 Dividend x = ( ), divisor d = ( ), scaled residual 2w[0] = 2(x/2) = x, q computed = q/2 23 2W S[0] = WC[0] = ŷ[0] = 0.5 q 1 = 1 q 1 d = W S[1] = WC[1] = ŷ[0] = 1 q 2 = 1 q 2 d = W S[2] = WC[2] = ŷ[1] = 0.5 q 3 = 1 q 3 d = W S[3] = WC[3] = ŷ[2] = 0 q 4 = 1 q 4 d = W S[4] = WC[4] = ŷ[4] = 1.5 q 5 = 1 q 5 d = * for 2 s complement of q j+1 d q = 2( ) =.1101 Figure 5.7: Example of radix-2 division with residual in carry-save form.

24 Divisor d WC[0] = 0 WC[j+1] WS[0] = x /2 WS[j+1] 24 q j+1 buffers 2 Reg. D Reg. WC Reg. WS d d 2WC[j] 4 2WS[j] 2-1 MUX {d, 0, d} c b [3:2] SZ; Convert q a q - WS[j+1] WC[j+1] qj+1 4 qsel qsel buff MUX HA* REG [3:2] adder HA qj+1 q + q critical path Modules defined in Fig. 5.4 Figure 5.8: IMPLEMENTATION OF RADIX-2 SCHEME.

25 DELAY AND AREA OF RADIX-2 STAGE 25 element delay area q-digit selection buffers MUX CSA registers (3) Convert & Round (NC) 1360 Cycle time 16.2 Total area 2585 NC denotes a delay not in the critical path

26 RADIX-4 DIVISION WITH CS RESIDUAL QUOTIENT DIGIT SET {-2,-1,0,1,2} 2. ρ < 1 initialize WS[0] x/4 3. THE NEXT RESIDUAL (WC[j + 1], WS[j + 1]) CSADD(4WC[j], 4WS[j], q j+1 d) 4. QUOTIENT-DIGIT SELECTION DEPENDS ON ESTIMATES OF SHIFTED RESIDUAL AND DIVISOR described in terms of SELECTION CONSTANTS m k (i) q j+1 = k if m k (i) ŷ < m k+1 (i) 5. FINAL QUOTIENT = 4 x OBTAINED QUOTIENT

27 SELECTION CONSTANTS 27 q j+1 = k if m k (i) ŷ < m k+1 (i) i = 16 ˆd and ˆd divisor truncated to the 4th fractional bit and ŷ is 4w[j] truncated to the 4th fractional bit. i m 2 (i) m 1 (i) m 0 (i) m 1 (i) : real value = shown value/16

28 Dividend x = ( ), divisor d = ( ) (i = 16(0.1100) 2 = 12) scaled residual 4w[0] = 4(x/4) = x, q computed = q/4 28 4WS[0] + = WC[0] + = ŷ[0] = 10/16 q 1 = 1 q 1 d + = W S[1] = W C[1] = WS[1] + = WC[1] + = ŷ[1] = 6/16 q 2 = 0 q 2 d + = W S[2] = W C[2] = WS[2] + = WC[2] + = ŷ[2] = 22/16 q 3 = 2 q 3 d + = w[3] = * least-significant 1 for 2 s complement of q j+1 d + only one integer bit used in the recurrence, because of the range of w[j + 1]. q[3] = = Figure 5.9: Example of radix-4 division with residual in carry-save form.(on-the-fly conversion and termination not shown)

29 DELAY AND AREA OF RADIX-4 STAGE 29 element delay area q-digit selection buffers MUX CSA registers (3) Convert & Round (NC) 1360 Cycle time 20.6 Total area 2840 NC denotes a delay not in the critical path

30 Divisor d WC[0]=0 WC[j+1] WS[0] = x /4 WS[j+1] 30 q j+1 buffers 4 Reg. D Reg. WC Reg. WS d d 4WC[j] 7 4WS[j] 4-1 MUX 7 qsel 3 {2d, d, 0, d, 2d} c b a [3:2] SZ; Convert (q j+1 < 0) WS[j+1] WC[j+1] 4 {d} 4 q j+1 q [3:2] adder (q2 +, q2 -, q1 +, q1 - ) qj+1 = 0 coded as (0, 0, 0, 0) 2.2 qsel buff MUX HA* REG HA critical path Modules defined in Fig. 5.4 Figure 5.10: IMPLEMENTATION OF RADIX-4 SCHEME.

31 RADIX-8 DIVISION WITH CS RESIDUAL 31 QUOTIENT DIGIT SET {-7,..., 7} DECOMPOSED INTO AND q H = { 8, 4, 0, 4, 8} q L = { 2, 1, 0, 1, 2} element delay area q-digit selection (q h ) buffers MUXes CSAh CSAl registers (3) Convert & Round (NC) 1360 Cycle time 26.2 Total area 3960

32 Divisor d WC[0]=0 WC[j+1] WS[0]=x/2 WS[j+1] 32 q H j+1 4 q L j+1 4 buffers buffers Reg. D Reg. WC Reg. WS d d 8WC[j] 8 8WS[j] 4-1 MUX {8d, 4d, 0, 4d, 8d} d 4-1 MUX d [3:2] (q H j+1 < 0) 8 qsel 4 4 q q H j+1 q L j+1 : j+1 (decoded as in Fig. 5.10) 3 {d} 4 {2d, d, 0, d, 2d} [3:2] SZ; Convert q (q L j+1 < 0) WS[j+1] WC[j+1] (q H j+1,q L j+1) q H j qsel buff MUX HA* HA REG HA 4.2 qsel buff MUX HA* q L j+1 Modules defined in Fig. 5.4 critical path Figure 5.11: Implementation of radix-8 scheme.

33 RADIX-16 DIVISION WITH TWO RADIX-4 OVERLAPPED STAGES 33 element delay area CSA q-digit selection MUX 1.4 buffers MUXes CSA1 (NC) 360 CSA registers (3) Convert & Round (NC) 1360 Cycle time 26.6 Total area 4390

34 34 Divisor d WC[0]=0 WC[j+2] WS[0]=x/4 WS[j+2] q j+1 4 buffers Reg. D Reg. WC Reg. WS d d 4WC[j] 4WS[j] 4-1 MUX q j+2 4 buffers {2d, d, 0, d, 2d} d 4-1 MUX {2d, d, 0, d, 2d} [3:2] d WS[j+1] WS[j+2] [3:2] (q j+1 < 0) WC[j+1] 4W[j+1] (q j+2 < 0) WC[j+2] (a) 4WS[j] 4WC[j] x x x. x x x x x x x x x x. x x x x x x x {4W[j]} 7 {4W[j]} 7 7 most 8 least {2d} 7 {d} 7 {d} 7 {2d} 7 8 least 7 most {d} qsel [3:2] [3:2] [3:2] [3:2] qsel qsel qsel qsel qsel 5-1 MUX Conditional truncated q j+1 q j+2 (b) residuals Figure 5.12: Implementation of radix-16 with radix-4 stages.

35 35 CSA2 q j+1 qsel buff MUX CSA HA REG 4 q j+2 [3:2] 8 qsel MUX buff MUX HA* 2.2 Modules defined in Fig. 5.4 critical path Figure 5.13: Critical path in radix-16 scheme.

36 RADIX-512 DIVISION WITH PRESCALING AND SELECTION BY ROUNDING 36 Cycle 1 : COMPUTE M 1/d; compare d and x and set g Cycle 2 : COMPUTE z = Md (in c-s form); v = 2 g x Cycle 3 : INITIALIZE w[0] = Mv (in c-s form); ASSIMILATE z; Cycles 4 to 9 : ITERATE q j+1 = round(ŷ); w[j + 1] = 512w[j] q j+1 z Cycle 10 : CORRECTING AND ROUNDING.

37 RADIX-512 DIVISON (cont.) 37 RECTANGULAR MULTIPLIER-ACCUMULATOR DELAY-AREA element delay area M-module (NC) 1800 MUX 1.4 recoder buffer 1.8 MUX levels of 4-2 CSA registers(3) Convert & Round (NC) 1360 Cycle time 27 Total area 9980

38 Module M 15 {d} 15 x d (Initialization not shown) 38 scale/iterate MUX M MUX z q j+1 Round & Recode M ; q j+1 MULTIPLIER - ACCUMULATOR Md; Mx; 512w -qz = w[j] WC[j+1] WS[j+1] W WC[j] WS[j] 2(10+2) CPA WC[j+1] WS[j+1] SZ; CONVERT q j+1 q Figure 5.14: Implementation of radix-512 scheme.

39 OVERALL COMPARISONS 39 Scheme r2 r4 r8 r16 (overlapped) r512 Cycle-time factor Number of cycles Speedup Area factor Correction: two cycles for radix-2, one cycle for other cases.

40 QUOTIENT-DIGIT SELECTION FUNCTION 40 Quotient-digit set: Redundancy factor: q j+1 D a = { a, a + 1,..., 1, 0, 1,...,a 1,a} ρ = a r 1, 1 2 < ρ 1 TWO FUNDAMENTAL CONDITIONS FOR q-selection CONTAINMENT must guarantee bounded residual CONTINUITY there must exist a valid choice of q j+1 in the range of shifted residual

41 CONTAINMENT AND SELECTION INTERVALS 41 RESIDUAL RECURRENCE w[j + 1] = rw[j] dq j+1 w[j] ρd ρ = a/(r 1) a q j a SELECTION INTERVALS If rw[j] [L k,u k ] then q j+1 = k makes w[j + 1] bounded L k rw[j] U k ρd w[j + 1] = rw[j] k d ρd EXPRESSIONS FOR SELECTION INTERVALS U k = (k + ρ)d L k = (k ρ)d

42 ROBERTSON S AND P-D DIAGRAMS 42 w[j+1] ρd -a k a -rρd -ad -d d rw[5] kd ad rρd rw[j] w[6] -ρd L k U k (a) Figure 5.16: ROBERTSON S DIAGRAM

43 rw[j] U a =rρd 43 k>0 selection region for q j+1 =k U k L k U 0 0 d L 0 U k k<0 L k (b) L -a =-rρd Figure 5.16: P-D DIAGRAM (for d > 0).

44 CONTINUITY CONDITION, OVERLAP, AND Q-DIGIT SELECTION 44 q j+1 = SEL(w[j],d) SEL represented by the set {s k }, a k a, q j+1 = k if s k rw[j] s k+1 ulp s k defined as the minimum value of rw[j] for which q j+1 = k s k s are functions of the divisor d CONTAINMENT: L k s k U k CONTINUITY: q j+1 = k 1 for rw[j] = s k ulp U k 1 U k U k 1 + ulp L k s k U k 1 + ulp or L k s k U k 1 OVERLAP RESULTING IN U k 1 L k = (k 1 + ρ)d (k ρ)d = (2ρ 1)d ρ 2 1 REDUNDANCY IN q-digit SET OVERLAP BETWEEN SELECTION INTERVALS - SIMPLER SELECTION

45 45 w[j+1] q j+1 =k-1 q j+1 =k rw[j] L k-1 k-1 L k k or k-1 Uk-1 overlap k U k (a) Figure 5.17: Overlap between selection intervals.

46 46 rw[j] U k-1 s k L k q j+1 =k overlap (k or k-1) q j+1 =k-1 1/2 normalized divisor range (b) 1 d Figure 5.17: Selection function.

47 SELECTION USING CONSTANTS 47 USE CONSTANTS m k, INDEPENDENT OF DIVISOR max(l k ) m k min(u k 1 ) + ulp max and min for the range 2 1 d < 1 For k > 0 which requires For k 0 which requires (k ρ) m k (k 1 + ρ)2 1 + ulp ρ k (k ρ)2 1 k 1 + ρ ρ ( k) + 2 3

48 48 rw[j] U k-1 m k L k k>0 1/2 1 k<0 d m k U k-1 L k Figure 5.18: BOUNDS ON m k.

49 RADIX-2 DIVISION WITH NON-REDUNDANT RESIDUAL 49 EXTENSION OF NON-RESTORING DIVISION: {-1,0,1} SRT ALLOWS SKIPPING OVER ZEROS SELECTION CONSTANTS: U 1 = 2d L 1 = 0 U 0 = d 1/2 L 0 = d 1/2 U 1 = 0 L 1 = 2d 0 m 1 1/2, 1/2 m 0 0 Choose: m 1 = 1/2 and m 0 = 1/2 THE QUOTIENT-DIGIT SELECTION FUNCTION 1 if 1/2 2w[j] q j+1 = 0 if 1/2 2w[j] < 1/2 1 if 2w[j] < 1/2

50 w[j+1] 50 d d -1/2 1/2 2w[j] -d d 2d -d L -1 U -1 L 1 U 1 L 0 U (a)

51 2w[j] 51 2 U 1 q j+1 =1 1 U 0 1/2 m 1 =1/2 U -1 d 1/2 L 1 1 q j+1 =0-1/2 m 0 =-1/2 L 0-1 L -1 q j+1 =-1-2

52 STAIRCASE SELECTION FUNCTION 52 FOR r > 2, m k DEPENDS ON DIVISOR DIVIDE RANGE OF DIVISOR INTO INTERVALS [d i,d i+1 ) with d 0 = 1 2, d i+1 = d i + 2 δ δ MS FRACTIONAL BITS OF DIVISOR REPRESENT THE INTERVAL FOR EACH INTERVAL, THERE IS A SET of selection constants m k (i) for d [d i, d i+1 ), q j+1 = k if m k (i) rw[j] m k+1 (i) ulp

53 DEFINITION OF m k (i) 53 rw[j] m k+1 (i) q j+1 =k+1 ulp q j+1 =k m k (i) d 2 -δ d i d i+1 Figure 5.20: DEFINITION OF m k (i).

54 RANGE CONDITION FOR SELECTION CONSTANTS 54 max(l k (d i ), L k (d i+1 )) m k (i) min(u k 1 (d i ), U k 1 (d i+1 )) + ulp rw[j] min(u k-1 (d i ), U k-1 (d i+1 )) region for m k (i) U k-1 L k max(l k (d i ), L k (d i+1 )) d 2 -δ d i d i+1 Figure 5.21: SELECTION CONSTANT REGION.

55 LOW-PRECISION SELECTION CONSTANTS 55 m k (i) = A k (i)2 c WHERE A k (i) IS INTEGER CAN USE TRUNCATED RESIDUAL IN COMPARISONS WITH SELECTION CONSTANTS RESIDUAL MUST BE IN 2 s COMPLEMENT SELECTION CONDITIONS for k > 0 L k (d i + 2 δ ) A k (i)2 c U k 1 (d i ) for k 0 L k (d i ) A k (i)2 c U k 1 (d i + 2 δ ) + ulp (5.1)

56 USE OF SELECTION CONSTANTS 56 rw[j] U k-1 2 -c m k (4) L k m k (2,3) m k (1) m k (0) 2 -δ d d 0 d 2 d 3 d 4 d 5 d 1 Figure 5.22: QUOTIENT-DIGIT SELECTION WITH SELECTION CONSTANTS.

57 SELECTION WITH TRUNCATED RESIDUAL AND DIVISOR log 2 r + c {rw [j ]} c log 2 r + c + δ SELECTION FUNCTION δ 1 {d } δ q j+1 Figure 5.23: SELECTION WITH TRUNCATED RESIDUAL AND DIVISOR.

58 LOWER BOUND ON δ 58 CONSIDER CASE k > 0 (similar argument for k 0); FROM CONTINUITY CONDITION = U k 1 (d i ) L k (d i + 2 δ ) 0 (ρ + k 1)d i ( ρ + k)(d i + 2 δ ) 0 Worst case: d 1/2 and k a: (2ρ 1)d i (k ρ)2 δ 2 δ 2ρ 1 2(a ρ) = 2ρ 1 2ρ(r 2) MINIMUM VALUE OF δ CAN RESULT IN A LARGE VALUE OF c OPTIMIZE THE VALUES OF δ AND c TOGETHER

59 RADIX-4 DIVISION WITH NONREDUNDANT RESIDUAL 59 Known as Robertson s division q j { 2, 1, 0, 1, 2} U k = ( k)d BOUND ON δ L k = ( k)d 2 δ 2ρ 1 2(a ρ) = 1 8

60 60 4w[j] U U 1 L 2 2d/3 w[j+1] 1 1 U d/3 4d/3 2d/3 5d/3 8d/3 4w[j] d=1/2 0 1 L 1 U -1 d -2d/3 (a) -1-1 L 0 U L -1 L -2 Figure 5.24: ROBERTSON S AND PD DIAGRAMS FOR RADIX-4 AND a = 2. (b)

61 [d i,d i+1 ) + [8, 9) [9, 10) [10, 11) [11, 12) L 2 (d i+1 ), U 1 (d i ) # 36, 40 40, 45 44, 50 48, 55 m 2 (i) L 1 (d i+1 ), U 0 (d i ) # 9,16 10, 18 11, 20 12, 22 m 1 (i) L 0 (d i ), U 1 (d i+1 ) # -16, -9-18, , , -12 m 0 (i) L 1 (d i ),U 2 (d i+1 ) # -40, , , , -48 m 1 (i) [d i,d i+1 ) + [12, 13) [13, 14) [14, 15) [15, 16) L 2 (d i+1 ), U 1 (d i ) # 52, 60 56, 65 60, 70 64, 75 m 2 (i) L 1 (d i+1 ), U 0 (d i ) # 13, 24 14, 26 15, 28 16, 30 m 1 (i) L 0 (d i ), U 1 (d i+1 ) # -24, , , , -16 m 0 (i) L 1 (d i ),U 2 (d i+1 ) # -60, , , , -64 m 1 (i)

62 QUOTIENT-DIGIT SELECTION FOR RADIX-4 DIVISION; NON-REDUNDANT RESIDUAL 62 {4w[j]} 3 U 1 m 2 (7) m 2 (4,5,6) 12/8 11/8 10/8 9/8 L 2 q j+1 =2 {4w[j]} 3 xxx.xxx 6 {d} 4 0.1xxx 3 m 2 (2,3) 1 SELECTION m 2 (1) m 2 (0) 7/8 6/8 q j+1 =1 3 5/8 q j+1 1/2 10/16 12/16 14/16 1 {d} 4 (b) 9/16 11/16 13/16 15/16 (a) Figure 5.25: QUOTIENT-DIGIT SELECTION: (a) FRAGMENT OF THE P-D DIAGRAM. (b) IMPLEMENTATION.

63 USE OF REDUNDANT ADDER 63 SO FAR: COMPUTE rw[j] IN FULL PRECISION, TRUNCATE, AND COM- PARE WITH LOW-PRECISION CONSTANTS FULL-PRECISION ADDITION: significant portion of the cycle time OVERLAP BETWEEN SELECTION INTERVALS = COULD USE AN ESTIMATE OF rw[j] ERROR IN ESTIMATE: ǫ min y ŷ ǫ max BASIC CONSTRAINT: if we choose q j+1 = k for an estimate ŷ then y [ŷ + ǫ min, ŷ + ǫ max ] L k = L k ǫ min U k = U k ǫ max

64 CONSTRAINTS ON SELECTION CONSTANTS 64 max(l k(d i ),L k(d i+1 )) m k (i) min(u k 1(d i ),U k 1(d i+1 )) U k-1 U* k-1 region for m k (i) ε max L* k ε min L k d i d i+1 Figure 5.26: CONSTRAINTS FOR SELECTION BASED ON ESTIMATES.

65 MINIMUM OVERLAP AND RANGE OF ESTIMATE 65 OVERLAP min(uk 1(d i ),Uk 1(d i+1 )) max(l k(d i ), L k(d i+1 )) 0 RANGE rw[j] rρd < rρ (for d < 1) rρ ǫ max < ŷ < rρ ǫ min y=rw[j] ε max -ε min -rρ y (estimate) rρ Figure 5.27: RANGE OF ESTIMATE

66 REDUNDANT ADDER 66 -q j+1 d rw[j] (redundant) (a) REDUNDANT ADDER w[j+1] (redundant) ws wc x x - x x + x. x. +. x x + t x x + x x + x x + x x + x x + x x + x x + rw[j] x + - x + - x. x t x + - x + - x + - x + - x + - x + - x + - rw[j] y - y^ y + y. y +. + y y + (estimate) 0 < ε < 2 -t+1 -ulp + (truncation error) y + - y^ y. y y y (estimate) y + - -(2 -t -ulp) < ε < (truncation error) 2 -t -ulp (b) (c) Figure 5.28: USE OF REDUNDANT ADDER: (a) Redundant adder. (b) Carry-save case. (c) Signed-digit case.

67 CARRY-SAVE ADDER 67 ERRORS ǫ min = 0 ǫ max = 2 t+1 ulp RESTRICTED SELECTION INTERVAL U k = U k 2 t+1 + ulp L k = L k U k 1 = Uk t t = U k 1 2 t t L k = L k t = L k t

68 y U k t Case B ^ U k-1 U* k-1 (represented by ) 2 -t+1 Case A ^ L k L k (represented by ) L* k d d d i i+1 i+2 Case A: U * k-1 is on the grid; U k-1 = U * k-1 +2-t on the grid Case B: U * k-1 is off the grid; U k-1 > U * k-1 on the grid Figure 5.29: Û and L for residual in carry-save form.

69 LOWER BOUND FOR t and δ 69 (for positive k) U k 1 (d i ) L k (d i+1 ) 0 U k 1 (d i ) 2 t L k (d i+1 ) 0 RANGE 2ρ 1 2 (a ρ)2 δ 2 t rρ 2 t t ŷ rρ ulp t z t = 2 t 2 t z

70 RADIX-2 DIVISION WITH CARRY-SAVE ADDER δ 2 t max( L k (d i ), L k (d i+1 )) m k (i) min(ûk 1(d i ),Ûk 1(d i+1 )) L 1 (1) = 0 U 0 (1/2) = 0 L 0 (1/2) = 1/2 U 1 (1) = 1/2 ( L 1 (1) = 0) m 1 (Û0(1/2) = 0) ( L 0 (1/2) = 1/2) m 0 (Û 1(1) = 1/2) This results in the selection constants m 1 = 0 and m 0 = 1/2

71 SELECTION FUNCTION ŷ 2 ulp ŷ 3/2 q j+1 = 1 if 0 ŷ 3/2 0 if ŷ = 1/2 1 if 5/2 ŷ 1

72 RADIX-2 WITH CSA: PD PLOT 72 2w[j] 2 3/2 U 1 y[j] ^ x x x. x x x x. x 1 U y[j] ^ U^ 0 1/2 0-1/2 L ^ m(0)=-1/ /2 q j+1 =1 q j+1 =0 q j+1 =-1 m(1)=0 ^ L 1 U^ U* 0 L, 1 U -1 U* -1 L 0, L* 0 d SELECTION FUNCTION q j+1 (b) -2-5/2 d=1/2 (a) d=1-ulp L -1 Figure 5.30: RADIX-2 DIVISION WITH CARRY-SAVE ADDER: (a) P-D PLOT. (b) SELECTION FUNCTION.

73 IMPLEMENTATION 73 q j+1 = (q s,q m ) where and q m = (p 1 p 0 p 1 ) (5.2) q s = p 2 (g 1 + p 1 g 0 + p 1 p 0 g 1 ) p i = c i s i g i = c i s i (c 2, c 1, c 0, c 1 ) (s 2,s 1, s 0,s 1 ) q j+1 = 0 (q s, q m ) = (1, 0)

74 RADIX-4 ALGORITHM WITH CARRY-SAVE ADDER δ 2 t 2 t = /3 1/16 4 ŷ 8/3 ulp ŷ 42 16

75 [d i, d i+1 ) + [8, 9) [9, 10) [10, 11) [11, 12) 75 L 2 (d i+1 ),Û1(d i ) + 12, 12 14, 14 15, 15 16, 17 m 2 (i) L 1 (d i+1 ),Û0(d i ) + 3, 4 4, 5 4, 5 4, 6 m 1 (i) L 0 (d i ),Û 1(d i+1 ) + -5, -4-6, -5-6, -5-7, -5 m 0 (i) L 1 (d i ),Û 2(d i+1 ) + -13, , , , -17 m 1 (i) [d i, d i+1 ) + [12, 13) [13, 14) [14, 15) [15, 16) L 2 (d i+1 ),Û1(d i ) + 18, 19 19, 20 20, 22 22, 24 m 2 (i) L 1 (d i+1 ),Û0(d i ) + 4, 7 5, 7 5, 8 6, 9 m 1 (i) L 0 (d i ),Û 1(d i+1 ) + -8, -6-8, -6-9, -6-10, -7 m 0 (i) L 1 (d i ),Û 2(d i+1 ) + -20, , , , -23 m 1 (i) : real value = shown value/16; L k = L k 4, Ûk = U k

76 76 y[j] ^ U 1 U^ 1 12/8 L^ 2 11/8 L 2 10/8 9/8 y^ x x x.x x x x x x x d^ 1 SELECTION FUNCTION 7/8 q j+1 (b) 6/8 5/8 1/2 9/16 10/16 11/16 12/16 13/16 14/16 15/16 1 ^ d m 2 (i) region of choice for m 2 (i) (a) Figure 5.31: SELECTION FUNCTION FOR RADIX-4 SCHEME WITH CARRY-SAVE ADDER: (a) Fragment of P-D diagram. (b) Implementation.

Chapter 5: Solutions to Exercises

Chapter 5: Solutions to Exercises 1 DIGITAL ARITHMETIC Miloš D. Ercegovac and Tomás Lang Morgan Kaufmann Publishers, an imprint of Elsevier Science, c 2004 Updated: September 9, 2003 Chapter 5: Solutions to Selected Exercises With contributions

More information

Chapter 6: Solutions to Exercises

Chapter 6: Solutions to Exercises 1 DIGITAL ARITHMETIC Miloš D. Ercegovac and Tomás Lang Morgan Kaufmann Publishers, an imprint of Elsevier Science, c 00 Updated: September 3, 003 With contributions by Elisardo Antelo and Fabrizio Lamberti

More information

DIGIT-SERIAL ARITHMETIC

DIGIT-SERIAL ARITHMETIC DIGIT-SERIAL ARITHMETIC 1 Modes of operation:lsdf and MSDF Algorithm and implementation models LSDF arithmetic MSDF: Online arithmetic TIMING PARAMETERS 2 radix-r number system: conventional and redundant

More information

Design and FPGA Implementation of Radix-10 Algorithm for Division with Limited Precision Primitives

Design and FPGA Implementation of Radix-10 Algorithm for Division with Limited Precision Primitives Design and FPGA Implementation of Radix-10 Algorithm for Division with Limited Precision Primitives Miloš D. Ercegovac Computer Science Department Univ. of California at Los Angeles California Robert McIlhenny

More information

Chapter 1: Solutions to Exercises

Chapter 1: Solutions to Exercises 1 DIGITAL ARITHMETIC Miloš D. Ercegovac and Tomás Lang Morgan Kaufmann Publishers, an imprint of Elsevier, c 2004 Exercise 1.1 (a) 1. 9 bits since 2 8 297 2 9 2. 3 radix-8 digits since 8 2 297 8 3 3. 3

More information

Hardware Design I Chap. 4 Representative combinational logic

Hardware Design I Chap. 4 Representative combinational logic Hardware Design I Chap. 4 Representative combinational logic E-mail: shimada@is.naist.jp Already optimized circuits There are many optimized circuits which are well used You can reduce your design workload

More information

VLSI Arithmetic. Lecture 9: Carry-Save and Multi-Operand Addition. Prof. Vojin G. Oklobdzija University of California

VLSI Arithmetic. Lecture 9: Carry-Save and Multi-Operand Addition. Prof. Vojin G. Oklobdzija University of California VLSI Arithmetic Lecture 9: Carry-Save and Multi-Operand Addition Prof. Vojin G. Oklobdzija University of California http://www.ece.ucdavis.edu/acsel Carry-Save Addition* *from Parhami 2 June 18, 2003 Carry-Save

More information

9. Datapath Design. Jacob Abraham. Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017

9. Datapath Design. Jacob Abraham. Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 9. Datapath Design Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 October 2, 2017 ECE Department, University of Texas at Austin

More information

Graduate Institute of Electronics Engineering, NTU Basic Division Scheme

Graduate Institute of Electronics Engineering, NTU Basic Division Scheme Basic Division Scheme 台灣大學電子所吳安宇博士 2002 ACCESS IC LAB Outline Shift/subtract division algorithm. Programmed division. Restoring hardware dividers. Nonstoring and signed division. Radix-2 SRT divisioin.

More information

Lecture 11. Advanced Dividers

Lecture 11. Advanced Dividers Lecture 11 Advanced Dividers Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 15 Variation in Dividers 15.3, Combinational and Array Dividers Chapter 16, Division

More information

Chapter 8: Solutions to Exercises

Chapter 8: Solutions to Exercises 1 DIGITAL ARITHMETIC Miloš D. Ercegovac and Tomás Lang Morgan Kaufmann Publishers, an imprint of Elsevier Science, c 2004 with contributions by Fabrizio Lamberti Exercise 8.1 Fixed-point representation

More information

Lecture 8: Sequential Multipliers

Lecture 8: Sequential Multipliers Lecture 8: Sequential Multipliers ECE 645 Computer Arithmetic 3/25/08 ECE 645 Computer Arithmetic Lecture Roadmap Sequential Multipliers Unsigned Signed Radix-2 Booth Recoding High-Radix Multiplication

More information

CS 140 Lecture 14 Standard Combinational Modules

CS 140 Lecture 14 Standard Combinational Modules CS 14 Lecture 14 Standard Combinational Modules Professor CK Cheng CSE Dept. UC San Diego Some slides from Harris and Harris 1 Part III. Standard Modules A. Interconnect B. Operators. Adders Multiplier

More information

Radix-4 Vectoring CORDIC Algorithm and Architectures. July 1998 Technical Report No: UMA-DAC-98/20

Radix-4 Vectoring CORDIC Algorithm and Architectures. July 1998 Technical Report No: UMA-DAC-98/20 Radix-4 Vectoring CORDIC Algorithm and Architectures J. Villalba E. Antelo J.D. Bruguera E.L. Zapata July 1998 Technical Report No: UMA-DAC-98/20 Published in: J. of VLSI Signal Processing Systems for

More information

Binary Multipliers. Reading: Study Chapter 3. The key trick of multiplication is memorizing a digit-to-digit table Everything else was just adding

Binary Multipliers. Reading: Study Chapter 3. The key trick of multiplication is memorizing a digit-to-digit table Everything else was just adding Binary Multipliers The key trick of multiplication is memorizing a digit-to-digit table Everything else was just adding 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 4 6 8 2 4 6 8 3 3 6 9 2 5 8 2 24 27 4 4 8 2 6

More information

Cost/Performance Tradeoff of n-select Square Root Implementations

Cost/Performance Tradeoff of n-select Square Root Implementations Australian Computer Science Communications, Vol.22, No.4, 2, pp.9 6, IEEE Comp. Society Press Cost/Performance Tradeoff of n-select Square Root Implementations Wanming Chu and Yamin Li Computer Architecture

More information

A Hardware-Oriented Method for Evaluating Complex Polynomials

A Hardware-Oriented Method for Evaluating Complex Polynomials A Hardware-Oriented Method for Evaluating Complex Polynomials Miloš D Ercegovac Computer Science Department University of California at Los Angeles Los Angeles, CA 90095, USA milos@csuclaedu Jean-Michel

More information

ARITHMETIC COMBINATIONAL MODULES AND NETWORKS

ARITHMETIC COMBINATIONAL MODULES AND NETWORKS ARITHMETIC COMBINATIONAL MODULES AND NETWORKS 1 SPECIFICATION OF ADDER MODULES FOR POSITIVE INTEGERS HALF-ADDER AND FULL-ADDER MODULES CARRY-RIPPLE AND CARRY-LOOKAHEAD ADDER MODULES NETWORKS OF ADDER MODULES

More information

Part VI Function Evaluation

Part VI Function Evaluation Part VI Function Evaluation Parts Chapters I. Number Representation 1. 2. 3. 4. Numbers and Arithmetic Representing Signed Numbers Redundant Number Systems Residue Number Systems Elementary Operations

More information

ALU (3) - Division Algorithms

ALU (3) - Division Algorithms HUMBOLDT-UNIVERSITÄT ZU BERLIN INSTITUT FÜR INFORMATIK Lecture 12 ALU (3) - Division Algorithms Sommersemester 2002 Leitung: Prof. Dr. Miroslaw Malek www.informatik.hu-berlin.de/rok/ca CA - XII - ALU(3)

More information

What s the Deal? MULTIPLICATION. Time to multiply

What s the Deal? MULTIPLICATION. Time to multiply What s the Deal? MULTIPLICATION Time to multiply Multiplying two numbers requires a multiply Luckily, in binary that s just an AND gate! 0*0=0, 0*1=0, 1*0=0, 1*1=1 Generate a bunch of partial products

More information

Tunable Floating-Point for Energy Efficient Accelerators

Tunable Floating-Point for Energy Efficient Accelerators Tunable Floating-Point for Energy Efficient Accelerators Alberto Nannarelli DTU Compute, Technical University of Denmark 25 th IEEE Symposium on Computer Arithmetic A. Nannarelli (DTU Compute) Tunable

More information

Chapter 5 Arithmetic Circuits

Chapter 5 Arithmetic Circuits Chapter 5 Arithmetic Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 11, 2016 Table of Contents 1 Iterative Designs 2 Adders 3 High-Speed

More information

Adders, subtractors comparators, multipliers and other ALU elements

Adders, subtractors comparators, multipliers and other ALU elements CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Instructor: Mohsen Imani UC San Diego Slides from: Prof.Tajana Simunic Rosing

More information

Svoboda-Tung Division With No Compensation

Svoboda-Tung Division With No Compensation Svoboda-Tung Division With No Compensation Luis MONTALVO (IEEE Student Member), Alain GUYOT Integrated Systems Design Group, TIMA/INPG 46, Av. Félix Viallet, 38031 Grenoble Cedex, France. E-mail: montalvo@archi.imag.fr

More information

Adders, subtractors comparators, multipliers and other ALU elements

Adders, subtractors comparators, multipliers and other ALU elements CSE4: Components and Design Techniques for Digital Systems Adders, subtractors comparators, multipliers and other ALU elements Adders 2 Circuit Delay Transistors have instrinsic resistance and capacitance

More information

Lecture 8. Sequential Multipliers

Lecture 8. Sequential Multipliers Lecture 8 Sequential Multipliers Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 9, Basic Multiplication Scheme Chapter 10, High-Radix Multipliers Chapter

More information

EECS150 - Digital Design Lecture 24 - Arithmetic Blocks, Part 2 + Shifters

EECS150 - Digital Design Lecture 24 - Arithmetic Blocks, Part 2 + Shifters EECS150 - Digital Design Lecture 24 - Arithmetic Blocks, Part 2 + Shifters April 15, 2010 John Wawrzynek 1 Multiplication a 3 a 2 a 1 a 0 Multiplicand b 3 b 2 b 1 b 0 Multiplier X a 3 b 0 a 2 b 0 a 1 b

More information

COMPUTERS ORGANIZATION 2ND YEAR COMPUTE SCIENCE MANAGEMENT ENGINEERING UNIT 3 - ARITMETHIC-LOGIC UNIT JOSÉ GARCÍA RODRÍGUEZ JOSÉ ANTONIO SERRA PÉREZ

COMPUTERS ORGANIZATION 2ND YEAR COMPUTE SCIENCE MANAGEMENT ENGINEERING UNIT 3 - ARITMETHIC-LOGIC UNIT JOSÉ GARCÍA RODRÍGUEZ JOSÉ ANTONIO SERRA PÉREZ OMUTERS ORGANIZATION 2ND YEAR OMUTE SIENE MANAGEMENT ENGINEERING UNIT 3 - ARITMETHI-LOGI UNIT JOSÉ GARÍA RODRÍGUEZ JOSÉ ANTONIO SERRA ÉREZ Tema 3. La Unidad entral de roceso. A.L.U. Arithmetic Logic Unit

More information

International Association of Scientific Innovation and Research (IASIR) (An Association Unifying the Sciences, Engineering, and Applied Research)

International Association of Scientific Innovation and Research (IASIR) (An Association Unifying the Sciences, Engineering, and Applied Research) International Association of Scientific Innovation and Research (IASIR) (An Association Unifying the Sciences, Engineering, and Applied Research) International Journal of Emerging Technologies in Computational

More information

DIVIDER IMPLEMENTATION

DIVIDER IMPLEMENTATION c n = cn-= DAIL LLAOCCA CLab@OU DIVID IPLTATIO The division of two unsigned integer numbers A (where A is the dividend and the divisor), results in a quotient and a residue. These quantities are related

More information

Design and Implementation of a Radix-4 Complex Division Unit with Prescaling

Design and Implementation of a Radix-4 Complex Division Unit with Prescaling esign and Implementation of a Radix-4 Complex ivision Unit with Prescaling Pouya ormiani Computer Science epartment University of California at Los Angeles Los Angeles, CA 90024, USA Email: pouya@cs.ucla.edu

More information

Complement Arithmetic

Complement Arithmetic Complement Arithmetic Objectives In this lesson, you will learn: How additions and subtractions are performed using the complement representation, What is the Overflow condition, and How to perform arithmetic

More information

CSE140: Components and Design Techniques for Digital Systems. Decoders, adders, comparators, multipliers and other ALU elements. Tajana Simunic Rosing

CSE140: Components and Design Techniques for Digital Systems. Decoders, adders, comparators, multipliers and other ALU elements. Tajana Simunic Rosing CSE4: Components and Design Techniques for Digital Systems Decoders, adders, comparators, multipliers and other ALU elements Tajana Simunic Rosing Mux, Demux Encoder, Decoder 2 Transmission Gate: Mux/Tristate

More information

Residue Number Systems Ivor Page 1

Residue Number Systems Ivor Page 1 Residue Number Systems 1 Residue Number Systems Ivor Page 1 7.1 Arithmetic in a modulus system The great speed of arithmetic in Residue Number Systems (RNS) comes from a simple theorem from number theory:

More information

CMP 334: Seventh Class

CMP 334: Seventh Class CMP 334: Seventh Class Performance HW 5 solution Averages and weighted averages (review) Amdahl's law Ripple-carry adder circuits Binary addition Half-adder circuits Full-adder circuits Subtraction, negative

More information

Logic and Computer Design Fundamentals. Chapter 5 Arithmetic Functions and Circuits

Logic and Computer Design Fundamentals. Chapter 5 Arithmetic Functions and Circuits Logic and Computer Design Fundamentals Chapter 5 Arithmetic Functions and Circuits Arithmetic functions Operate on binary vectors Use the same subfunction in each bit position Can design functional block

More information

A 32-bit Decimal Floating-Point Logarithmic Converter

A 32-bit Decimal Floating-Point Logarithmic Converter A 3-bit Decimal Floating-Point Logarithmic Converter Dongdong Chen 1, Yu Zhang 1, Younhee Choi 1, Moon Ho Lee, Seok-Bum Ko 1, Department of Electrical and Computer Engineering, University of Saskatchewan

More information

ECE380 Digital Logic. Positional representation

ECE380 Digital Logic. Positional representation ECE380 Digital Logic Number Representation and Arithmetic Circuits: Number Representation and Unsigned Addition Dr. D. J. Jackson Lecture 16-1 Positional representation First consider integers Begin with

More information

Tree and Array Multipliers Ivor Page 1

Tree and Array Multipliers Ivor Page 1 Tree and Array Multipliers 1 Tree and Array Multipliers Ivor Page 1 11.1 Tree Multipliers In Figure 1 seven input operands are combined by a tree of CSAs. The final level of the tree is a carry-completion

More information

In the 1960's, the term "Op Art" was coined to describe the work of a growing group of abstract painters. This movement was led by Vasarely.

In the 1960's, the term Op Art was coined to describe the work of a growing group of abstract painters. This movement was led by Vasarely. In the 1960's, the term "Op Art" was coined to describe the work of a growing group of abstract painters. This movement was led by Vasarely. Preliminary version Range: From logic gate to combinatorial

More information

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1> Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building

More information

Low Power Division and Square Root

Low Power Division and Square Root UNIVERSITY OF CALIFORNIA, IRVINE Low Power Division and Square Root DISSERTATION submitted in partial satisfaction of the requirements for the degree of DOCTOR OF PHILOSOPHY in Engineering by Alberto Nannarelli

More information

Proposal to Improve Data Format Conversions for a Hybrid Number System Processor

Proposal to Improve Data Format Conversions for a Hybrid Number System Processor Proceedings of the 11th WSEAS International Conference on COMPUTERS, Agios Nikolaos, Crete Island, Greece, July 6-8, 007 653 Proposal to Improve Data Format Conversions for a Hybrid Number System Processor

More information

A HIGH-SPEED PROCESSOR FOR RECTANGULAR-TO-POLAR CONVERSION WITH APPLICATIONS IN DIGITAL COMMUNICATIONS *

A HIGH-SPEED PROCESSOR FOR RECTANGULAR-TO-POLAR CONVERSION WITH APPLICATIONS IN DIGITAL COMMUNICATIONS * Copyright IEEE 999: Published in the Proceedings of Globecom 999, Rio de Janeiro, Dec 5-9, 999 A HIGH-SPEED PROCESSOR FOR RECTAGULAR-TO-POLAR COVERSIO WITH APPLICATIOS I DIGITAL COMMUICATIOS * Dengwei

More information

Carry Look Ahead Adders

Carry Look Ahead Adders Carry Look Ahead Adders Lesson Objectives: The objectives of this lesson are to learn about: 1. Carry Look Ahead Adder circuit. 2. Binary Parallel Adder/Subtractor circuit. 3. BCD adder circuit. 4. Binary

More information

Multiplication Ivor Page 1

Multiplication Ivor Page 1 Multiplication 1 Multiplication Ivor Page 1 10.1 Shift/Add Multiplication Algorithms We will adopt the notation, a Multiplicand a k 1 a k 2 a 1 a 0 b Multiplier x k 1 x k 2 x 1 x 0 p Product p 2k 1 p 2k

More information

Proposal to Improve Data Format Conversions for a Hybrid Number System Processor

Proposal to Improve Data Format Conversions for a Hybrid Number System Processor Proposal to Improve Data Format Conversions for a Hybrid Number System Processor LUCIAN JURCA, DANIEL-IOAN CURIAC, AUREL GONTEAN, FLORIN ALEXA Department of Applied Electronics, Department of Automation

More information

A VLSI Algorithm for Modular Multiplication/Division

A VLSI Algorithm for Modular Multiplication/Division A VLSI Algorithm for Modular Multiplication/Division Marcelo E. Kaihara and Naofumi Takagi Department of Information Engineering Nagoya University Nagoya, 464-8603, Japan mkaihara@takagi.nuie.nagoya-u.ac.jp

More information

Parallel Multipliers. Dr. Shoab Khan

Parallel Multipliers. Dr. Shoab Khan Parallel Multipliers Dr. Shoab Khan String Property 7=111=8-1=1001 31= 1 1 1 1 1 =32-1 Or 1 0 0 0 0 1=32-1=31 Replace string of 1s in multiplier with In a string when ever we have the least significant

More information

Combinational Logic. By : Ali Mustafa

Combinational Logic. By : Ali Mustafa Combinational Logic By : Ali Mustafa Contents Adder Subtractor Multiplier Comparator Decoder Encoder Multiplexer How to Analyze any combinational circuit like this? Analysis Procedure To obtain the output

More information

EE260: Digital Design, Spring n Digital Computers. n Number Systems. n Representations. n Conversions. n Arithmetic Operations.

EE260: Digital Design, Spring n Digital Computers. n Number Systems. n Representations. n Conversions. n Arithmetic Operations. EE 260: Introduction to Digital Design Number Systems Yao Zheng Department of Electrical Engineering University of Hawaiʻi at Mānoa Overview n Digital Computers n Number Systems n Representations n Conversions

More information

L1 2.1 Long Division of Polynomials and The Remainder Theorem Lesson MHF4U Jensen

L1 2.1 Long Division of Polynomials and The Remainder Theorem Lesson MHF4U Jensen L1 2.1 Long Division of Polynomials and The Remainder Theorem Lesson MHF4U Jensen In this section you will apply the method of long division to divide a polynomial by a binomial. You will also learn to

More information

Overview. Arithmetic circuits. Binary half adder. Binary full adder. Last lecture PLDs ROMs Tristates Design examples

Overview. Arithmetic circuits. Binary half adder. Binary full adder. Last lecture PLDs ROMs Tristates Design examples Overview rithmetic circuits Last lecture PLDs ROMs Tristates Design examples Today dders Ripple-carry Carry-lookahead Carry-select The conclusion of combinational logic!!! General-purpose building blocks

More information

Numbering Systems. Contents: Binary & Decimal. Converting From: B D, D B. Arithmetic operation on Binary.

Numbering Systems. Contents: Binary & Decimal. Converting From: B D, D B. Arithmetic operation on Binary. Numbering Systems Contents: Binary & Decimal. Converting From: B D, D B. Arithmetic operation on Binary. Addition & Subtraction using Octal & Hexadecimal 2 s Complement, Subtraction Using 2 s Complement.

More information

Sample Test Paper - I

Sample Test Paper - I Scheme G Sample Test Paper - I Course Name : Computer Engineering Group Marks : 25 Hours: 1 Hrs. Q.1) Attempt any THREE: 09 Marks a) Define i) Propagation delay ii) Fan-in iii) Fan-out b) Convert the following:

More information

The goal differs from prime factorization. Prime factorization would initialize all divisors to be prime numbers instead of integers*

The goal differs from prime factorization. Prime factorization would initialize all divisors to be prime numbers instead of integers* Quantum Algorithm Processor For Finding Exact Divisors Professor J R Burger Summary Wiring diagrams are given for a quantum algorithm processor in CMOS to compute, in parallel, all divisors of an n-bit

More information

3.3 Dividing Polynomials. Copyright Cengage Learning. All rights reserved.

3.3 Dividing Polynomials. Copyright Cengage Learning. All rights reserved. 3.3 Dividing Polynomials Copyright Cengage Learning. All rights reserved. Objectives Long Division of Polynomials Synthetic Division The Remainder and Factor Theorems 2 Dividing Polynomials In this section

More information

SRT Division and the Pentium FDIV Bug (draft lecture notes, CSCI P415)

SRT Division and the Pentium FDIV Bug (draft lecture notes, CSCI P415) SRT Division and the Pentium FDIV Bug (draft lecture notes, CSCI P4) Steven D. Johnson September 0, 000 Abstract This talk explains the widely publicized design error in a 994 issue of the Intel Corp.

More information

Chapter 2 Basic Arithmetic Circuits

Chapter 2 Basic Arithmetic Circuits Chapter 2 Basic Arithmetic Circuits This chapter is devoted to the description of simple circuits for the implementation of some of the arithmetic operations presented in Chap. 1. Specifically, the design

More information

Divider Implementation

Divider Implementation c n = cn-= LCTRICAL AD COTR GIRIG DPARTT, OAKLAD UIVRSITY RCRLA@OU ALGORITH Divider Implementation The division of two unsigned integer numbers A (where A is the dividend and the divisor), results in a

More information

L1 2.1 Long Division of Polynomials and The Remainder Theorem Lesson MHF4U Jensen

L1 2.1 Long Division of Polynomials and The Remainder Theorem Lesson MHF4U Jensen L1 2.1 Long Division of Polynomials and The Remainder Theorem Lesson MHF4U Jensen In this section you will apply the method of long division to divide a polynomial by a binomial. You will also learn to

More information

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Arithmetic Circuits January, 2003 1 A Generic Digital Processor MEM ORY INPUT-OUTPUT CONTROL DATAPATH

More information

Hakim Weatherspoon CS 3410 Computer Science Cornell University

Hakim Weatherspoon CS 3410 Computer Science Cornell University Hakim Weatherspoon CS 3410 Computer Science Cornell University The slides are the product of many rounds of teaching CS 3410 by Professors Weatherspoon, Bala, Bracy, and Sirer. memory inst 32 register

More information

Arithmetic in Integer Rings and Prime Fields

Arithmetic in Integer Rings and Prime Fields Arithmetic in Integer Rings and Prime Fields A 3 B 3 A 2 B 2 A 1 B 1 A 0 B 0 FA C 3 FA C 2 FA C 1 FA C 0 C 4 S 3 S 2 S 1 S 0 http://koclab.org Çetin Kaya Koç Spring 2018 1 / 71 Contents Arithmetic in Integer

More information

MATH Dr. Halimah Alshehri Dr. Halimah Alshehri

MATH Dr. Halimah Alshehri Dr. Halimah Alshehri MATH 1101 haalshehri@ksu.edu.sa 1 Introduction To Number Systems First Section: Binary System Second Section: Octal Number System Third Section: Hexadecimal System 2 Binary System 3 Binary System The binary

More information

Part II Addition / Subtraction

Part II Addition / Subtraction Part II Addition / Subtraction Parts Chapters I. Number Representation 1. 2. 3. 4. Numbers and Arithmetic Representing Signed Numbers Redundant Number Systems Residue Number Systems Elementary Operations

More information

A COMBINED 16-BIT BINARY AND DUAL GALOIS FIELD MULTIPLIER. Jesus Garcia and Michael J. Schulte

A COMBINED 16-BIT BINARY AND DUAL GALOIS FIELD MULTIPLIER. Jesus Garcia and Michael J. Schulte A COMBINED 16-BIT BINARY AND DUAL GALOIS FIELD MULTIPLIER Jesus Garcia and Michael J. Schulte Lehigh University Department of Computer Science and Engineering Bethlehem, PA 15 ABSTRACT Galois field arithmetic

More information

Number representation

Number representation Number representation A number can be represented in binary in many ways. The most common number types to be represented are: Integers, positive integers one-complement, two-complement, sign-magnitude

More information

Numbers & Arithmetic. Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University. See: P&H Chapter , 3.2, C.5 C.

Numbers & Arithmetic. Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University. See: P&H Chapter , 3.2, C.5 C. Numbers & Arithmetic Hakim Weatherspoon CS 3410, Spring 2012 Computer Science Cornell University See: P&H Chapter 2.4-2.6, 3.2, C.5 C.6 Example: Big Picture Computer System Organization and Programming

More information

Numbers and Arithmetic

Numbers and Arithmetic Numbers and Arithmetic See: P&H Chapter 2.4 2.6, 3.2, C.5 C.6 Hakim Weatherspoon CS 3410, Spring 2013 Computer Science Cornell University Big Picture: Building a Processor memory inst register file alu

More information

ECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks

ECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part A Combinational Logic Building Blocks ECE 545 Digital System Design with VHDL Lecture Digital Logic Refresher Part A Combinational Logic Building Blocks Lecture Roadmap Combinational Logic Basic Logic Review Basic Gates De Morgan s Law Combinational

More information

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

Digital Integrated Circuits A Design Perspective. Arithmetic Circuits. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Arithmetic Circuits January, 2003 1 A Generic Digital Processor MEMORY INPUT-OUTPUT CONTROL DATAPATH

More information

Computer Architecture 10. Fast Adders

Computer Architecture 10. Fast Adders Computer Architecture 10 Fast s Ma d e wi t h Op e n Of f i c e. o r g 1 Carry Problem Addition is primary mechanism in implementing arithmetic operations Slow addition directly affects the total performance

More information

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr. Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational

More information

Fundamentals of Digital Design

Fundamentals of Digital Design Fundamentals of Digital Design Digital Radiation Measurement and Spectroscopy NE/RHP 537 1 Binary Number System The binary numeral system, or base-2 number system, is a numeral system that represents numeric

More information

A High-Speed Realization of Chinese Remainder Theorem

A High-Speed Realization of Chinese Remainder Theorem Proceedings of the 2007 WSEAS Int. Conference on Circuits, Systems, Signal and Telecommunications, Gold Coast, Australia, January 17-19, 2007 97 A High-Speed Realization of Chinese Remainder Theorem Shuangching

More information

Solutions for Appendix C Exercises

Solutions for Appendix C Exercises C Solutions for Appix C Exercises 1 Solutions for Appix C Exercises C.1 A B A B A + B A B A B A + B 0 0 1 1 1 1 1 1 0 1 1 0 0 0 1 1 1 0 0 1 0 0 1 1 1 1 0 0 0 0 0 0 C.2 Here is the first equation: E = ((

More information

Combinational Logic. Mantıksal Tasarım BBM231. section instructor: Ufuk Çelikcan

Combinational Logic. Mantıksal Tasarım BBM231. section instructor: Ufuk Çelikcan Combinational Logic Mantıksal Tasarım BBM23 section instructor: Ufuk Çelikcan Classification. Combinational no memory outputs depends on only the present inputs expressed by Boolean functions 2. Sequential

More information

EDULABZ INTERNATIONAL NUMBER SYSTEM

EDULABZ INTERNATIONAL NUMBER SYSTEM NUMBER SYSTEM 1. Find the product of the place value of 8 and the face value of 7 in the number 7801. Ans. Place value of 8 in 7801 = 800, Face value of 7 in 7801 = 7 Required product = 800 7 = 00. How

More information

Answers (1) A) 36 = - - = Now, we can divide the numbers as shown below. For example : 4 = 2, 2 4 = -2, -2-4 = -2, 2-4 = 2.

Answers (1) A) 36 = - - = Now, we can divide the numbers as shown below. For example : 4 = 2, 2 4 = -2, -2-4 = -2, 2-4 = 2. Answers (1) A) 36 We can divide the two numbers by using the following steps : 1. Firstly, we will divide the mathematical signs of the numbers. We place a negative sign before the negative numbers and

More information

Notes on arithmetic. 1. Representation in base B

Notes on arithmetic. 1. Representation in base B Notes on arithmetic The Babylonians that is to say, the people that inhabited what is now southern Iraq for reasons not entirely clear to us, ued base 60 in scientific calculation. This offers us an excuse

More information

Numbering Systems. Computational Platforms. Scaling and Round-off Noise. Special Purpose. here that is dedicated architecture

Numbering Systems. Computational Platforms. Scaling and Round-off Noise. Special Purpose. here that is dedicated architecture Computational Platforms Numbering Systems Basic Building Blocks Scaling and Round-off Noise Computational Platforms Viktor Öwall viktor.owall@eit.lth.seowall@eit lth Standard Processors or Special Purpose

More information

Volume 3, No. 1, January 2012 Journal of Global Research in Computer Science RESEARCH PAPER Available Online at

Volume 3, No. 1, January 2012 Journal of Global Research in Computer Science RESEARCH PAPER Available Online at Volume 3, No 1, January 2012 Journal of Global Research in Computer Science RESEARCH PAPER Available Online at wwwjgrcsinfo A NOVEL HIGH DYNAMIC RANGE 5-MODULUS SET WHIT EFFICIENT REVERSE CONVERTER AND

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Multiplication CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev HW

More information

Linear Feedback Shift Registers (LFSRs) 4-bit LFSR

Linear Feedback Shift Registers (LFSRs) 4-bit LFSR Linear Feedback Shift Registers (LFSRs) These are n-bit counters exhibiting pseudo-random behavior. Built from simple shift-registers with a small number of xor gates. Used for: random number generation

More information

How fast can we add (or subtract) two numbers n and m?

How fast can we add (or subtract) two numbers n and m? Addition and Subtraction How fast do we add (or subtract) two numbers n and m? How fast can we add (or subtract) two numbers n and m? Definition. Let A(d) denote the maximal number of steps required to

More information

Part II Addition / Subtraction

Part II Addition / Subtraction Part II Addition / Subtraction Parts Chapters I. Number Representation 1. 2. 3. 4. Numbers and Arithmetic Representing Signed Numbers Redundant Number Systems Residue Number Systems Elementary Operations

More information

An Effective New CRT Based Reverse Converter for a Novel Moduli Set { 2 2n+1 1, 2 2n+1, 2 2n 1 }

An Effective New CRT Based Reverse Converter for a Novel Moduli Set { 2 2n+1 1, 2 2n+1, 2 2n 1 } An Effective New CRT Based Reverse Converter for a Novel Moduli Set +1 1, +1, 1 } Edem Kwedzo Bankas, Kazeem Alagbe Gbolagade Department of Computer Science, Faculty of Mathematical Sciences, University

More information

Number Representations

Number Representations Computer Arithmetic Algorithms Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University Number Representations Information Textbook Israel Koren, Computer Arithmetic

More information

14:332:231 DIGITAL LOGIC DESIGN. 2 s-complement Representation

14:332:231 DIGITAL LOGIC DESIGN. 2 s-complement Representation 4:332:23 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 203 Lecture #3: Addition, Subtraction, Multiplication, and Division 2 s-complement Representation RECALL

More information

Lecture 18: Datapath Functional Units

Lecture 18: Datapath Functional Units Lecture 8: Datapath Functional Unit Outline Comparator Shifter Multi-input Adder Multiplier 8: Datapath Functional Unit CMOS VLSI Deign 4th Ed. 2 Comparator 0 detector: A = 00 000 detector: A = Equality

More information

Processor Design & ALU Design

Processor Design & ALU Design 3/8/2 Processor Design A. Sahu CSE, IIT Guwahati Please be updated with http://jatinga.iitg.ernet.in/~asahu/c22/ Outline Components of CPU Register, Multiplexor, Decoder, / Adder, substractor, Varity of

More information

Complex Logarithmic Number System Arithmetic Using High-Radix Redundant CORDIC Algorithms

Complex Logarithmic Number System Arithmetic Using High-Radix Redundant CORDIC Algorithms Complex Logarithmic Number System Arithmetic Using High-Radix Redundant CORDIC Algorithms David Lewis Department of Electrical and Computer Engineering, University of Toronto Toronto, Ontario, Canada M5S

More information

Digital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits.

Digital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits. CS211 Computer Architecture Digital Logic l Topics l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Figures & Tables borrowed from:! http://www.allaboutcircuits.com/vol_4/index.html!

More information

Design of Sequential Circuits

Design of Sequential Circuits Design of Sequential Circuits Seven Steps: Construct a state diagram (showing contents of flip flop and inputs with next state) Assign letter variables to each flip flop and each input and output variable

More information

CHAPTER 2 NUMBER SYSTEMS

CHAPTER 2 NUMBER SYSTEMS CHAPTER 2 NUMBER SYSTEMS The Decimal Number System : We begin our study of the number systems with the familiar decimal number system. The decimal system contains ten unique symbol 0, 1, 2, 3, 4, 5, 6,

More information

Conversions between Decimal and Binary

Conversions between Decimal and Binary Conversions between Decimal and Binary Binary to Decimal Technique - use the definition of a number in a positional number system with base 2 - evaluate the definition formula ( the formula ) using decimal

More information

Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing

Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing IT 204 Section 3.0 Boolean Algebra and Digital Logic Boolean Algebra 2 Logic Equations to Truth Tables X = A. B + A. B + AB A B X 0 0 0 0 3 Sum of Products The OR operation performed on the products of

More information

Lecture 12: Datapath Functional Units

Lecture 12: Datapath Functional Units Lecture 2: Datapath Functional Unit Slide courtey of Deming Chen Slide baed on the initial et from David Harri CMOS VLSI Deign Outline Comparator Shifter Multi-input Adder Multiplier Reading:.3-4;.8-9

More information