DIVIDER IMPLEMENTATION

Transcription

1 c n = cn-= DAIL LLAOCCA CLab@OU DIVID IPLTATIO The division of two unsigned integer numbers A (where A is the dividend and the divisor), results in a quotient and a residue. These quantities are related by A = +. For the implementation, we follow the hand-division method. We grab bits of A one by one and comparing it with the divisor. If the result is greater or equal than, then we subtract from it. On each iteration, we get one bit of. Fig. shows the algorithm as well as an example: A = ; = A ALGOITH = for i = n- downto left shift (input = a i ) if q i =, - else q i = end end Figure. Division Algorithm For hardware implementation, we consider restoring dividers (i.e., those that keep the actual residue value at every step). I. SUTACTIO OF USIGD US PSTD WITH n-its: T = This point deserves special attention as the divider hardware relies on a result obtained here. We usually determine the sign of the subtraction by sign-extending and so that they are in 2 s complement representation with n + bits. Then, we do T = + not() +, where T = t n t n t n 2 t, and t n determines the sign of the subtraction operation. However, when and are unsigned, we can compute not() without sign-extending. We then analyze n : - If n = (and is equal to t n t n 2 t, i.e. it is an unsigned number with n bits) - If n = < (here is OT equal to t n t n 2 t ) I.. ote about the 2 s complement of zero: Let A be a number in 2 s complement with n bits: A = a n a n 2 a, where A = a n 2 n + n 2 i= a i 2 i is the signed decimal value of A. The 2 s complement of A is given by: P = not(a) +. P = p n p n 2 p If P and A are thought as n-bit unsigned numbers, ie.: A = n i= a i 2 i, P = n i= p i 2 i then: P = 2 n A. What if A =? Here P = 2 n requires n + bits. Why P is not zero. This is actually consistent with 2 s complement arithmetic, as in the operation A: A = + not(p) +, we let cin hold the value of, so that if A =, then not(a) = and cin =. This way not(a) + is properly c in = c represented. Fig. 2 shows this operation. ote that with cin =, all carries : q n- q n-2 q n-3 q + (from c to c ) are one. The result of the operation is then. There is no P: overflow as overflow = c n c n =. Thus, the case A = works very q n- q n-2 q n-3 q well for 2 s complement operations, if we include let cin carry the value of. Figure 2. -A when A= I.2. Demonstration of the computation of with n bits. = r n r n 2 r, = b n b n 2 b. With, unsigned, we have, 2 n To do, we sign-extend and to n + bits turning them into two numbers in 2 s complement representation. The sign-extension actually amounts to zero-extending. Then: = r n r n 2 r, = b n b n 2 b. r n = b n =. In 2 s complement, we have that:, 2 n. It follows that: (2 n ) 2 n. Thus can be represented in 2 s complement with n + bits (as expected). Let K = not() +, K = k n k n k n 2 k. In unsigned representation, K = 2 n+.

2 DAIL LLAOCCA Fig. 3 shows the operation by using: + K, where K = not() +. ecall that we let be held by cin. ote that if = K = 2 n+ (here K is represented by the second operator as well as cin = ) : : r n- r n-2 r - b n- b n-2 b : K: c in r n- r n-2 r + k n- k n-2 k Figure 3. Operation + K = + not() +! ow, we determine the value of k n : Case : 2 n 2 n+ (2 n ) K 2 n+ 2 n + K 2 n+. Thus, k n = Case = : K = 2 n+. K requires + 2 bits, with k n+ =, and k n = : K k n k n k n 2 k k n 2 n 2 n + (or > ) k n = 2 n+ = 2 n+ k n = ow, we consider,, and K to represent unsigned integers. n + K = r i 2 i + k i 2 i = r i 2 i + k n 2 n + k i 2 i i= n i= n n i= + K = + 2 n+ = r i 2 i + 2 n+ b i 2 i i= n i= < : Since > k n = + 2 n+ = n i= r i 2 i + 2 n+ n i= b i 2 i < 2 n+ + K = n i= r i 2 i + k n 2 n + n i= k i 2 i < 2 n+ n i= r i 2 i + n i= k i 2 i < 2 n o The (n + )-bit sum (considering the operation as unsigned) of and K is lower than 2 n+. Then, there is no overflow in the (n + )- bit unsigned sum. Thus c n+ =. o The n-bit sum (considering the operations as unsigned) of and k n k n 2 k is lower than 2 n. Thus, there is no overflow of the n-bit unsigned sum. Thus c n =. : + 2 n+ = n i= r i 2 i + 2 n+ n i= b i 2 i 2 n+ + K = n i= r i 2 i + k n 2 n + n i= k i 2 i 2 n+ n i= r i 2 i + n i= k i 2 i 2 n+ k n 2 n o The (n + )-bit sum (considering the operation as unsigned) of and K is greater or equal than 2 n+. Then, there is overflow of the (n + )-bit unsigned sum. Thus c n+ =. o For the n-bit sum of and k n k n 2 k, we have two cases: > k n =. Then n i= r i 2 i + n i= k i 2 i 2 n+ 2 n n i= r i 2 i + n i= k i 2 i 2 n = k n =. Then n i= r i 2 i + n i= k i 2 i 2 n+ In both cases, the n-bit sum (considering the operands as unsigned) of and k n k n 2 k is greater of equal than 2 n. So, there is overflow of the n-bit unsigned sum. Thus c n = when. 2 s complement operation - with n + bits: There is no overflow of the subtraction as c n = c n. For : The result T = is a positive number, thus T n =. Therefore t n t n 2 t contains in unsigned representation. In conclusion: If < c n =. The n bits T n T n 2 T DO OT contain the result. If c n =. The n bits T n T n 2 T DO represent in unsigned representation. n i= 2

3 DAIL LLAOCCA II. STOIG AAY DIVID FO USIGD US A, : positive integers in unsigned representation. A = a a 2 a with bits, and = b b 2 b with bits, with the condition that. = quotient, = residue. A = +. bits In this parallel implementation, the result of every stage is Y called the residue i. Stage Fig. 4 depicts the parallel algorithm with stages. For each stage i, i =,,, we have: Y i : output of stage i. esidue after every stage. Y i : input of stage i. It holds the minuend. Stage For the next stage, we append the next bit of A to i. This becomes Y i+ (the minuend): Y i+ = i &a i, i =,, Stage 2 Y 2 At each stage i, the subtraction Y i is performed. If Y i then i = Y i. If Y i <, then i = Y i. Stage Y i Computation of i Y = a Y = &a 2 2 Y 2 = &a 3 = Y, if Y = Y, if Y < = Y, if Y = Y, if Y < 2 = Y 2, if Y 2 2 = Y 2, if Y 2 < # of i bits - Y = 2 &a = Y, if Y = Y, if Y < 2 3 Stage 3 Stage - Stage 2 Y 3-2 Y - - Y Since has bits, the operation Y i requires bits for both operands. To maintain consistency, we let Y i be represented with bits. Stage + Y + + Y +2 i : output of each stage. For the first stages, i requires i + bits. However, for consistency and clarity s sake, since i might be the result of a subtraction, we let i use bits. Stage + -2 Y - For stages to 2: i is always transferred onto the next stage. ote that we transfer i with least significant bits. There is no loss of accuracy here since i at most requires - bits for stage -2. We need i with - bits since Y i+ uses bits. Stage + + bits Stages to : Figure 4. Parallel implementation algorithm Starting from stage, i requires bits. We also know that the residue requires at most bits (maximum value is 2 2). So, starting from stage - we need to transfer bits. As Y i+ now requires + bits, we need + units starting from stage. To implement the operation Y i we use a subtractor. When Y i i =, and when Y i < i =. This i becomes a bit of the quotient: i = i. This quotient requires bits at most. Also, the final residue is the result of the last stage. The maximum theoretical value of the residue is 2 2, thus the residue requires bits. =. Also, note that we should avoid a division by. If =, then, in our circuit: = 2 and = a a 2 a. - 3

4 DAIL LLAOCCA II.. Combinatorial Array Divider Fig. 5 shows the hardware of this array divider for =8, =4. ote that the first =4 stages only require 4 units, while the next stages require 5 units. This is fully combinatorial implementation. ach level computes i. It first computes Y i. When Y i i =, and when Y i < i =. This i is used to determine whether the next i is Y i or Y i. ach Processing Unit () is used to process Y i one bit at a time, and to let a particular bit of either Y i or Y i be transferred on to the next stage. b 3 b 2 b b x 3 x 2 x x q 7 c 4 c 3 c 2 c c y 3 y 2 y y a 6 x 3 x 2 x x q 6 A q 5 c 4 c 3 c 2 a 7 c c y 3 y 2 y y a 5 x 23 x 22 x 2 x 2 FA cin c 24 c 23 c 22 c 2 c 2 y 23 y 22 y 2 y 2 a 4 s x 33 x 32 x 3 x 3 q 4 c 34 c 33 c 32 c 3 c 3 y 33 y 32 y 3 y 3 a 3 r x 44 x 43 x 42 x 4 x 4 q 3 c 45 c 44 c 43 c 42 c 4 c 4 y 44 y 43 y 42 y 4 y 4 a 2 x 54 x 53 x 52 x 5 x 5 q 2 c 55 c 54 c 53 c 52 c 5 5 c y 54 y 53 y 52 y 5 y 5 a x 64 x 63 x 62 x 6 x 6 q c 65 c 64 c 63 c 62 c 6 c 6 y a 64 y 63 y 62 y 6 y 6 x 74 x 73 x 72 x 7 x 7 AAY c 75 c 74 c 73 c 72 c DIVID 7 q b a y 74 y 73 y 72 y 7 y 7 c 7 Figure 5. Fully Combinatorial Array Divider architecture for =8, =4 r 3 r 2 r r II.2. Fully Pipelined Array Divider Fig. 6 shows the hardware core of the fully pipelined array divider with its inputs, outputs, and parameters. I/O delay: cycles A resetn clock AAY DIVID Figure 6. Fully pipelined IP core for the array divider v 4

5 DAIL LLAOCCA Fig. 7 shows the internal architecture of this pipelined array divider for =8, =4. ote that the first =4 stages only require 4 units, while the next stages require 5 units. ote that the enable input is only an input to the shift register on the left, which is used to generate the valid output v. This way, valid outputs are readily signaled. If =, the output result is computed in cycles (and v= after cycles). b 3 b 2 b b a 7 a 6 a 5 a 4 a 3 a 2 a a x 3 x 2 x x c c 4 c 3 c 2 c y 3 y 2 y y x 3 x 2 x x c 4 c 3 c 2 c c y 3 y 2 y y x 23 x 22 x 2 x 2 c 24 c 23 c 22 c 2 c 2 y 23 y 22 y 2 y 2 x 33 x 32 x 3 x 3 c 34 c 33 c 32 c 3 c 3 y 33 y 32 y 3 y 3 x 44 x 43 x 42 x 4 x 4 c 45 c 44 c 43 c 42 c 4 c 4 y 44 y 43 y 42 y 4 y 4 x 54 x 53 x 52 x 5 x 5 c 55 c 54 c 53 c 52 c 5 c 5 y 54 y 53 y 52 y 5 y 5 x 64 x 63 x 62 x 6 x 6 c 65 c 64 c 63 c 62 c 6 c 6 y 64 y 63 y 62 y 6 y 6 x 74 x 73 x 72 x 7 x 7 c 75 c 74 c 73 c 72 c 7 c 7 y 74 y 73 y 72 y 7 y 7 v q 7 q 6 q 5 q 4 q 3 q 2 q q r 3 r 2 r r Figure 7. Fully Pipelined Array Divider architecture for =8, =4 5

6 LA A DAIL LLAOCCA CLab@OU III. ITATIV STOIG DIVID Fig. 8 shows the iterative hardware architecture as well as the state machine. Here, i is always held at register. The subtractor computes Y i. This requires + bits in the worst case. If Y i then i = Y i. Yi here is the minuend. Y i is loaded onto register. ote that only bits are needed. If Y i <, then i = Y i. Here only Y i is loaded onto register. This is done by just shifting a into register ote that requires bits since it holds the residue at every stage. Also, since we always shift i onto register A, the quotient is held at A in the last iteration. DA D resetn= S FS sclr L L LFT SHIFT w GIST GIST A - -2 a - sclr L Y LFT SHIFT GIST & w a - S2 sclr, C LA, A, A L no C=- C C+ a S3 yes done done Figure 8. Iterative Divider 6