Introduction to the Xilinx Spartan-3E

Transcription

1 Introduction to the Xilinx Spartan-3E Nash Kaminski Instructor: Dr. Jafar Saniie ECE597 Illinois Institute of Technology Acknowledgment: I acknowledge that all of the work (including figures and code) belongs to myself or is properly attributed. Signature

2 Introduction Purpose The purpose of this laboratory activity was to further familiarize me with the VHDL to FPGA design flow as well as further reinforce my knowledge and understanding of VHDL and FPGA based hardware design. For this laboratory activity, a series of the ECE 446 labs, namely labs 1 (code conversion), lab 2 (four bit ripple carry adder and subtractor), lab 4 (error correcting codes) and lab 5 (8 bit barrel shifter) were completed. These 4 activities were selected since they require VHDL development of progressively increasing complexity but could all be implemented within a reasonable timeframe and tested both in simulation and on physical hardware. Background Effective design of FPGA based digital systems requires both a strong theoretical background in the area of both FPGA design as well as digital system design in general, combined with physical experience designing, implementing, and testing such systems. FPGA s allow for hardware level implementation of digital systems modeled at a variety of levels of abstraction such as the behavioral, RTL, or gate level in a specialized programming language referred to as a hardware description language. Once an HDL model of an intended system has been designed, a series of software tools can be used to simulate the behavior of the design as well as synthesize and implement the design, producing a so called bit file which can be used to configure the internal hardware of an FPGA to perform such functionality described in the HDL model. While most practical applications of hardware/software codesign are significantly more involved than the systems implemented during these laboratory activities, the same concepts apply in both cases. Furthermore, functions such as BCD code conversion, addition/subtraction, error correction and arithmetic shifting are commonly used as building blocks in many complex digital systems. Code conversion between numbers represented in BCD and those represented in excess-3 BCD is a common function since numbers represented in standard BCD cannot be added and subtracted using normal arithmetic operations, while those represented in excess-3 BCD can. While standard addition as well as 2 s complement subtraction are also very common operations, faster performing adders and subtracters, such as the carry skip and carry lookahead adder/subtracters are often used in practice. Arithmetic shift is yet another very common primitive operation used in a countless number of applications. With respect to the implementation of such functionality, there are multiple means by which logical and/or arithmetic shift can be implemented in hardware. Sequential shifters, where the data is latched in a series of flip flops and shifted one bit per clock cycle, can be implemented using a relatively small amount of hardware but are rather limited in terms of performance. Owing to the performance and flexibility drawbacks of sequential shifters, combinational shifters, such as the barrel shifter implemented in this laboratory activity, can be implemented however such combinational shifters require significantly more hardware to implement. Finally, it is often critical when digital data is transmitted, especially over long distances, to be able to detect and ideally correct errors in such data transmission. While there are a variety of means of error detection and correction each with varying levels of performance, overhead and error detection/correction capabilities, the Hamming error correction code is one of the most common schemes, allowing for single bit error correction and multi bit error detection. This is partially because in practice, a large number of transient error conditions introduce either single bit errors or large burst errors. Therefore, being able to detect and correct single bit errors quickly and without the retransmission of data is ideal since this will likely have the greatest impact on improving transmission efficiency without sacrificing reliability. Equipment Xilinx ISE 14.7 CentOS 6 Linux Virtual Machine Digilent Spartan-3E Starter Development Board. 1

3 Procedure During this laboratory activity, the following procedure was performed: 1. Setup CentOS 6 Linux inside VM and install Xilinx ISE Design Suite. 2. Test and troubleshoot connectivity to FPGA board. 3. Derive output equations for BCD-excess3 code converter from truth tables using K-maps. 4. Create new Xilinx ISE project for code converter. 5. Implement output equations in VHDL. 6. Implement test bench in VHDL to verify functionality of BCD to excess3 conversion functionality. 7. Simulate functionality using Xilinx ISim and debug as needed until output is correct. 8. Synthesize design for Xilinx XC3S500E FPGA. 9. Define user constraint file, assigning inputs to switches and outputs to the onboard LEDs. 10. Implement design in Xilinx ISE and generate the bit file. 11. Download bitfile to Digilent Starter Board using Xilinx impact utility. 12. Verify functionality of design. 13. Reset Digilent Starter Board. 14. Derive output equations for excess3-bcd code converter from truth tables using K-maps. 15. Implement output equations and conversion selection functionality in VHDL. 16. Implement test bench in VHDL. 17. Simulate and debug as needed using previous procedure. 18. Synthesize, define pin mappings and implement using previous procedure. 19. Download bitfile to board and verify functionality. 20. Reset Digilent Starter Board. 21. Create new Xilinx ISE project for 4 bit adder. 22. Design and implement single bit adder in structural VHDL. 23. Design and implement 4 bit ripple carry adder by chaining 4 single bit adders. 24. Design and implement test bench for 4 bit adder. 25. Simulate and debug as needed using previous procedure. 26. Synthesize, define pin mappings and implement using previous procedure. 27. Download bitfile to board and verify functionality. 28. Reset Digilent Starter Board. 29. Create new Xilinx ISE project for 4 bit Hamming error corrector. 30. Design and implement 4 bit Hamming parity generator in structural VHDL. 2

4 31. Design and implement VHDL test bench for parity generator. 32. Simulate in ISim and debug as needed until output matches manually computed result. 33. Synthesize, define pin mappings and implement using previous procedure. 34. Download bitfile to board and verify functionality. 35. Reset Digilent Starter Board. 36. Design and implement 4 bit Hamming check bit generator in structural VHDL. 37. Design and implement VHDL test bench for parity generator. 38. Simulate in ISim and debug as needed until output matches manually computed result. 39. Synthesize, define pin mappings and implement using previous procedure. 40. Download bitfile to board and verify functionality. 41. Reset Digilent Starter Board. 42. Design and implement 7 bit error corrector in behavioral VHDL. 43. Design and implement VHDL test bench for error corrector. 44. Simulate in ISim and debug as needed until output matches manually computed result. 45. Synthesize, define pin mappings and implement using previous procedure. 46. Download bitfile to board and verify functionality. 47. Reset Digilent Starter Board. 48. Create top level module containing parity generator, check generator, and error corrector. 49. Create error introduction module that inserts errors by XORing bits in the codeword with a user provided input. 50. Insert error introduction module between the parity and check generator blocks. 51. Synthesize, define pin mappings and implement using previous procedure. 52. Download bitfile to board and verify functionality. 53. Reset Digilent Starter Board. 54. Create new Xilinx ISE project for 8 bit Hamming error corrector. 55. Design and implement 8 bit Hamming parity generator in structural VHDL. 56. Design and implement new VHDL test bench for 8 bit parity generator. 57. Simulate in ISim and debug as needed until output matches manually computed result. 58. Design and implement 8 bit Hamming check bit generator in structural VHDL. 59. Design and implement new VHDL test bench for parity generator. 60. Simulate in ISim and debug as needed until output matches manually computed result. 61. Design and implement 12 bit error corrector in behavioral VHDL. 62. Design and implement new VHDL test bench for error corrector. 3

5 63. Simulate in ISim and debug as needed until output matches manually computed result. 64. Create new top level module with 8 bit I/O ports containing parity generator, check generator, and error corrector. 65. Create 12 bit error introduction module that inserts errors by XORing bits in the codeword with a user provided input. 66. Insert error introduction module between the parity and check generator blocks. 67. Simulate in ISim and verify against manually computed result. 68. Create new Xilinx ISE project for barrel shifter. 69. Implement 2 input multiplexer module in structural VHDL. 70. Implement 8 bit barrel shifter as per laboratory manual, using VHDL for loops to expedite implementation. 71. Design and implement test bench to fully test barrel shifter including all possible shift amounts and directions. 72. Simulate in ISim and debug as needed. 73. Synthesize, define pin mappings and implement using previous procedure. 74. Download bitfile to board and verify functionality. 75. Reset Digilent Starter Board. 4

6 Results Code Converter 200 ns 250 ns 300 ns 350 ns Figure 1: 4-bit BCD to excess-3 code converter simulation. 5

7 200 ns 250 ns 300 ns 350 ns 400 ns 450 ns 500 ns 550 ns Figure 2: 4-bit universal code converter simulation. 6

8 4 bit adder and subtracter 200 ns 205 ns 210 ns 215 ns 220 ns 225 ns Figure 3: 4 bit adder simulation 7

9 Hamming Code Error Detector and Corrector 200 ns 210 ns 220 ns 230 ns 240 ns Figure 4: 4 bit Hamming parity bit generator simulation. 8

10 90 ns 100 ns 110 ns 120 ns 130 ns Figure 5: 4 bit Hamming check bit generator simulation. 9

11 200 ns 205 ns 210 ns 215 ns 220 ns 225 ns 230 ns 235 ns Figure 6: 7-bit error corrector simulation. 10

12 200 ns 210 ns 220 ns 230 ns 240 ns Figure 7: Full 8-bit Hamming error detector and corrector simulation. 11

13 Barrel Shifter 200 ns 220 ns 240 ns 260 ns 280 ns 300 ns 320 ns ip[7:0] amt[2:0] dir op[7:0] Analysis and Discussion Figure 8: 8-bit barrel shifter simulation. Owing to both my prior experience with Verilog in ECE429 as well as my exposure to VHDL in ECE729, little difficulty was faced with the implementation of the VHDL modules required for these laboratory activities. All functions including the BCD-excess3 code converters, 4-bit adder and subtracter, 4 and 8 bit Hamming code error correctors and barrel shifter were implemented and successfully tested both in simulation as well as physically on the Digilent Spartan-3E FPGA development board, provided that a sufficient number of switches and LEDs were available to map the inputs and outputs to. While some of the functions such as the universal code converter and Hamming code error corrector implemented during this laboratory activity are materially complete, with little opportunity for expansion beyond increasing or decreasing the sized of the operands, other functions have a significant amount of opportunity for expansion. For example, the performance of the adder/subtracter could be improved dramatically by the implementation of faster carry logic in order to reduce the critical path delay. Additionally, the barrel shifter could also be fairly easily modified to also implement circular shift/rotate by adding a feedback path from the MSB to the new LSB in the case of left shift or the LSB to the new MSB in case of right shift along with associated control logic. Such module would then be capable of performing both standard shifts as well as circular shift/rotation. Finally, while all of these circuits could have been implemented using exclusively discrete TTL components, the number of such components required as well as the time and effort required for 12

14 assembly would have been immense compared to the time and effort required to implement such functionality within an FPGA. This is especially true for mux-heavy designs such as the barrel shifter, which would require upwards of 100 discrete gates to implement. Additionally, owing to the newer process technology, shorter and therefore faster interconnects as well as lower operating voltage, the FPGA implementation of these functions would completely outperform the discrete implementations in nearly all areas including power consumption, path delay, and reliability. However, I did face a significant amount of difficulty early on with communication to the Digilent Spartan- 3E starter board form Xilinx impact. After a fair bit of debugging, I was able to track down the issue to a capitalization error in the Linux udev rules file supplied with Xilinx ISE Xilinx impact relies on Linux s udev as well as the free software program fxload to load the firmware into the USB-to-JTAG chipset on the Digilent Spartan-3E starter board. While udev has always specified in its documentation that variables to be substituted be provided in lowercase, Xilinx has used uppercase environment variables to specify the Linux device node that the firmware file is to be sent to in its udev rules file. While in very early versions of udev, environment variables were substituted case insensitively, newer versions of udev, such as those supplied with the Xilinx supported CentOS 6 and Red Hat Enterprise Linux 6 Linux distributions, use case sensitive substitution for variable substitution. As a result, the firmware fails to be loaded into the USB-to-JTAG chipset on the development board and Xilinx impact fails with the generic error of No cables detected. To remedy the error, the Xilinx udev rules file in /etc/udev/rules.d was edited, replacing all occurrences of $TEMPNODE with $tempnode and the system rebooted. Conclusion After overcoming a few initial issues with the setup of Xilinx ISE and communication with the Digilent Spartan-3E starter board, I was able to successfully complete activities 1, 2, 4 and 5 from the ECE446 laboratory manual with little difficulty, easily implementing all required VHDL functionality required to meet the provided specifications. During the course of these activities and with my past experience being nearly entirely with Verilog, I feel that my VHDL development skills have improved significantly, along with my overall knowledge of FPGA based digital system design. However, moving forwards I would prefer to work with designs that pose more formidable engineering challenges to implement. Code Listings Simple Code Converter 1 Company : 3 Engineer : 5 Create Date : 1 6 : 1 9 : /29/2016 Design Name : 7 Module Name : /media/ s f n a s h k a m i n s k i / Desktop / c o u r s e s / ece742 / i s e p r o j e c t s / c o d e c o n v e r t e r s i m p l e / c o d e c o n v e r t e r s i m p l e t e s t. vhd P r o j e c t Name : 9 Target Device : Tool v e r s i o n s : 11 D e s c r i p t i o n : c o d e c o n v e r t e r s i m p l e 13 VHDL Test Bench Created by ISE f o r module : c o d e c o n v e r t e r s i m p l e 15 Dependencies : 17 Revision : Revision F i l e Created 19 A d d i t i o n a l Comments : 21 Notes : This t e s t b e n c h has been a u t o m a t i c a l l y generated using types s t d l o g i c and 23 s t d l o g i c v e c t o r f o r the p o r t s o f the u n i t under t e s t. X i l i n x recommends 13

15 that t h e s e types always be used f o r the top l e v e l I /O o f a d e s i g n i n order 25 to guarantee that the t e s t b e n c h w i l l bind c o r r e c t l y to the post implementation s i m u l a t i o n model. 27 LIBRARY i e e e ; 29 USE i e e e. s t d l o g i c ALL; 31 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f using a r i t h m e t i c f u n c t i o n s with Signed or Unsigned v a l u e s 33 USE i e e e. numeric std.all; 35 ENTITY c o d e c o n v e r t e r s i m p l e t e s t IS END c o d e c o n v e r t e r s i m p l e t e s t ; ARCHITECTURE behavior OF c o d e c o n v e r t e r s i m p l e t e s t Component D e c l a r a t i o n f o r the Unit Under Test (UUT) COMPONENT c o d e c o n v e r t e r s i m p l e 43 PORT( A : IN s t d l o g i c v e c t o r (3 downto 0) ; 45 CLK : IN s t d l o g i c ; Y : OUT s t d l o g i c v e c t o r (3 downto 0) 47 ) ; END COMPONENT; Inputs s i g n a l A : s t d l o g i c v e c t o r (3 downto 0) := ( o t h e r s => 0 ) ; 53 Outputs 55 s i g n a l Y : s t d l o g i c v e c t o r (3 downto 0) ; 57 s i g n a l CLK : s t d l o g i c ; IS BEGIN constant CLK period : time := 10 ns ; I n s t a n t i a t e the Unit Under Test (UUT) 65 uut : c o d e c o n v e r t e r s i m p l e PORT MAP ( A => A, 67 CLK => CLK, Y => Y 69 ) ; 71 Clock p r o c e s s d e f i n i t i o n s CLK process : p r o c e s s 73 begin CLK <= 0 ; 75 wait f o r CLK period / 2 ; CLK <= 1 ; 77 wait f o r CLK period / 2 ; end p r o c e s s ; Stimulus p r o c e s s s t i m p r o c : p r o c e s s 83 begin hold r e s e t s t a t e f o r 100 ns. 85 wait f o r 100 ns ; 87 wait f o r CLK period 1 0 ; A <= 0000 ; 14

16 89 wait f o r 20 ns ; A <= 0001 ; 91 wait f o r 20 ns ; A <= 0010 ; 93 wait f o r 20 ns ; A <= 0011 ; 95 wait f o r 20 ns ; A <= 0100 ; 97 wait f o r 20 ns ; A <= 0101 ; 99 wait f o r 20 ns ; A <= 0110 ; 101 wait f o r 20 ns ; A <= 0111 ; 103 wait f o r 20 ns ; A <= 1000 ; 105 wait f o r 20 ns ; A <= 1001 ; 107 wait ; 109 end p r o c e s s ; 111 END; iseprojects/codeconvertersimple/codeconvertersimpletest.vhd 1 Company : 3 Engineer : 5 Create Date : 1 7 : 3 3 : /24/2016 Design Name : 7 Module Name : c o d e c o n v e r t e r s i m p l e S t r u c t u r a l P r o j e c t Name : 9 Target Devices : Tool v e r s i o n s : 11 D e s c r i p t i o n : 13 Dependencies : 15 Revision : Revision F i l e Created 17 A d d i t i o n a l Comments : 19 l i b r a r y IEEE ; 21 use IEEE. STD LOGIC 1164.ALL; 23 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f using a r i t h m e t i c f u n c t i o n s with Signed or Unsigned v a l u e s 25 use IEEE. NUMERIC STD. ALL; 27 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f i n s t a n t i a t i n g any X i l i n x p r i m i t i v e s i n t h i s code. 29 l i b r a r y UNISIM ; use UNISIM. VComponents. a l l ; 31 e n t i t y c o d e c o n v e r t e r s i m p l e i s 33 Port ( A : i n STD LOGIC VECTOR ( 3 downto 0) ; CLK : i n STD LOGIC ; 35 Y : out STD LOGIC VECTOR ( 3 downto 0) ) ; end c o d e c o n v e r t e r s i m p l e ; a r c h i t e c t u r e S t r u c t u r a l o f c o d e c o n v e r t e r s i m p l e i s 15

17 begin 41 Y( 0 ) <= NOT A( 0 ) ; Y( 1 ) <= ( (NOT A( 0 ) AND NOT A( 1 ) ) OR (A( 1 ) AND A( 0 ) ) ) ; 43 Y( 2 ) <= (NOT A( 3 ) AND NOT A( 2 ) AND A( 0 ) ) OR (NOT A( 3 ) AND NOT A( 2 ) AND A( 1 ) ) OR (A( 2 ) AND NOT A ( 1 ) AND NOT A( 0 ) ) OR (A( 3 ) AND A( 0 ) ) ; Y( 3 ) <= A( 3 ) OR (A( 2 ) AND A( 0 ) ) OR (A( 2 ) AND A( 1 ) ) ; 45 end S t r u c t u r a l ; iseprojects/codeconvertersimple/codeconvertersimple.vhd Universal Code Converter 1 Company : 3 Engineer : 5 Create Date : 1 8 : 2 1 : /29/2016 Design Name : 7 Module Name : /media/ s f n a s h k a m i n s k i / Desktop / c o u r s e s / ece742 / i s e p r o j e c t s / c o d e c o n v e r t e r u n i v e r s a l / c c u n i t e s t. vhd P r o j e c t Name : 9 Target Device : Tool v e r s i o n s : 11 D e s c r i p t i o n : c o d e c o n v e r t e r u n i v e r s a l 13 VHDL Test Bench Created by ISE f o r module : c o d e c o n v e r t e r u n i v e r s a l 15 Dependencies : 17 Revision : Revision F i l e Created 19 A d d i t i o n a l Comments : 21 Notes : This t e s t b e n c h has been a u t o m a t i c a l l y generated using types s t d l o g i c and 23 s t d l o g i c v e c t o r f o r the p o r t s o f the u n i t under t e s t. X i l i n x recommends that t h e s e types always be used f o r the top l e v e l I /O o f a d e s i g n i n order 25 to guarantee that the t e s t b e n c h w i l l bind c o r r e c t l y to the post implementation s i m u l a t i o n model. 27 LIBRARY i e e e ; 29 USE i e e e. s t d l o g i c ALL; 31 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f using a r i t h m e t i c f u n c t i o n s with Signed or Unsigned v a l u e s 33 USE i e e e. numeric std.all; 35 ENTITY c c u n i t e s t IS END c c u n i t e s t ; ARCHITECTURE behavior OF c c u n i t e s t Component D e c l a r a t i o n f o r the Unit Under Test (UUT) COMPONENT c o d e c o n v e r t e r u n i v e r s a l 43 PORT( A : IN s t d l o g i c v e c t o r (3 downto 0) ; 45 SEL : IN s t d l o g i c ; CLK : IN s t d l o g i c ; 47 Y : OUT s t d l o g i c v e c t o r (3 downto 0) ) ; 49 END COMPONENT; IS 16

18 51 Inputs 53 s i g n a l A : s t d l o g i c v e c t o r (3 downto 0) := ( o t h e r s => 0 ) ; s i g n a l SEL : s t d l o g i c := 0 ; 55 s i g n a l CLK : s t d l o g i c := 0 ; 57 Outputs s i g n a l Y : s t d l o g i c v e c t o r (3 downto 0) ; 59 Clock p e r i o d d e f i n i t i o n s 61 constant CLK period : time := 10 ns ; 63 BEGIN 65 I n s t a n t i a t e the Unit Under Test (UUT) uut : c o d e c o n v e r t e r u n i v e r s a l PORT MAP ( 67 A => A, SEL => SEL, 69 CLK => CLK, Y => Y 71 ) ; 73 Clock p r o c e s s d e f i n i t i o n s CLK process : p r o c e s s 75 begin CLK <= 0 ; 77 wait f o r CLK period / 2 ; CLK <= 1 ; 79 wait f o r CLK period / 2 ; end p r o c e s s ; Stimulus p r o c e s s s t i m p r o c : p r o c e s s 85 begin hold r e s e t s t a t e f o r 100 ns. 87 wait f o r 100 ns ; 89 wait f o r CLK period 1 0 ; 91 i n s e r t s t i m u l u s here SEL <= 0 ; 93 A <= 0000 ; wait f o r 20 ns ; 95 A <= 0001 ; wait f o r 20 ns ; 97 A <= 0010 ; wait f o r 20 ns ; 99 A <= 0011 ; wait f o r 20 ns ; 101 A <= 0100 ; wait f o r 20 ns ; 103 A <= 0101 ; wait f o r 20 ns ; 105 A <= 0110 ; wait f o r 20 ns ; 107 A <= 0111 ; wait f o r 20 ns ; 109 A <= 1000 ; wait f o r 20 ns ; 111 A <= 1001 ; wait f o r 20 ns ; 113 SEL <= 1 ; A <= 0011 ; 115 wait f o r 20 ns ; 17

19 A <= 0100 ; 117 wait f o r 20 ns ; A <= 0101 ; 119 wait f o r 20 ns ; A <= 0110 ; 121 wait f o r 20 ns ; A <= 0111 ; 123 wait f o r 20 ns ; A <= 1000 ; 125 wait f o r 20 ns ; A <= 1001 ; 127 wait f o r 20 ns ; A <= 1010 ; 129 wait f o r 20 ns ; A <= 1011 ; 131 wait f o r 20 ns ; A <= 1100 ; 133 wait ; end p r o c e s s ; 135 END; iseprojects/codeconverteruniversal/ccuni test.vhd l i b r a r y IEEE ; 2 use IEEE. STD LOGIC 1164.ALL; 4 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f using a r i t h m e t i c f u n c t i o n s with Signed or Unsigned v a l u e s 6 use IEEE. NUMERIC STD. ALL; 8 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f i n s t a n t i a t i n g any X i l i n x p r i m i t i v e s i n t h i s code. 10 l i b r a r y UNISIM ; use UNISIM. VComponents. a l l ; 12 e n t i t y c o d e c o n v e r t e r u n i v e r s a l i s 14 Port ( A : i n STD LOGIC VECTOR ( 3 downto 0) ; SEL : i n STD LOGIC ; 16 CLK : i n STD LOGIC ; Y : out STD LOGIC VECTOR ( 3 downto 0) ) ; 18 end c o d e c o n v e r t e r u n i v e r s a l ; 20 a r c h i t e c t u r e S t r u c t u r a l o f c o d e c o n v e r t e r u n i v e r s a l i s 22 begin 24 p r o c e s s (A, SEL) begin 26 i f (SEL = 0 ) then Y( 0 ) <= NOT A( 0 ) ; 28 Y( 1 ) <= ( (NOT A( 0 ) AND NOT A( 1 ) ) OR (A( 1 ) AND A( 0 ) ) ) ; Y( 2 ) <= (NOT A( 3 ) AND NOT A( 2 ) AND A( 0 ) ) OR (NOT A( 3 ) AND NOT A( 2 ) AND A( 1 ) ) OR (A( 2 ) AND NOT A ( 1 ) AND NOT A( 0 ) ) OR (A( 3 ) AND A( 0 ) ) ; 30 Y( 3 ) <= A( 3 ) OR (A( 2 ) AND A( 0 ) ) OR (A( 2 ) AND A( 1 ) ) ; ELSIF (SEL = 1 ) then 32 Y( 0 ) <= NOT A( 0 ) ; Y( 1 ) <= (NOT A( 1 ) AND A( 0 ) ) OR (A( 1 ) AND NOT A( 0 ) ) ; 34 Y( 2 ) <= (A( 3 ) AND NOT A( 2 ) AND NOT A( 1 ) ) OR (A( 2 ) AND A( 1 ) AND A( 0 ) ) OR (A( 3 ) AND A( 1 ) AND NOT A ( 0 ) ) ; Y( 3 ) <= (A( 3 ) AND A( 2 ) ) OR (A( 3 ) AND A( 1 ) AND A( 0 ) ) ; 36 end i f ; end p r o c e s s ; 38 end S t r u c t u r a l ; 18

20 iseprojects/codeconverteruniversal/codeconverteruniversal.vhd 4-bit Ripple Carry Adder 1 Company : 3 Engineer : 5 Create Date : 1 6 : 1 0 : /05/2016 Design Name : 7 Module Name : /media/ s f n a s h k a m i n s k i / Desktop / c o u r s e s / ece742 / i s e p r o j e c t s / fouradder / f o u r a d d e r t e s t. vhd P r o j e c t Name : 9 Target Device : Tool v e r s i o n s : 11 D e s c r i p t i o n : fouradder 13 VHDL Test Bench Created by ISE f o r module : fouradder 15 Dependencies : 17 Revision : Revision F i l e Created 19 A d d i t i o n a l Comments : 21 Notes : This t e s t b e n c h has been a u t o m a t i c a l l y generated using types s t d l o g i c and 23 s t d l o g i c v e c t o r f o r the p o r t s o f the u n i t under t e s t. X i l i n x recommends that t h e s e types always be used f o r the top l e v e l I /O o f a d e s i g n i n order 25 to guarantee that the t e s t b e n c h w i l l bind c o r r e c t l y to the post implementation s i m u l a t i o n model. 27 LIBRARY i e e e ; 29 USE i e e e. s t d l o g i c ALL; USE i e e e. s t d l o g i c a r i t h.all; 31 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f using a r i t h m e t i c f u n c t i o n s with Signed or Unsigned v a l u e s 33 USE i e e e. numeric std.all; 35 ENTITY f o u r a d d e r t e s t IS END f o u r a d d e r t e s t ; ARCHITECTURE behavior OF f o u r a d d e r t e s t Component D e c l a r a t i o n f o r the Unit Under Test (UUT) COMPONENT fouradder 43 PORT( a : IN s t d l o g i c v e c t o r (3 downto 0) ; 45 b : IN s t d l o g i c v e c t o r (3 downto 0) ; op : IN s t d l o g i c ; 47 CLK : IN s t d l o g i c ; cout : OUT s t d l o g i c ; 49 s : OUT s t d l o g i c v e c t o r (3 downto 0) ) ; 51 END COMPONENT; IS 53 Inputs 55 s i g n a l a : s t d l o g i c v e c t o r (3 downto 0) := ( o t h e r s => 0 ) ; s i g n a l b : s t d l o g i c v e c t o r (3 downto 0) := ( o t h e r s => 0 ) ; 57 s i g n a l op : s t d l o g i c := 0 ; 19

21 s i g n a l CLK : s t d l o g i c := 0 ; 59 Outputs s i g n a l cout : s t d l o g i c ; 61 s i g n a l s : s t d l o g i c v e c t o r (3 downto 0) ; BEGIN constant CLK period : time := 10 ns ; I n s t a n t i a t e the Unit Under Test (UUT) 69 uut : fouradder PORT MAP ( a => a, 71 b => b, op => op, 73 CLK => CLK, cout => cout, 75 s => s ) ; 77 Clock p r o c e s s d e f i n i t i o n s 79 CLK process : p r o c e s s begin 81 CLK <= 0 ; wait f o r CLK period / 2 ; 83 CLK <= 1 ; wait f o r CLK period / 2 ; 85 end p r o c e s s ; 87 Stimulus p r o c e s s 89 s t i m p r o c : p r o c e s s begin 91 hold r e s e t s t a t e f o r 100 ns. wait f o r 100 ns ; wait f o r CLK period 1 0 ; i n s e r t s t i m u l u s here 97 a <= c o n v s t d l o g i c v e c t o r ( 2, 4 ) ; b <= c o n v s t d l o g i c v e c t o r ( 3, 4 ) ; 99 op <= 0 ; wait f o r CLK period ; 101 a <= c o n v s t d l o g i c v e c t o r ( 1, 4 ) ; b <= c o n v s t d l o g i c v e c t o r ( 5, 4 ) ; 103 op <= 0 ; wait f o r CLK period ; 105 a <= c o n v s t d l o g i c v e c t o r ( 2, 4 ) ; b <= c o n v s t d l o g i c v e c t o r ( 3, 4 ) ; 107 op <= 1 ; wait f o r CLK period ; 109 wait ; end p r o c e s s ; 111 END; iseprojects/fouradder/fouraddertest.vhd 2 Company : Engineer : 4 Create Date : 1 5 : 5 2 : /05/ Design Name : Module Name : fouradder S t r u c t u r a l 20

22 8 P r o j e c t Name : Target Devices : 10 Tool v e r s i o n s : D e s c r i p t i o n : 12 Dependencies : 14 Revision : 16 Revision F i l e Created A d d i t i o n a l Comments : l i b r a r y IEEE ; use IEEE. STD LOGIC 1164.ALL; 22 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f using 24 a r i t h m e t i c f u n c t i o n s with Signed or Unsigned v a l u e s use IEEE. NUMERIC STD. ALL; 26 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f i n s t a n t i a t i n g 28 any X i l i n x p r i m i t i v e s i n t h i s code. l i b r a r y UNISIM ; 30 use UNISIM. VComponents. a l l ; 32 e n t i t y fouradder i s Port ( a : i n STD LOGIC VECTOR ( 3 downto 0) ; 34 b : i n STD LOGIC VECTOR ( 3 downto 0) ; op : i n STD LOGIC ; 36 CLK : i n STD LOGIC ; cout : out STD LOGIC ; 38 s : out STD LOGIC VECTOR ( 3 downto 0) ) ; end fouradder ; 40 a r c h i t e c t u r e S t r u c t u r a l o f fouradder i s 42 component f u l l a d d e r Port ( a : i n STD LOGIC ; 44 b : i n STD LOGIC ; c i n : i n STD LOGIC ; 46 o p s e l : i n STD LOGIC ; s : out STD LOGIC ; 48 cout : out STD LOGIC) ; end component ; 50 s i g n a l c : s t d l o g i c v e c t o r (3 downto 1) ; begin 52 add0 : f u l l a d d e r port map ( a ( 0 ), b ( 0 ), op, op, s ( 0 ), c ( 1 ) ) ; add1 : f u l l a d d e r port map ( a ( 1 ), b ( 1 ), c ( 1 ), op, s ( 1 ), c ( 2 ) ) ; 54 add2 : f u l l a d d e r port map ( a ( 2 ), b ( 2 ), c ( 2 ), op, s ( 2 ), c ( 3 ) ) ; add3 : f u l l a d d e r port map ( a ( 3 ), b ( 3 ), c ( 3 ), op, s ( 3 ), cout ) ; 56 end S t r u c t u r a l ; iseprojects/fouradder/fouradder.vhd 2 Company : Engineer : 4 Create Date : 1 5 : 4 4 : /05/ Design Name : Module Name : f u l l a d d e r S t r u c t u r a l 8 P r o j e c t Name : Target Devices : 10 Tool v e r s i o n s : D e s c r i p t i o n : 12 Dependencies : 21

23 14 Revision : 16 Revision F i l e Created A d d i t i o n a l Comments : l i b r a r y IEEE ; use IEEE. STD LOGIC 1164.ALL; 22 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f using 24 a r i t h m e t i c f u n c t i o n s with Signed or Unsigned v a l u e s use IEEE. NUMERIC STD. ALL; 26 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f i n s t a n t i a t i n g 28 any X i l i n x p r i m i t i v e s i n t h i s code. l i b r a r y UNISIM ; 30 use UNISIM. VComponents. a l l ; 32 e n t i t y f u l l a d d e r i s Port ( a : i n STD LOGIC ; 34 b : i n STD LOGIC ; c i n : i n STD LOGIC ; 36 o p s e l : i n STD LOGIC ; s : out STD LOGIC ; 38 cout : out STD LOGIC) ; end f u l l a d d e r ; 40 a r c h i t e c t u r e S t r u c t u r a l o f f u l l a d d e r i s 42 s i g n a l b1 : STD LOGIC ; begin 44 b1 <= b XOR o p s e l ; s <= ( a XOR b1 ) XOR c i n ; 46 cout <= ( a AND b1 ) OR ( a AND c i n ) OR ( b1 AND c i n ) ; end S t r u c t u r a l ; iseprojects/fouradder/fulladder.vhd 4-bit Hamming code Error Detector and Corrector 1 Company : 3 Engineer : 5 Create Date : 1 7 : 5 2 : /05/2016 Design Name : 7 Module Name : /media/ s f n a s h k a m i n s k i / Desktop / c o u r s e s / ece742 / i s e p r o j e c t s /hamming4/ p a r g e n t e s t. vhd P r o j e c t Name : 9 Target Device : Tool v e r s i o n s : 11 D e s c r i p t i o n : hamming4 13 VHDL Test Bench Created by ISE f o r module : pargen 15 Dependencies : 17 Revision : Revision F i l e Created 19 A d d i t i o n a l Comments : 21 Notes : This t e s t b e n c h has been a u t o m a t i c a l l y generated using types s t d l o g i c and 23 s t d l o g i c v e c t o r f o r the p o r t s o f the u n i t under t e s t. X i l i n x recommends that t h e s e types always be used f o r the top l e v e l I /O o f a d e s i g n i n order 22

24 25 to guarantee that the t e s t b e n c h w i l l bind c o r r e c t l y to the post implementation s i m u l a t i o n model. 27 LIBRARY i e e e ; 29 USE i e e e. s t d l o g i c ALL; 31 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f using a r i t h m e t i c f u n c t i o n s with Signed or Unsigned v a l u e s 33 USE i e e e. numeric std.all; 35 ENTITY p a r g e n t e s t IS END p a r g e n t e s t ; ARCHITECTURE behavior OF p a r g e n t e s t Component D e c l a r a t i o n f o r the Unit Under Test (UUT) COMPONENT pargen 43 PORT( i p : IN s t d l o g i c v e c t o r (3 downto 0) ; 45 CLK : IN s t d l o g i c ; op : OUT s t d l o g i c v e c t o r (6 downto 0) 47 ) ; END COMPONENT; Inputs s i g n a l i p : s t d l o g i c v e c t o r (3 downto 0) := ( o t h e r s => 0 ) ; 53 s i g n a l CLK : s t d l o g i c := 0 ; 55 Outputs s i g n a l op : s t d l o g i c v e c t o r (6 downto 0) ; 57 Clock p e r i o d d e f i n i t i o n s 59 constant CLK period : time := 10 ns ; 61 BEGIN 63 I n s t a n t i a t e the Unit Under Test (UUT) uut : pargen PORT MAP ( 65 i p => ip, CLK => CLK, 67 op => op ) ; 69 Clock p r o c e s s d e f i n i t i o n s 71 CLK process : p r o c e s s begin 73 CLK <= 0 ; wait f o r CLK period / 2 ; 75 CLK <= 1 ; wait f o r CLK period / 2 ; 77 end p r o c e s s ; IS 79 Stimulus p r o c e s s 81 s t i m p r o c : p r o c e s s begin 83 hold r e s e t s t a t e f o r 100 ns. wait f o r 100 ns ; wait f o r CLK period 1 0 ; i n s e r t s t i m u l u s here 89 i p <= 0000 ; 23

25 wait f o r CLK period ; 91 i p <= 0001 ; wait f o r CLK period ; 93 i p <= 0010 ; wait f o r CLK period ; 95 i p <= 0011 ; wait f o r CLK period ; 97 i p <= 1111 ; wait f o r CLK period ; 99 wait ; end p r o c e s s ; 101 END; iseprojects/hamming4/pargentest.vhd 2 Company : Engineer : 4 Create Date : 1 7 : 0 6 : /05/ Design Name : Module Name : pargen S t r u c t u r a l 8 P r o j e c t Name : Target Devices : 10 Tool v e r s i o n s : D e s c r i p t i o n : 12 Dependencies : 14 Revision : 16 Revision F i l e Created A d d i t i o n a l Comments : l i b r a r y IEEE ; use IEEE. STD LOGIC 1164.ALL; 22 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f using 24 a r i t h m e t i c f u n c t i o n s with Signed or Unsigned v a l u e s use IEEE. NUMERIC STD. ALL; 26 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f i n s t a n t i a t i n g 28 any X i l i n x p r i m i t i v e s i n t h i s code. l i b r a r y UNISIM ; 30 use UNISIM. VComponents. a l l ; 32 e n t i t y pargen i s Port ( i p : i n STD LOGIC VECTOR ( 3 downto 0) ; 34 CLK : i n STD LOGIC ; op : out STD LOGIC VECTOR ( 6 downto 0) ) ; 36 end pargen ; 38 a r c h i t e c t u r e S t r u c t u r a l o f pargen i s s i g n a l b : STD LOGIC VECTOR (6 downto 0) ; 40 begin b ( 0 ) <= i p ( 0 ) xor i p ( 1 ) xor i p ( 3 ) ; 42 b ( 1 ) <= i p ( 0 ) xor i p ( 2 ) xor i p ( 3 ) ; b ( 2 ) <= i p ( 0 ) ; 44 b ( 3 ) <= i p ( 1 ) xor i p ( 2 ) xor i p ( 3 ) ; b ( 4 ) <= i p ( 1 ) ; 46 b ( 5 ) <= i p ( 2 ) ; b ( 6 ) <= i p ( 3 ) ; 48 op <= b ; end S t r u c t u r a l ; 24

26 iseprojects/hamming4/pargen.vhd 2 Company : Engineer : 4 Create Date : 1 6 : 4 2 : /07/ Design Name : Module Name : /media/ s f n a s h k a m i n s k i / Desktop / c o u r s e s / ece742 / i s e p r o j e c t s /hamming4/ c h e c k g e n t e s t. vhd 8 P r o j e c t Name : hamming4 Target Device : 10 Tool v e r s i o n s : D e s c r i p t i o n : 12 VHDL Test Bench Created by ISE f o r module : checkgen 14 Dependencies : 16 Revision : 18 Revision F i l e Created A d d i t i o n a l Comments : 20 Notes : 22 This t e s t b e n c h has been a u t o m a t i c a l l y generated using types s t d l o g i c and s t d l o g i c v e c t o r f o r the p o r t s o f the u n i t under t e s t. X i l i n x recommends 24 that t h e s e types always be used f o r the top l e v e l I /O o f a d e s i g n i n order to guarantee that the t e s t b e n c h w i l l bind c o r r e c t l y to the post implementation 26 s i m u l a t i o n model. 28 LIBRARY i e e e ; USE i e e e. s t d l o g i c ALL; 30 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f using 32 a r i t h m e t i c f u n c t i o n s with Signed or Unsigned v a l u e s USE i e e e. numeric std.all; 34 ENTITY c h e c k g e n t e s t 36 END c h e c k g e n t e s t ; 38 ARCHITECTURE behavior OF c h e c k g e n t e s t IS IS 40 Component D e c l a r a t i o n f o r the Unit Under Test (UUT) 42 COMPONENT checkgen PORT( 44 i p : IN s t d l o g i c v e c t o r (6 downto 0) ; c : OUT s t d l o g i c v e c t o r (2 downto 0) ; 46 CLK : IN s t d l o g i c ; d : OUT s t d l o g i c v e c t o r (6 downto 0) 48 ) ; END COMPONENT; Inputs s i g n a l i p : s t d l o g i c v e c t o r (6 downto 0) := ( o t h e r s => 0 ) ; 54 s i g n a l CLK : s t d l o g i c := 0 ; 56 Outputs s i g n a l c : s t d l o g i c v e c t o r (2 downto 0) ; 58 s i g n a l d : s t d l o g i c v e c t o r (6 downto 0) ; 60 Clock p e r i o d d e f i n i t i o n s constant CLK period : time := 10 ns ; 25

27 62 64 BEGIN I n s t a n t i a t e the Unit Under Test (UUT) 66 uut : checkgen PORT MAP ( i p => ip, 68 c => c, CLK => CLK, 70 d => d ) ; 72 Clock p r o c e s s d e f i n i t i o n s 74 CLK process : p r o c e s s begin 76 CLK <= 0 ; wait f o r CLK period / 2 ; 78 CLK <= 1 ; wait f o r CLK period / 2 ; 80 end p r o c e s s ; 82 Stimulus p r o c e s s 84 s t i m p r o c : p r o c e s s begin 86 hold r e s e t s t a t e f o r 100 ns. wait f o r 100 ns ; 88 i p <= ; wait f o r CLK period ; 90 i p <= ; wait f o r CLK period ; 92 i p <= ; wait f o r CLK period ; 94 i p <= ; wait ; 96 end p r o c e s s ; 98 END; iseprojects/hamming4/checkgentest.vhd 2 Company : Engineer : 4 Create Date : 1 7 : 2 3 : /05/ Design Name : Module Name : checkgen S t r u c t u r a l 8 P r o j e c t Name : Target Devices : 10 Tool v e r s i o n s : D e s c r i p t i o n : 12 Dependencies : 14 Revision : 16 Revision F i l e Created A d d i t i o n a l Comments : l i b r a r y IEEE ; use IEEE. STD LOGIC 1164.ALL; 22 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f using 24 a r i t h m e t i c f u n c t i o n s with Signed or Unsigned v a l u e s use IEEE. NUMERIC STD. ALL; 26

28 26 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f i n s t a n t i a t i n g 28 any X i l i n x p r i m i t i v e s i n t h i s code. l i b r a r y UNISIM ; 30 use UNISIM. VComponents. a l l ; 32 e n t i t y checkgen i s Port ( i p : i n STD LOGIC VECTOR ( 6 downto 0) ; 34 c : out STD LOGIC VECTOR ( 2 downto 0) ; CLK : i n STD LOGIC ; 36 d : out STD LOGIC VECTOR ( 6 downto 0) ) ; end checkgen ; 38 a r c h i t e c t u r e S t r u c t u r a l o f checkgen i s 40 begin d <= i p ; 42 c ( 0 ) <= i p ( 0 ) xor i p ( 2 ) xor i p ( 4 ) xor i p ( 6 ) ; c ( 1 ) <= i p ( 1 ) xor i p ( 2 ) xor i p ( 5 ) xor i p ( 6 ) ; 44 c ( 2 ) <= i p ( 3 ) xor i p ( 4 ) xor i p ( 5 ) xor i p ( 6 ) ; 46 end S t r u c t u r a l ; iseprojects/hamming4/checkgen.vhd 1 Company : 3 Engineer : 5 Create Date : 1 7 : 3 1 : /07/2016 Design Name : 7 Module Name : /media/ s f n a s h k a m i n s k i / Desktop / c o u r s e s / ece742 / i s e p r o j e c t s /hamming4/ e c c t e s t. vhd P r o j e c t Name : hamming4 9 Target Device : Tool v e r s i o n s : 11 D e s c r i p t i o n : 13 VHDL Test Bench Created by ISE f o r module : e c c 15 Dependencies : 17 Revision : Revision F i l e Created 19 A d d i t i o n a l Comments : 21 Notes : This t e s t b e n c h has been a u t o m a t i c a l l y generated using types s t d l o g i c and 23 s t d l o g i c v e c t o r f o r the p o r t s o f the u n i t under t e s t. X i l i n x recommends that t h e s e types always be used f o r the top l e v e l I /O o f a d e s i g n i n order 25 to guarantee that the t e s t b e n c h w i l l bind c o r r e c t l y to the post implementation s i m u l a t i o n model. 27 LIBRARY i e e e ; 29 USE i e e e. s t d l o g i c ALL; 31 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f using a r i t h m e t i c f u n c t i o n s with Signed or Unsigned v a l u e s 33 USE i e e e. numeric std.all; 35 ENTITY e c c t e s t IS END e c c t e s t ; ARCHITECTURE behavior OF e c c t e s t Component D e c l a r a t i o n f o r the Unit Under Test (UUT) IS 27

29 COMPONENT ecc 43 PORT( c i n : IN s t d l o g i c v e c t o r (2 downto 0) ; 45 din : IN s t d l o g i c v e c t o r (6 downto 0) ; CLK : IN s t d l o g i c ; 47 dout : OUT s t d l o g i c v e c t o r (3 downto 0) ) ; 49 END COMPONENT; 51 Inputs 53 s i g n a l c i n : s t d l o g i c v e c t o r (2 downto 0) := ( o t h e r s => 0 ) ; s i g n a l din : s t d l o g i c v e c t o r (6 downto 0) := ( o t h e r s => 0 ) ; 55 s i g n a l CLK : s t d l o g i c := 0 ; 57 Outputs s i g n a l dout : s t d l o g i c v e c t o r (3 downto 0) ; 59 Clock p e r i o d d e f i n i t i o n s 61 constant CLK period : time := 10 ns ; 63 BEGIN 65 I n s t a n t i a t e the Unit Under Test (UUT) uut : ecc PORT MAP ( 67 c i n => cin, din => din, 69 CLK => CLK, dout => dout 71 ) ; 73 Clock p r o c e s s d e f i n i t i o n s CLK process : p r o c e s s 75 begin CLK <= 0 ; 77 wait f o r CLK period / 2 ; CLK <= 1 ; 79 wait f o r CLK period / 2 ; end p r o c e s s ; Stimulus p r o c e s s s t i m p r o c : p r o c e s s 85 begin hold r e s e t s t a t e f o r 100 ns. 87 wait f o r 100 ns ; 89 wait f o r CLK period 1 0 ; 91 i n s e r t s t i m u l u s here din <= ; 93 c i n <= 000 ; wait f o r CLK period ; 95 c i n <= 011 ; wait f o r CLK period ; 97 c i n <= 101 ; wait f o r CLK period ; 99 c i n <= 111 ; wait f o r CLK period ; 101 wait ; end p r o c e s s ; 103 END; iseprojects/hamming4/ecctest.vhd 28

30 2 Company : Engineer : 4 Create Date : 1 7 : 3 5 : /05/ Design Name : Module Name : ecc Behavioral 8 P r o j e c t Name : Target Devices : 10 Tool v e r s i o n s : D e s c r i p t i o n : 12 Dependencies : 14 Revision : 16 Revision F i l e Created A d d i t i o n a l Comments : l i b r a r y IEEE ; use IEEE. STD LOGIC 1164.ALL; 22 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f using 24 a r i t h m e t i c f u n c t i o n s with Signed or Unsigned v a l u e s use IEEE. NUMERIC STD. ALL; 26 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f i n s t a n t i a t i n g 28 any X i l i n x p r i m i t i v e s i n t h i s code. l i b r a r y UNISIM ; 30 use UNISIM. VComponents. a l l ; 32 e n t i t y ecc i s Port ( c i n : i n STD LOGIC VECTOR ( 2 downto 0) ; 34 din : i n STD LOGIC VECTOR ( 6 downto 0) ; CLK : i n STD LOGIC ; 36 dout : out STD LOGIC VECTOR ( 3 downto 0) ) ; end ecc ; 38 a r c h i t e c t u r e Behavioral o f ecc i s 40 s i g n a l c o r r : s t d l o g i c v e c t o r (6 downto 0) ; s i g n a l corrcw : s t d l o g i c v e c t o r (6 downto 0) ; 42 s i g n a l c o r r d a t a : s t d l o g i c v e c t o r (6 downto 0) ; constant one : b i t v e c t o r (6 downto 0) := ; 44 begin 46 C o r r e c t i o n b i t c o r r <= t o s t d l o g i c v e c t o r ( one s l l ( t o i n t e g e r ( unsigned ( c i n ) ) 1) ) ; 48 c o r r d a t a <= din xor c o r r ; Use c o r r e c t e d data i f e r r o r 50 corrcw <= din when c i n = 000 e l s e c o r r d a t a ; dout ( 0 ) <= corrcw ( 2 ) ; 52 dout ( 1 ) <= corrcw ( 4 ) ; dout ( 2 ) <= corrcw ( 5 ) ; 54 dout ( 3 ) <= corrcw ( 6 ) ; 56 end Behavioral ; iseprojects/hamming4/ecc.vhd 1 Company : 3 Engineer : 5 Create Date : 1 7 : 5 9 : /07/2016 Design Name : 29

31 7 Module Name : t o p l e v e l Behavioral P r o j e c t Name : 9 Target Devices : Tool v e r s i o n s : 11 D e s c r i p t i o n : 13 Dependencies : 15 Revision : Revision F i l e Created 17 A d d i t i o n a l Comments : 19 l i b r a r y IEEE ; 21 use IEEE. STD LOGIC 1164.ALL; 23 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f using a r i t h m e t i c f u n c t i o n s with Signed or Unsigned v a l u e s 25 use IEEE. NUMERIC STD. ALL; 27 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f i n s t a n t i a t i n g any X i l i n x p r i m i t i v e s i n t h i s code. 29 l i b r a r y UNISIM ; use UNISIM. VComponents. a l l ; 31 e n t i t y t o p l e v e l i s 33 Port ( data : i n STD LOGIC VECTOR ( 3 downto 0) ; e r r o r : i n STD LOGIC VECTOR (6 downto 0) ; 35 c b i t : out STD LOGIC VECTOR (2 downto 0) ; output : out STD LOGIC VECTOR ( 3 downto 0) ; 37 CLK : i n STD LOGIC) ; end t o p l e v e l ; 39 a r c h i t e c t u r e Behavioral o f t o p l e v e l i s 41 COMPONENT checkgen PORT( 43 i p : IN s t d l o g i c v e c t o r (6 downto 0) ; c : OUT s t d l o g i c v e c t o r (2 downto 0) ; 45 CLK : IN s t d l o g i c ; d : OUT s t d l o g i c v e c t o r (6 downto 0) 47 ) ; END COMPONENT; 49 COMPONENT ecc PORT( 51 c i n : IN s t d l o g i c v e c t o r (2 downto 0) ; din : IN s t d l o g i c v e c t o r (6 downto 0) ; 53 CLK : IN s t d l o g i c ; dout : OUT s t d l o g i c v e c t o r (3 downto 0) 55 ) ; END COMPONENT; 57 COMPONENT pargen PORT( 59 i p : IN s t d l o g i c v e c t o r (3 downto 0) ; CLK : IN s t d l o g i c ; 61 op : OUT s t d l o g i c v e c t o r (6 downto 0) ) ; 63 END COMPONENT; s i g n a l code0 : s t d l o g i c v e c t o r (6 downto 0) ; 65 s i g n a l code1 : s t d l o g i c v e c t o r (6 downto 0) ; s i g n a l chk : s t d l o g i c v e c t o r (2 downto 0) ; 67 s i g n a l data0 : s t d l o g i c v e c t o r (6 downto 0) ; begin 69 pg0 : pargen PORT MAP ( i p => data, 71 CLK => CLK, 30

32 op => code0 73 ) ; code1 <= code0 xor e r r o r ; 75 check0 : checkgen PORT MAP ( 77 i p => code1, c => chk, 79 CLK => CLK, d => data0 81 ) ; ecc0 : ecc PORT MAP ( 83 c i n => chk, din => data0, 85 CLK => CLK, dout => output 87 ) ; c b i t <= chk ; 89 end Behavioral ; iseprojects/hamming4/toplevel.vhd 8-bit Hamming code Error Detector and Corrector 2 Company : Engineer : 4 Create Date : 1 7 : 5 2 : /05/ Design Name : Module Name : /media/ s f n a s h k a m i n s k i / Desktop / c o u r s e s / ece742 / i s e p r o j e c t s /hamming4/ p a r g e n t e s t. vhd 8 P r o j e c t Name : hamming4 Target Device : 10 Tool v e r s i o n s : D e s c r i p t i o n : 12 VHDL Test Bench Created by ISE f o r module : pargen 14 Dependencies : 16 Revision : 18 Revision F i l e Created A d d i t i o n a l Comments : 20 Notes : 22 This t e s t b e n c h has been a u t o m a t i c a l l y generated using types s t d l o g i c and s t d l o g i c v e c t o r f o r the p o r t s o f the u n i t under t e s t. X i l i n x recommends 24 that t h e s e types always be used f o r the top l e v e l I /O o f a d e s i g n i n order to guarantee that the t e s t b e n c h w i l l bind c o r r e c t l y to the post implementation 26 s i m u l a t i o n model. 28 LIBRARY i e e e ; USE i e e e. s t d l o g i c ALL; 30 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f using 32 a r i t h m e t i c f u n c t i o n s with Signed or Unsigned v a l u e s USE i e e e. numeric std.all; 34 ENTITY p a r g e n t e s t 36 END p a r g e n t e s t ; 38 ARCHITECTURE behavior OF p a r g e n t e s t IS IS 40 Component D e c l a r a t i o n f o r the Unit Under Test (UUT) 31

33 42 COMPONENT pargen PORT( 44 i p : IN s t d l o g i c v e c t o r (7 downto 0) ; CLK : IN s t d l o g i c ; 46 op : OUT s t d l o g i c v e c t o r (11 downto 0) ) ; 48 END COMPONENT; 50 Inputs 52 s i g n a l i p : s t d l o g i c v e c t o r (7 downto 0) := ( o t h e r s => 0 ) ; s i g n a l CLK : s t d l o g i c := 0 ; 54 Outputs 56 s i g n a l op : s t d l o g i c v e c t o r (11 downto 0) ; 58 Clock p e r i o d d e f i n i t i o n s constant CLK period : time := 10 ns ; BEGIN I n s t a n t i a t e the Unit Under Test (UUT) 64 uut : pargen PORT MAP ( i p => ip, 66 CLK => CLK, op => op 68 ) ; 70 Clock p r o c e s s d e f i n i t i o n s CLK process : p r o c e s s 72 begin CLK <= 0 ; 74 wait f o r CLK period / 2 ; CLK <= 1 ; 76 wait f o r CLK period / 2 ; end p r o c e s s ; Stimulus p r o c e s s s t i m p r o c : p r o c e s s 82 begin hold r e s e t s t a t e f o r 100 ns. 84 wait f o r 100 ns ; 86 wait f o r CLK period 1 0 ; 88 i n s e r t s t i m u l u s here i p <= ; 90 wait f o r CLK period ; i p <= ; 92 wait f o r CLK period ; i p <= ; 94 wait f o r CLK period ; i p <= ; 96 wait f o r CLK period ; i p <= ; 98 wait f o r CLK period ; wait ; 100 end p r o c e s s ; 102 END; iseprojects/hamming8/pargentest.vhd 32

34 2 Company : Engineer : 4 Create Date : 1 7 : 0 6 : /05/ Design Name : Module Name : pargen S t r u c t u r a l 8 P r o j e c t Name : Target Devices : 10 Tool v e r s i o n s : D e s c r i p t i o n : 12 Dependencies : 14 Revision : 16 Revision F i l e Created A d d i t i o n a l Comments : l i b r a r y IEEE ; use IEEE. STD LOGIC 1164.ALL; 22 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f using 24 a r i t h m e t i c f u n c t i o n s with Signed or Unsigned v a l u e s use IEEE. NUMERIC STD. ALL; 26 Uncomment the f o l l o w i n g l i b r a r y d e c l a r a t i o n i f i n s t a n t i a t i n g 28 any X i l i n x p r i m i t i v e s i n t h i s code. l i b r a r y UNISIM ; 30 use UNISIM. VComponents. a l l ; 32 e n t i t y pargen i s Port ( i p : i n STD LOGIC VECTOR ( 7 downto 0) ; 34 CLK : i n STD LOGIC ; op : out STD LOGIC VECTOR ( 11 downto 0) ) ; 36 end pargen ; 38 a r c h i t e c t u r e S t r u c t u r a l o f pargen i s s i g n a l b : STD LOGIC VECTOR (11 downto 0) ; 40 begin 3, 5, 7, 9, b ( 0 ) <= i p ( 0 ) xor i p ( 1 ) xor i p ( 3 ) xor i p ( 4 ) xor i p ( 6 ) ; 3, 6, 7, 10, b ( 1 ) <= i p ( 0 ) xor i p ( 2 ) xor i p ( 3 ) xor i p ( 5 ) xor i p ( 6 ) ; b ( 2 ) <= i p ( 0 ) ; 46 5, 6, 7, 12 b ( 3 ) <= i p ( 1 ) xor i p ( 2 ) xor i p ( 3 ) xor i p ( 7 ) ; 48 b ( 4 ) <= i p ( 1 ) ; b ( 5 ) <= i p ( 2 ) ; 50 b ( 6 ) <= i p ( 3 ) ; 9, 10, 11, b ( 7 ) <= i p ( 4 ) xor i p ( 5 ) xor i p ( 6 ) xor i p ( 7 ) ; b ( 8 ) <= i p ( 4 ) ; 54 b ( 9 ) <= i p ( 5 ) ; b ( 1 0 )<= i p ( 6 ) ; 56 b ( 1 1 )<= i p ( 7 ) ; op <= b ; 58 end S t r u c t u r a l ; iseprojects/hamming8/pargen.vhd 1 Company : 3 Engineer : 33