Luleå Tekniska Universitet Kurskod SMD098 Tentamensdatum

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Berniece Payne
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1 Luleå Tekniska Universitet Kurskod SMD098 Tentamensdatum Skrivtid 4 timmar Tentamen i Beräkningsstrukturer Antal uppgifter: 6 Max poäng: 30 Betygsgränser: >20 poäng 4 >25 poäng 5 Betygsgränser kan komma att sänkas, dock ej höjas. Tentamen ger enbart betyget U, 4 eller 5. Har studenten fått godkänt på den praktiska delen av kursen ger detta betyget 3 även om resultatet på tentamen är ett U. Lärare: Tel: 2459 Jonas Thor Tillåtna hjälpmedel: Inga förutom skrivmaterial! Längst bak i tentamen hittar ni en guide till VHDL syntax. Frågorna besvaras på själva tentamen och lösblad. Lämna in tentamen och lösblad. Svaren skrives på svenska. Lycka till! 1

2 1. Xilinx XC4000 Configurable Logic Block (CLB) (5p) You have the following VHDL code library ieee; use ieee.std_logic_1164.all; entity Logic is port ( Clk : in std_logic; -- Clock Reset : in std_logic; -- Reset Enable : in std_logic; -- Clock Enable A, B, C, D, E, F, G, H, I : in std_logic; -- Logic Inputs Y : out std_logic); -- Output end Logic; architecture RTL of Logic is process(clk, Reset) if Reset = 1 then Y <= 0 ; elsif rising_edge(clk) then if Enable = 1 then Y <= (A and B and C and D) xor E xor (F or G or H or I); end if; end if; end process; end RTL; a) Draw the schematics of the VHDL model below. (1p) 2

3 b) The modeled logic can be implemented in a single Xilinx XC4000 CLB. In the figure below, clearly indicate how the CLB is configured. Name the inputs/outputs as they are defined in the VHDL source. Use a pen to indicate what connections and resources are used. Show how the multiplexers are configured by drawing a line through them, from one input to the output. (2p) C 1 C 4 4 H 1 D IN /H 2 SR/H0 EC G 4 G 3 G 2 LOGIC FUNCTION G' OF G1-G4 DIN F' G' H' S/R CONTROL D SD Q Bypass YQ G 1 LOGIC FUNCTION OF H' F', G', AND H1 G' H' 1 EC RD Y F 4 F 3 F 2 LOGIC FUNCTION OF F1-F4 F' DIN F' G' H' S/R CONTROL D SD Q Bypass XQ F 1 K (CLOCK) H' F' 1 EC RD X Multiplexer Controlled by Configuration Program X6692 3

4 c) You probably used the Look-Up Tables (LUT) F, G and H in b). What are the contents of the LUTs, i.e. how are they programmed. Complete the tables below. (2p) F1 F2 F3 F4 F G1 G2 G3 G4 G F G H1 H

5 2. Manual synthesis (5p, 1p each) Here you are given five different VHDL models. Your task is to draw the schematics of the VHDL models. Use gates, multiplexers, flip-flops etc. Clearly mark the names of the inputs/outputs as indicated in the VHDL source. a) library ieee; use ieee.std_logic_1164.all; entity Signals is port ( Clk : in std_logic; -- Clock A, B, C : in std_logic; -- Inputs Y, X : out std_logic); -- Outputs end Signals; architecture RTL of Signals is signal S1, S2 : std_logic; process(clk) if rising_edge(clk) then S1 <= A and B; S2 <= S1 or C; X <= S1; Y <= S2; end if; end process; end RTL; 5

6 b) library ieee; use ieee.std_logic_1164.all; entity Variables is port ( Clk : in std_logic; -- Clock A, B, C : in std_logic; -- Inputs Y, X : out std_logic); -- Outputs end Variables; architecture RTL of Variables is process(clk) variable V1, V2 : std_logic; if rising_edge(clk) then V1 := A and B; V2 := V1 or C; X <= V1; Y <= V2; end if; end process; end RTL; 6

7 c) library ieee; use ieee.std_logic_1164.all; entity Logic is port ( A, B, C, D, E, F : in std_logic; Y : out std_logic ); end Logic; architecture RTL of Logic is Y <= A when D = 1 else Z ; Y <= B when E = 1 else Z ; Y <= C when F = 1 else Z ; end RTL; 7

8 d) library ieee; use ieee.std_logic_1164.all; entity Astrid is port ( Clk : in std_logic; -- Clock A : in std_logic; -- Inputs Y : out std_logic); -- Outputs end Astrid; architecture RTL of Astrid is signal B, C : std_logic; process(clk) if rising_edge(clk) then C <= B; Y <= C; B <= A; end if; end process; end RTL; 8

9 e) library ieee; use ieee.std_logic_1164.all; entity Kerstin is port ( Clk : in std_logic; -- Clock A : in std_logic; -- Inputs Y : out std_logic); -- Outputs end Kerstin; architecture RTL of Kerstin is process(clk) variable B, C : std_logic; if rising_edge(clk) then C := B; Y <= C; B := A; end if; end process; end RTL; 9

10 3. Synchronous design and timing (5p, 1p each) a) What does the acronym RTL stand for? Give a definition of RTL. b) Draw a timing diagram for a D flip-flop. The timing diagram must show the three important parameters, setup time, hold time and clock-to-output delay. 10

11 c) In the circuit shown below mark the short path and the long path also specify the delays for both paths. The delay of each gate is shown above the gate. Reg A 4 ns 2 ns Reg B 2 ns 1 ns Reg D Reg C Clock d) Now assume that the hold-time for the flip-flops in c) is.5 ns, the setup-time for the flip-flops are 1.5 ns and the clock-to-output delay for the flip-flops are.8 ns. Assuming that we have no clock skew, what is the minimum clock period? Explain and show your calculations 11

12 e) We have the same circuit, but there is clock skew between the input flip-flops and the output flip-flop as indicated in the figure below. The timing parameters for the flipflops are the same as in d). What is the maximum clock skew in order to guarantee failsafe operation? Explain and show your calculations. Reg A 4 ns 2 ns Reg B 2 ns 1 ns Reg D Reg C Clock t skew 12

13 4. State machine design (5 points) Here you will design a Moore finite state machine that controls three LEDs (sw: lysdioder). A simple block diagram of the design is shown in the figure below. Moore FSM L1 Control[1:0] L2 Reset L3 Clk The LEDs will be lit in different sequences depending on the Control input. Only one or zero LEDs are lit at the same time. When Reset is active, all LEDs will be off. The table below shows a functional description of the FSM. Reset (asynch) Control Sequence 1 -- All LEDs are off 0 00 L1 L2 L3 L1 L2 L L3 L2 L1 L3 L2 L L1 L2 L1 L2 L1 L L2 L3 L2 L3 L2 L3... For instance L1 L2 means that in the first clock cycle L1 is lit and in the next clock cycle L2 is lit. Draw a bubble diagram of your Moore FSM and write a VHDL model of the FSM using the entity declaration below. library ieee; use ieee.std_logic_1164.all; entity FSM is port ( Clk : in std_logic; -- Clock : in std_logic; -- Active high asynch reset Reset Control : in std_logic_vector(1 downto 0); L1, L2, L3 : out std_logic -- LED Outputs ); end FSM; 13

14 5. Various questions (5p, 1p each) 1. How are buses with multiple drivers modeled in VHDL? What is the difference between the std_u_logic and std_logic types? 2. The symbol for a 2 1 multiplexer is shown below. Use two tri-state buffers, with active high enable, and an inverter to implement the same functionality. Draw the schematics. A B Sel 0 1 Y 3. Write two VHDL processes, one describing the behavior of a 2-1 multiplexer implemented in gates or LUTs and one process that implements the 2-1 multiplexer with tri-state buffers. 4. Give three reasons why asynchronous designs are more complex than synchronous designs. 5. What is metastability? When can metastability occur? 14

15 6. Implementation technologies (5p) a) Describe the internal structure of a PAL. (0.5p) b) Name four technologies used to program programmable logic. (0.5p) c) FPGA, Full Custom, CPLD, PAL, Standard Cell and Gate Array are six technologies for programmable logic. i. Sort these in order of density (highest lowest). (0.5p) ii. Sort these in order of performance (highest lowest). (0.5p) d) Your company is manufacturing a simple digital circuit board, which needs new chip select logic. Which technology will you use to construct this? Motivate. (1p) e) You are in a hurry to create prototypes to an advanced digital chip. The prototype will be used as a base for a production run of a few thousand samples. Which technologies will you use for the prototypes and the production series respectively? Motivate. (1p) f) The new product to be ready for sale in two years is expected to sell large volumes. It requires handling of both digital and analog signals within a very small surface area. You want to realize this in one single chip. Which technology will you choose? Motivate. (1p) 15

ECE 448 Lecture 6. Finite State Machines. State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code. George Mason University

ECE 448 Lecture 6. Finite State Machines. State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code. George Mason University ECE 448 Lecture 6 Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL Code George Mason University Required reading P. Chu, FPGA Prototyping by VHDL Examples