Shannon dekomposition
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1 Shannon dekomposition Claude Shannon matematiker/elektrotekniker 96 William Sandqvist
2 ÖH 8.6 Visa hur en 4-to- multipleor kan användas som funktionsgenerator för att te. Generera OR-funktionen. William Sandqvist
3 ÖH 8.6 Visa hur en 4-to- multipleor kan användas som funktionsgenerator för att te. Generera OR-funktionen. William Sandqvist
4 ÖH 8.6 Visa hur en 4-to- multipleor kan användas som funktionsgenerator för att te. Generera OR-funktionen. William Sandqvist
5 William Sandqvist
6 BV 6. Sho ho the function f,, m,,, 4, 5, 7 can e implemented using a -to-8 decoder and an OR gate. William Sandqvist illiam@kth.se
7 BV 6. Sho ho the function f,, m,,, 4, 5, 7 can e implemented using a -to-8 decoder and an OR gate. William Sandqvist illiam@kth.se
8 William Sandqvist
9 ÖH 8.7 En majoritetsgrind antar på utgången samma värde som en majoritet av ingångarna. Grinden kan te. användas i feltolerant logik, eller till ildehandlingskretsar. a Ställ upp grindens sanningstaell och minimera funktionen med Karnaughdiagram. Realisera funktionen med AND-OR grindar. Realisera majoritetsgrinden med en 8: MUX. c Använd Shannon dekomposition och realisera majoritetsgrinden med en : MUX och grindar. d Realisera majorotetsgrinden med ara : MUXar. William Sandqvist illiam@kth.se
10 8.7a Med AND OR grindar William Sandqvist
11 8.7a Med AND OR grindar William Sandqvist
12 8.7a Med AND OR grindar M ac a c William Sandqvist illiam@kth.se
13 8.7a Med AND OR grindar M ac a c William Sandqvist illiam@kth.se
14 8.7 Med 8-to- mu William Sandqvist
15 8.7 Med 8-to- mu William Sandqvist
16 8.7c Shannon dekomposition. -to- mu och grindar. William Sandqvist
17 8.7c Shannon dekomposition. -to- mu och grindar. M a c ac ac ac a c a c c c William Sandqvist illiam@kth.se
18 8.7c Shannon dekomposition. -to- mu och grindar. M a c ac ac ac a c a c c c William Sandqvist illiam@kth.se
19 8.7c Shannon dekomposition. -to- mu och grindar. M a c ac ac ac a c a c c c OR William Sandqvist illiam@kth.se
20 8.7c Shannon dekomposition. -to- mu och grindar. M a c ac ac ac a c a c c c a c a c OR William Sandqvist illiam@kth.se
21 8.7c Shannon dekomposition. -to- mu och grindar. M a c ac ac ac a c a c c c a c a c OR William Sandqvist illiam@kth.se
22 8.7d Shannon dekomposition. Enart -to- muar. William Sandqvist
23 William Sandqvist 8.7d Shannon dekomposition. Enart -to- muar. c c c c c c c h c c g c h c g c a c a M
24 William Sandqvist 8.7d Shannon dekomposition. Enart -to- muar. c c c c c c c h c c g c h c g c a c a M
25 William Sandqvist 8.7d Shannon dekomposition. Enart -to- muar. c c c c c c c h c c g c h c g c a c a M
26 William Sandqvist
27 BV 6.5 For the function f,, m,,, 6 use Shannon s epansion to derive an implementation using a -to- multipleer and any necessary gates. William Sandqvist illiam@kth.se
28 BV 6.5 William Sandqvist For the function use Shannon s epansion to derive an implementation using a -to- multipleer and any necessary gates. 6,,,,, m f,,,,, m f
29 BV 6.5 William Sandqvist For the function use Shannon s epansion to derive an implementation using a -to- multipleer and any necessary gates. 6,,,,, m f,,,,, m f
30 BV 6.5 William Sandqvist For the function use Shannon s epansion to derive an implementation using a -to- multipleer and any necessary gates. 6,,,,, m f,,,,, m f
31 William Sandqvist
32 ÖH 8.9 Visa hur en 4 ingångars eorgrind XOR, udda paritetsfunktion realiseras i en FPGA-krets. Visa innehållet i SRAM-cellerna LUT, LookUp Tale. William Sandqvist illiam@kth.se
33 8.9 William Sandqvist
34 8.9 William Sandqvist
35 8.9 William Sandqvist
36 ÖH 8.8 Ställ upp Ställ upp heladderarens sanningstaell. Visa hur en heladderare realiseras i en FPGA-krets. Logikelementen i en FPGA har möjlighet att kaskadkoppla C OUT och C IN mellan grannarna. Visa innehållet i SRAMcellerna LUT, LookUp Tale. William Sandqvist illiam@kth.se
37 8.8 William Sandqvist
38 8.8 William Sandqvist
39 8.8 William Sandqvist
40 8.8 William Sandqvist
41 BV e 6. In digital systems it is often necessary to have circuits that can shift the its of a vector one or more it positions to the left or right. Design a circuit that can shift a four-it vector W one it position to the right hen a control signal Shift is equal to. Let the outputs of the circuit e a four-it vector Y y y y y and a signal k, such that if Shift then y, y, y, y, and k. If Shift then Y W and k. William Sandqvist illiam@kth.se
42 William Sandqvist
43 BV e 6. Vi använder multipleorer: William Sandqvist illiam@kth.se
44 BV e 6. Vi använder multipleorer: William Sandqvist illiam@kth.se
45 William Sandqvist
46 BV e. 6. Barrel shifter The shifter in Eample 6. shifts the its of an input vector y one it position to the right. It fills the vacated it on the left side ith. If the its that are shifted out are placed into the vacated position on the left, then the circuit effectively rotates the its of the input vector y a specified numer of it positions. Such a circuit is called a arrel shifter. Design a four-it arrel shifter that rotates the its y,,, or it positions as determined y the valuation of to control signals s and s. En arrelshifter används för att snaa upp flyttalsoperationer. William Sandqvist illiam@kth.se
47 Barrel shifter William Sandqvist
48 BV e. 6. Sanningstaell: William Sandqvist
49 BV e. 6. Sanningstaell: William Sandqvist
50 BV e. 6. Sanningstaell: William Sandqvist
51 BV e. 6. Sanningstaell: William Sandqvist
52 BV e. 6. Sanningstaell: William Sandqvist
53 BV e. 6. Sanningstaell: Och så vidare William Sandqvist
54 William Sandqvist
55 Lågpris FPGA Key Benefits Loest FPGA unit cost starting at $.49 Ultra-lo poer in Flash*Freeze mode, as lo as µw Nonvolatile FPGA eliminates unnecessary parts from BOM Single-chip and ultra-lo-poer products simplify oard design Variety of cost-optimized packages reduce assemly costs Lo-poer FPGAs reduce thermal management and cooling needs William Sandqvist
56 BV 6.6 Actel Corporation manufactures an FPGA family called Act, hich uses multipleer ased logic locks. Sho ho the function f can e implemented using only ACT logic locks. William Sandqvist illiam@kth.se
57 BV 6.6 f William Sandqvist illiam@kth.se
58 William Sandqvist BV 6.6 f f f
59 William Sandqvist BV 6.6 f f f
60 William Sandqvist BV 6.6 f f f
61 William Sandqvist
62 William Sandqvist VHDL BV.5a Write VHDL code to descrie the folloing functions f f VHDL koden skrivs med en teteditor och sparas i en fil med ändelsen.vhd. Koden estår alltid av två avsnitt ENTITY och ARCHITECTURE. Entity är en eskrivning av hur kretsen ser ut utifrån gränssnittet, och Architecture hur den ser ut inuti.
63 VHDL BV.5a f f Programkod skrivs med teteditorer. Man kan därför ara göra tetkommentarer till koden. Ett typsnitt med fast redd används e. Courier Ne. 4 Kommentarer örjar med - Om man vill, kan man rita förtydligande ASCII-grafik inom kommentarraderna. Man rukar också indentera tetlock som hör ihop för ökad tydlighet Functions -- ->- -- ->- f ->- -- ->- f ->- -- -> William Sandqvist illiam@kth.se
64 VHDL BV.5a f f ENTITY Functions IS PORT,,, 4 :IN STD_LOGIC; f, f, :OUT STD_LOGIC END Functions ARCHITECTURE LogicFunc OF Functions IS BEGIN f < AND NOT OR AND NOT OR NOT AND NOT 4OR AND OR AND NOT 4; f < OR NOT AND OR OR NOT 4AND OR NOT OR NOT 4; END LogicFunc ; 4 William Sandqvist illiam@kth.se
65 VHDL BV 6. Using a selected signal assignement, rite VHDL code for a 4-to- inary encoder. Only one of is at a time. LIBRARY ieee; USE IEEE.std_logic_64.all; ENTITY ENCODER IS PORT :IN STD_LOGIC_VECTOR DOWNTO ; y :OUT STD_LOGIC_VECTOR DOWNTO ; END ENCODER ARCHITECTURE Behavior OF ENCODER IS BEGIN WITH SELECT y < WHEN, WHEN, WHEN, WHEN OTHERS; END Behavior ; William Sandqvist illiam@kth.se
66 William Sandqvist
67 Y Etrauppgift Realisera Y med ara grindar, och med grindar en 4: MUX William Sandqvist illiam@kth.se
68 Y Y Y William Sandqvist illiam@kth.se
69 Y ,, Y,, William Sandqvist illiam@kth.se
70 Y ,, Y - -,, William Sandqvist illiam@kth.se
71 Y Y Y - -, Y, Y - -, Y, Y William Sandqvist illiam@kth.se
72 Y Eller Y Y - -, Y, Y, Y - -, Y Eller om det är svårt att få tag i inverterad William Sandqvist illiam@kth.se
73 William Sandqvist
Shannon decomposition
Shannon decomposition Claude Shannon mathematician / electrical engineer 96 William Sandqvist illiam@kth.se E 8.6 Sho ho a 4-to- multipleer can e used as a "function generator" for eample to generate the
Shannon decomposition
Shannon decomposition Claude Shannon mathematician / electrical engineer 96 William Sandqvist illiam@kth.se E 8.6 Sho ho a 4-to- multipleer can e used as a "function generator" for eample to generate the
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