Shannon decomposition
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1 Shannon decomposition Claude Shannon mathematician / electrical engineer 96 William Sandqvist illiam@kth.se
2 E 8.6 Sho ho a 4-to- multipleer can e used as a "function generator" for eample to generate the OR function. William Sandqvist illiam@kth.se
3 E 8.6 Sho ho a 4-to- multipleer can e used as a "function generator" for eample to generate the OR function. Multipleer as function generator William Sandqvist illiam@kth.se
4 E 8.6 Sho ho a 4-to- multipleer can e used as a "function generator" for eample to generate the OR function. Multipleer as function generator William Sandqvist illiam@kth.se
5 William Sandqvist
6 BV 6. Sho ho the function f,, m,,, 4, 5, 7 can e implemented using a -to-8 decoder and an OR gate. William Sandqvist illiam@kth.se
7 BV 6. Sho ho the function f,, m,,, 4, 5, 7 can e implemented using a -to-8 decoder and an OR gate. William Sandqvist illiam@kth.se
8 William Sandqvist
9 E 8.7 A majority gate outputs the same value as the majority of the inputs. The gate can for eample e used in fault-tolerant logic, or in image processing circuits. a Set up the gate's truth tale and minimize the function ith Karnaugh map. Realize the function ith AND-OR gates. Realize the majority gate ith an 8: MUX. c Use Shannon decomposition and realize the majority gate ith a : MUX and gates. d Realize the majority gate ith only : MUXes. William Sandqvist illiam@kth.se
10 8.7a With AND OR gates William Sandqvist
11 8.7a With AND OR gates William Sandqvist
12 8.7a With AND OR gates M ac a c William Sandqvist illiam@kth.se
13 8.7a With AND OR gates M ac a c William Sandqvist illiam@kth.se
14 8.7 With 8-to- mu William Sandqvist
15 8.7 With 8-to- mu William Sandqvist
16 8.7c Shannon decomposition. -to- mu and gates. William Sandqvist
17 8.7c Shannon decomposition. -to- mu and gates. M a c ac ac ac a c a c c c William Sandqvist illiam@kth.se
18 8.7c Shannon decomposition. -to- mu and gates. M a c ac ac ac a c a c c c William Sandqvist illiam@kth.se
19 8.7c Shannon decomposition. -to- mu and gates. M a c ac ac ac a c a c c c OR William Sandqvist illiam@kth.se
20 8.7c Shannon decomposition. -to- mu and gates. M a c ac ac ac a c a c c c a c a c OR William Sandqvist illiam@kth.se
21 8.7c Shannon decomposition. -to- mu and gates. M a c ac ac ac a c a c c c a c a c OR William Sandqvist illiam@kth.se
22 8.7d Shannon decomposition. Only -to- mues. William Sandqvist
23 William Sandqvist 8.7d c c c c c c c h c c g c h c g c a c a M Shannon decomposition. Only -to- mues.
24 William Sandqvist 8.7d c c c c c c c h c c g c h c g c a c a M Shannon decomposition. Only -to- mues.
25 William Sandqvist 8.7d c c c c c c c h c c g c h c g c a c a M Shannon decomposition. Only -to- mues.
26 William Sandqvist
27 BV 6.5 For the function f,, m,,, 6 use Shannon s epansion to derive an implementation using a -to- multipleer and any necessary gates. William Sandqvist illiam@kth.se
28 BV 6.5 William Sandqvist For the function use Shannon s epansion to derive an implementation using a -to- multipleer and any necessary gates. 6,,,,, m f,,,,, m f
29 BV 6.5 William Sandqvist For the function use Shannon s epansion to derive an implementation using a -to- multipleer and any necessary gates. 6,,,,, m f,,,,, m f
30 BV 6.5 William Sandqvist For the function use Shannon s epansion to derive an implementation using a -to- multipleer and any necessary gates. 6,,,,, m f,,,,, m f
31 William Sandqvist
32 E 8.9 Sho ho one four-input eorgate XOR, odd parity function is realized in an FPGA circuit. Sho the contents of the SRAM cells LUT, Lookup Tale William Sandqvist
33 8.9 William Sandqvist
34 8.9 William Sandqvist
35 8.9 William Sandqvist
36 E 8.8 Set up full adder truth tale. Sho ho a full adder is implemented in an FPGA chip. Logic elements of an FPGA is ale to cascade COUT and CIN eteen "neighors." Sho the contents of the SRAM cells LUT, Lookup Tale. William Sandqvist illiam@kth.se
37 8.8 William Sandqvist
38 8.8 William Sandqvist
39 8.8 William Sandqvist
40 8.8 William Sandqvist
41 BV e 6. In digital systems it is often necessary to have circuits that can shift the its of a vector one or more it positions to the left or right. Design a circuit that can shift a four-it vector W one it position to the right hen a control signal Shift is equal to. Let the outputs of the circuit e a four-it vector Y y y y y and a signal k, such that if Shift then y, y, y, y, and k. If Shift then Y W and k. William Sandqvist illiam@kth.se
42 William Sandqvist
43 BV e 6. We uses MUXes: William Sandqvist illiam@kth.se
44 BV e 6. We uses MUXes: William Sandqvist illiam@kth.se
45 William Sandqvist
46 BV e. 6. Barrel shifter The shifter in Eample 6. shifts the its of an input vector y one it position to the right. It fills the vacated it on the left side ith. If the its that are shifted out are placed into the vacated position on the left, then the circuit effectively rotates the its of the input vector y a specified numer of it positions. Such a circuit is called a arrel shifter. Design a four-it arrel shifter that rotates the its y,,, or it positions as determined y the valuation of to control signals s and s. A arrelshifter is used to speed up floating point operations. William Sandqvist illiam@kth.se
47 Barrel shifter William Sandqvist
48 BV e. 6. Truth tale: William Sandqvist
49 BV e. 6. Truth tale: William Sandqvist
50 BV e. 6. Truth tale: William Sandqvist
51 BV e. 6. Truth tale: William Sandqvist
52 BV e. 6. Truth tale: William Sandqvist
53 BV e. 6. Truth tale: And so on... William Sandqvist
54 William Sandqvist
55 Locost FPGA Key Benefits Loest FPGA unit cost starting at $.49 Ultra-lo poer in Flash*Freeze mode, as lo as µw Nonvolatile FPGA eliminates unnecessary parts from BOM Single-chip and ultra-lo-poer products simplify oard design Variety of cost-optimized packages reduce assemly costs Lo-poer FPGAs reduce thermal management and cooling needs William Sandqvist
56 BV 6.6 Actel Corporation manufactures an FPGA family called Act, hich uses multipleer ased logic locks. Sho ho the function f can e implemented using only ACT logic locks. William Sandqvist illiam@kth.se
57 BV 6.6 f William Sandqvist illiam@kth.se
58 William Sandqvist BV 6.6 f f f
59 William Sandqvist BV 6.6 f f f
60 William Sandqvist BV 6.6 f f f
61 William Sandqvist
62 William Sandqvist VHDL BV.5a Write VHDL code to descrie the folloing functions f f VHDL code is ritten ith a tet editor and saved in a file ith the etension.vhd. The code alays consists of to sections ENTITY and ARCHITECTURE. Entity is a description of ho the circuit "looks from the outside" the interface, and Architecture ho it "looks like inside."
63 VHDL BV.5a f f Program code is ritten ith a tet editor. So e can only do tet comments to the code. A fied-idth font is used eg. Courier Ne. 4 Comments egin ith - If you ish, you can "dra" clarification ASCII graphics in the comment lines.. One usually indent tet locks that elong together for greater clarity Functions -- ->- -- ->- f ->- -- ->- f ->- -- -> William Sandqvist illiam@kth.se
64 VHDL BV.5a f f ENTITY Functions IS PORT,,, 4 :IN STD_LOGIC; f, f, :OUT STD_LOGIC END Functions ARCHITECTURE LogicFunc OF Functions IS BEGIN f < AND NOT OR AND NOT OR NOT AND NOT 4OR AND OR AND NOT 4; f < OR NOT AND OR OR NOT 4AND OR NOT OR NOT 4; END LogicFunc ; 4 William Sandqvist illiam@kth.se
65 VHDL BV 6. Using a selected signal assignement, rite VHDL code for a 4-to- inary encoder. Only one of is at a time. LIBRARY ieee; USE IEEE.std_logic_64.all; ENTITY ENCODER IS PORT :IN STD_LOGIC_VECTOR DOWNTO ; y :OUT STD_LOGIC_VECTOR DOWNTO ; END ENCODER ARCHITECTURE Behavior OF ENCODER IS BEGIN WITH SELECT y < WHEN, WHEN, WHEN, WHEN OTHERS; END Behavior ; William Sandqvist illiam@kth.se
66 William Sandqvist
67 Additional if time permits Y William Sandqvist illiam@kth.se
68 Y Y Y William Sandqvist illiam@kth.se
69 Y ,, Y,, William Sandqvist illiam@kth.se
70 Y ,, Y - -,, William Sandqvist illiam@kth.se
71 Y Y Y - -, Y, Y - -, Y, Y William Sandqvist illiam@kth.se
72 Y Or Y Y - -, Y, Y, Y - -, Y Or if you don t have acess to the variale inverted William Sandqvist illiam@kth.se
73 William Sandqvist
Shannon decomposition
Shannon decomposition Claude Shannon mathematician / electrical engineer 96 William Sandqvist illiam@kth.se E 8.6 Sho ho a 4-to- multipleer can e used as a "function generator" for eample to generate the
Shannon dekomposition
Shannon dekomposition Claude Shannon matematiker/elektrotekniker 96 William Sandqvist illiam@kth.se ÖH 8.6 Visa hur en 4-to- multipleor kan användas som funktionsgenerator för att te. Generera OR-funktionen.
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