Logic Effort Revisited


 Pearl Blake
 11 months ago
 Views:
Transcription
1 Logic Effort Revisited Mark This note ill take another look at logical effort, first revieing the asic idea ehind logical effort, and then looking at some of the more sutle issues in sizing transistors..0 Background As a starting point let s revie asic CMOS gate delay. We model the delay of a gate to e in the form: Td = Tparasitic + Tload * Cload/Cin (EQ ) We can get these parameters from any gate y measuring its delay vs. fanout, and finding the slope (Tload) and the intercept (Tparasitic). We can also get the parameters from using our RC model of a MOS transistor. In the terminology of logical effort, the first term is the parasitic delay, and the second term is the effort delay. We ill see that this effort delay is critical for sizing. Given a string of gates e ant to kno A B hat the optimal sizing is for these gates in a chain For a given numer of gates in a 64 chain, it is relatively easy to find the sizes. If e are looking for minimum delay, then it should not e possile to change any of the device sizes and decrease the delay. If I make gate B % larger, the increase in delay of gate A should match the decrease in the delay of gate B. In other ords changing Cload of Gate A y % should cause a delay change that is equal in magnitude to the delay change caused y increase Cin of gate B y %. Given (EQ ), this alance ill occur hen the effort delay of each gate is the same. The alancing of the effort delays for minimum delay is the main result of logical effort.. Logical Effort Rather than orking in ns, e generally ork in a normalize space. Since an inverter is generally the fastest gate one can uild, it is used as the ruler to measure other (more complex) gates. We define the logical effort of an inverter to e. The effort delay is then ritten as the product of three factors  a technology constant, the logical effort of the gate, and the electrical effort of the gate (hich is just the fanout Cload/Cin). The technology constant is just Tload for an inverter, and the logical effort is the ratio of Tload(gate)/ Tload(inv). This sets the technology constant to e the numer of picoseconds needed for. You should e careful aout finding optimal solutions  optimal for hat? This note is mostly interested in optimal timing, ut in most circuits you need to orry aout poer and area too. These other factors often set the transistor sizing
2 an inverter to drive an addition load equal to its input capacitance. I call the product of the electrical effort (fanout) and the logical effort the effective fanout of the gate. The logical effort of a gate is the slope of the delay vs. fanout for the gate, divided y the slope for an inverter. It is easy to estimate this numer using the simple RC model e used in EE27. Since delay of the gate is set y a sum of RC time constants, the effort delay comes from the term hich is the effective resistance of the gate driving the load capacitance. For CMOS gates the resistance is invery proportional to input capacitance, so the logical effort of a gate is: LE = C gate R gate C inv R inv (EQ 2) One can find the LE y either making the input capacitance of the gate equal to the inverter, and looking at the resistance ratio, or y making the resistance the same and looking at the capacitance ratio..2 Optimal Numer of Stages and Optimal Fanout Delay vs Fanout 6 5 Delay Delay a=.5 Delay a= Delay a=.5 Delay a= Fanout The question of the optimal fanout and numer of stages in a chain, is oth simple and a little tricky. This anser comes from solving the delay equation for a string of gates: Total delay = N * (f * Tload+Tparasitic) = ln(cl/cin) * Tload * (f + α) / ln(f) (EQ 3) here α is Tparasitic/Tload. From the delay plot, it does seem like 4 is the right anser, since it seems to make the delay close to the minimum. In addition, the curves are flat, so there is not a huge prolem ith using a range of fanouts eteen 2 and 8. So far this all seems to e revie. 2
3 No notice that (EQ 3) did not specify the logical effort of the gate. It turns out that the optimal fanout, here fanout is the electrical effort (Cload/Cin), for any string of homogeneous gates is around 4. So it ould seem at first glance e have a conflict. The theory of logical effort said e should make the effective fanout (fanout * LE) 4. The reason for this confusion is that life gets more interesting hen the gates are not all the same. With different gates you have a choice on ho you are going to drive your load. If the fanout per stage is too high, you could alays add an inverter to the chain to drive the load. When adding uffers, e alays think of using inverters since they are the fastest ay to drive fanout. So the optimization prolem e think aout hen sizing fanout is should I use this pile of gates to do my logic ith n stages, or should I add a uffer (or to) and do it in n+ (or 2) stages. Since the extra stages e are thinking aout are inverters, it is this element that should have a fanout of around 4 for optimal performance. With inverters having a fanout of 4, it means that the effort delay of all other gates should e around 4 as ell (they all have to e the same) and so the fanout of the logic gates ill e less than 4. Understanding that the optimal effective fanout is hen the est uffer element has a fanout of 4ish is important hen there are gates faster than inverters, as e ill see in section on domino logic. In domino logic, the effective fanout (LE * Cload/Cin) is around 3..3 Parasitic Delay The parasitic delay of a gate can e complicated to calculate, and can depend on hich input causes the output to transition. In general e don t need to calculate this preciy, ut you should kno that the parasitic delay of a gate gros more than linearly ith the numer of inputs. This is ecause the parasitic capacitance of parallel transistors gros linearly ith the numer of inputs (n transistors of the same size), hile the parasitic of series devices gros quadratically (n transistors, each n times larger). The large parasitic delay makes large fanin gates rarely useful. In general, gates ith more than 3 stacked devices are rarely used. 2.0 Using Logical Effort Logical effort is a very handy tool, ut there are some situations that ill still require some thought. The first prolem that arises in real designs is that the input and output capacitance are rarely given to you in a nice form so you can calculate logical effort. Even hen this information is availale there are often fixed ire capacitance that needs to e driven. All this makes formulating the prolem more difficult, ut not impossile. It just takes some reasonale approximations. Once the prolem is formed, you often find some circuits that don t fit nicely into the logical effort frameork, so I ill talk aout these next. The issues that I ill discuss are side loads, logical efforts for transmission gates, and dealing ith reconvergent fanout. Finally I ill take a quick look at using logical effort for dynamic gates. 3
4 2. Forming The Prolem In many design prolems the input or output capacitance is not knon, and you need to come up ith reasonale goals. In many situations focusing on the sizes that optimizes the delay is often not the correct strategy. If ire cap is present, the optimal sizing is alays to make the transistor sizes so large that the ire cap is a small fraction of the total. While this often a good idea, you generally stop hen the transistors are 6070% of the total, since the return on area and poer has gotten pretty poor. If you really like solving optimization prolems then you need to add poer or area constraints hen you set the prolem up. In some designs, hile the input and output capacitances are not kno, the fanout is knon. A multiplier is a good example of this situation. While it is possile that each ro of the multiplier ould have a different size, this ould e a pain to layout, so a etter design ould use all the same sizes. Often assuming the input and output capacitances are the same is a good starting point (you can drive as much as you load your inputs). This starting point is a good ase numer since it is easy to correct if you find out you need to drive a larger load (if the output is 4 times the input cap, the delay ill increase y one FO4 inverter). Lastly in many designs there are large ire capacitors that act as nice reaking points for the sizing prolems. While the optimal solution ould have the susequent gate size depend on the gate driving the large ire, as the next section ill sho, the gain is small, and the cost in poer and area is large. In general reaking the prolem at this point, and using a reasonale size for the susequent gate orks ell. 2.2 Fixed Side Loads In doing a sizing prolem, one often runs into a situation like shon in the figure here are to fixed loads that need to e driven, A and B that are x y separated y one or more gates. These loads could e from ire capacitance, or loading of noncritical gates. Although this prolem is hard to solve exactly, it is easy to solve approximately. The A B approximation starts y ignoring cap A and find the sizes for the gates if it did not exist. In this process if you need to add uffer stages to get the fanout correct, it is alays est to add them BEFORE cap A since this ill minimize its effect. Adding uffers efore A increases the cap of gate y hich ill make the side load relatively smaller in comparison. There are three cases that can arise: the cap of A can e much smaller, much larger or aout the same as gate y, In all scenarios the procedure is asically the same: add the cap of A to the load on gate x, and recalculate the fanout of the uffers efore the cap. Unless the numer of uffers in the prechain change, you are asically done. You could recalculate the FO of the uffers in the post chain, ut this has only a very small effect on the delay, and tends to make the post cap uffers much larger for small improvements in 4
5 delay. I ould recalculate the fanouts in gates after A only if I am going to remove a uffer in this chain, or I added one in the prechain. Let s look at each scenario in a little more detail. In all the case here cap A is small compared to the cap of gate y, the initial sizes are correct, and the prolem is solved. Since this is the minimum delay situation, it is good to try to get the side load further don a chain of gates here its effect ill e smaller. The other easy case is here A is much larger than the gate cap. In this case resolve the prolem assuming that A is the output. Once these sizes are found, the optimal y size is easy to find: x  A+ y = y = Bx x (EQ 4) Since y is small compared to A the interation converges quickly. Also notice that this is going to push the post chain to using small fanouts per stage, and increase the loading on the prechain. We can guess that this change in the output fanout ill have little effect on delay ecause the improvement in delay in going to lo fanout is small (the fixed parasitic loads really hurt), and this gain is partially offset y the large load on the prechain. The net result is that doing this optimization only slightly improves performance at the expense of area. When A is comparale to x the change in the fanouts in the prestage ill e small, since e amortize the change over a numer of stages. If they did not change at all ( x did not change) the fanout in the post stage ould e exactly correct, since y/x=b/y. Since x only changes slightly, e should not e surprised that its effect on the fanout of the post cap gates is small. Said a different ay, our method gets the change in fanouts from the fixed load approximately correct, so the change in delay to get it exactly correct is small. Just to demonstrate that finding the optimal delay is often not the right approach, I solved the for optimal delay for a chain of gates, hen each gate drives a fixed side load. You might guess that the optimal sizes have each of the gates e the same, ut that ould not e right. Since the delay decreases if the fixed load is small compared to the capacitance of the gate, the optimal sizes ramp up in the middle of the chain and then ramp them ack don (making the fanout less than ) The curves are for different numers in the chain, and the y axis is the size of the gate relative to The equation is not much more complicated hen there are chains of gates instead of the single gate x, since the fanout of all the gates in the chain remains the same 5
6 the fixed load. What is interesting is that the overall delay is only slightly etter than a chain here all the gates are the same size and roughly equal to the load capacitance. 2.3 Transmission Gates and other issues ith Gate sizing For all the gates that e have talked aout in class, e make the logical effort of all the inputs the same. This strategy is a good one, since if you try to improve the LE of one input, the LE of the other inputs gets much orse. But hat should you do aout transmission gates? First since e are interested in the effective resistance driving the load capacitance, e can only find the LE for a transmission gate hen it is used in some context. The LE needs to e found for the supergate it is in. No the question is ho to size the devices in the inverter and the TGate. Inv + TGate _ A A B NAND2 + TGate _ To start e need to kno hether e should consider and _ to different signals, or should e add the cap together. The anser is descried in more detail in the next section, and turns out that the logical effort of a splitter (creates A and A_) is only slightly greater than one. So the logic effort should e considered y only looking at the input. No ho do e ant the logical Inv + TGate NAND2 + Tgate efforts to turn out? If the ect signal 2 _ is critical e ould ant to make the 2 _ LE of this signal small, and let the LE A for the inverter or NAND gate gro A larger. This is exactly hat happens if B e make the resistance of the TGate LE A=2 LE A = 8/3 2 equal to the resistance of the inverter. LE Sel=2/3 LE Sel = 2/3 What is happening is that the TGate doules the resistance of the gate ithout changing the input capacitance. To get equal logical efforts, the resistance of the transmission gate must e Inv + TGate NAND2 + Tgate 2 _ made much smaller than the resistance 2 3 _ of the inverter. Since the resistance of A 3 4 the supergate is the same for oth A inputs, to get equal logical efforts, e B make the input capacitance the same. LE A=4/3 LE A = 5/3 2 This makes the transistors in the LE Sel=4/3 LE Sel = 5/3 TGate 3 for the inverter, and the LE of the oth A and Sel 4/3. Oviously you can set the LE of the input at any point in 6
7 eteen these points. The est LE depends on hich of the inputs is critical. I don t think it ould make sense to go outside these to points, since oth are getting a little inefficient in terms of making use of the transistor idth consumed. 2.4 Reconvergent Fanout (phase splitting) Sizing gets a little more complex hen e end up ith a situation like the one shon in the figure. There are to paths from the gate to gate. The path through a is longer, ut the other path requires more fanout per stage. This prolem is called reconvergent fanout. a Some 2input gate It turns out that the short path is the one you ant to consider hile computing gain per stage in a reconvergent fanout prolem ecause a heavy load on the short path ill also increase the delay of the long path. Let the input have unit of cap and the final gate have a size of times the input. What e ant to kno is hat is the effective logical effort of this comination of gates. That is ho does the delay of the path change as e change. Once e kno this, e can just use this effective logical effort hen e come across this situation and quickly find the fanouts at each stage. The critical path is clearly through inverter a, and the delay of this path is: t = (a+)/ + /a + 2* Tparasitic (EQ 5) Since the load on the first inverter is simply a side load for the prolem of sizing a, the size of a is just the geometric mean of gate and, hich is sqrt(). Thus the total delay of this path is t = Tparasitic dt d = (EQ 6) So the logical effort (the slope of the delay ith load) is not really a constant, ut for reasonale total effort (around 4), the fanout ould e around 2.5, and the effective logical effort is.6. This is a reasonale numer to use for stage efforts from 3 to 8. Actually this is not the est solution for this Some 2input gate prolem since e have not matched the delay x of the to paths. We have loaded the critical a path ith directly driving the large gate. This kind of prolem often occurs, and you can x speed up the circuit y duplicating some logic and splitting the critical path from the noncritical path. So hat e should have done is to split the first inverter into to inverters, here the sum of the inverter sizes is equal to. In this prolem, e have to find oth x and a hich minimize the total delay of the circuit. This is a little harder to solve, ut it is easy to rite the equations to solve. At the optimal point the delay of the to paths ill e the same, and a ill e the geometric mean of and (x). This gives 7
8 t =  + Tpar = 2 x Tpar x (EQ 7) It is easy to solve for as a function of x, so that is hat I did. Given x and, I can find the delay and this gives the plot shon elo Delay Delay no split The lue curves (ith diamonds) are the result of splitting the first inverter. If the inverter is not split (the first technique) you get the pink (squares) curves. The loer curves are the results you get if you ignore the parasitic delay, the upper curves are the results if the f loading is equal to its gate capacitance. Splitting the gate is alays etter than not splitting the gate. When the gate drive is split, the circuit ehaves like a single stage gate ith logical effort of aout (. if you ant to e precise) and a large effective parasitic delay (around 4). 2.5 Domino Gates Working ith domino gates is nearly the same as orking ith static gates. The one issue you need to e careful aout is setting the correct effective fanout per stage. For static gates the est uffer is an inverter, so the optimal effective fanout per stage is around 4. If the logical effort of a gate is larger than, the fanout of the stage should e reduced. In domino gates, the LE is often less than, so to make the effective fanout 4, the true fanout ould need to e greater than 4. This is not 2 correct, since in domino circuits there are etter uffers than inverters. The est uffer /2 ould look like a domino stage folloed y a skeed inverter. The logical effort for the inverter is 5/6, and the domino stage is somehere eteen /3 and 2/3 depending on the size of the clock transistor (let us assume 2/ 8
9 3). The LE for the to stages is.55, and the average LE per stage is If e used a chain of these gates and tried to find the est fan out per stage, the anser ould e that each stage should have an electrical fanout of aout 4, (actually 4.4 for dynamic stage and 3.6 for the static gate). At this fanout, the effective fanout (LE * Fanout) of the domino gate is 3, not 4. Thus in dynamic circuits you should aim for smaller effective fanout per stage than for static logic, hich makes the electrical fanout more similar to hat you ould do ith static gates. 9
EE M216A.:. Fall Lecture 5. Logical Effort. Prof. Dejan Marković
EE M26A.:. Fall 200 Lecture 5 Logical Effort Prof. Dejan Marković ee26a@gmail.com Logical Effort Recap Normalized delay d = g h + p g is the logical effort of the gate g = C IN /C INV Inverter is sized
More informationBusiness Cycles: The Classical Approach
San Francisco State University ECON 302 Business Cycles: The Classical Approach Introduction Michael Bar Recall from the introduction that the output per capita in the U.S. is groing steady, but there
More informationSpiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp
27.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 27.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance
More informationConsider this problem. A person s utility function depends on consumption and leisure. Of his market time (the complement to leisure), h t
VI. INEQUALITY CONSTRAINED OPTIMIZATION Application of the KuhnTucker conditions to inequality constrained optimization problems is another very, very important skill to your career as an economist. If
More informationLecture 6: Logical Effort
Lecture 6: Logical Effort Outline Logical Effort Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary Introduction Chip designers face a bewildering array
More informationStatic CMOS Circuits. Example 1
Static CMOS Circuits Conventional (ratioless) static CMOS Covered so far Ratioed logic (depletion load, pseudo nmos) Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0,
More informationLecture 8: Combinational Circuits
Introduction to CMOS VLSI Design Lecture 8: Combinational Circuits David Harris Harvey Mudd College Spring 004 Outline ubble Pushing Compound Gates Logical Effort Example Input Ordering symmetric Gates
More information7. Combinational Circuits
7. Combinational Circuits Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 September 25, 2017 ECE Department, University of Texas
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationInterconnects. Introduction
Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 Krish Chakrabarty 1 Introduction Chips are mostly made of ires called interconnect In stick diagram,
More informationEE371  Advanced VLSI Circuit Design
EE371  Advanced VLSI Circuit Design Midterm Examination May 1999 Name: No. Points Score 1. 20 2. 24 3. 26 4. 20 TOTAL / 90 In recognition of and in the spirit of the Stanford University Honor Code, I
More informationPEDS2009. Index Terms leakage inductance, magneto motive force (MMF), finite element analysis (FEA), interleaving, half turn, planar transformer
PEDS9 The Analysis and Comparison of Leakage Inductance in Different Winding Arrangements for Planar Transformer Ziei Ouyang, Ole C. Thomsen, Michael A. E. Andersen Department of Electrical Engineering,
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. MadianVLSI Contents Delay estimation Simple RC model PenfieldRubenstein Model Logical effort Delay
More informationMinimize Cost of Materials
Question 1: Ho do you find the optimal dimensions of a product? The size and shape of a product influences its functionality as ell as the cost to construct the product. If the dimensions of a product
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationEE115C Digital Electronic Circuits Homework #5
EE115C Digital Electronic Circuits Homework #5 Due Thursday, May 13, 6pm @ 56147E EIV Problem 1 Elmore Delay Analysis Calculate the Elmore delay from node A to node B using the values for the resistors
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationChapter 9. Estimating circuit speed. 9.1 Counting gate delays
Chapter 9 Estimating circuit speed 9.1 Counting gate delays The simplest method for estimating the speed of a VLSI circuit is to count the number of VLSI logic gates that the input signals must propagate
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #9 EECS141 PROBLEM 1: TIMING Consider the simple state machine shown
More informationEE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
More informationLecture 6: TimeDependent Behaviour of Digital Circuits
Lecture 6: TimeDependent Behaviour of Digital Circuits Two rather different quasiphysical models of an inverter gate were discussed in the previous lecture. The first one was a simple delay model. This
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
More information3  Vector Spaces Definition vector space linear space u, v,
3  Vector Spaces Vectors in R and R 3 are essentially matrices. They can be vieed either as column vectors (matrices of size and 3, respectively) or ro vectors ( and 3 matrices). The addition and scalar
More informationNbit Parity Neural Networks with minimum number of threshold neurons
Open Eng. 2016; 6:309 313 Research Article Open Access Marat Z. Arslanov*, Zhazira E. Amirgalieva, and Chingiz A. Kenshimov Nbit Parity Neural Netorks ith minimum number of threshold neurons DOI 10.1515/eng20160037
More informationThe following document was developed by Learning Materials Production, OTEN, DET.
NOTE CAREFULLY The following document was developed y Learning Materials Production, OTEN, DET. This material does not contain any 3 rd party copyright items. Consequently, you may use this material in
More informationDC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575604 yrpeng@uark.edu Pass Transistors We have assumed source is
More informationCMPEN 411 VLSI Digital Circuits Spring Lecture 14: Designing for Low Power
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 14: Designing for Low Power [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp12 CMPEN
More informationIntroduction to CMOS VLSI Design. Lecture 5: Logical Effort. David Harris. Harvey Mudd College Spring Outline
Introduction to CMOS VLSI Design Lecture 5: Logical Effort David Harris Harve Mudd College Spring 00 Outline Introduction Dela in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages
More informationInterconnect (2) Buffering Techniques. Logical Effort
Interconnect (2) Buffering Techniques. Logical Effort Lecture 14 18322 Fall 2002 Textbook: [Sections 4.2.1, 8.2.3] A few announcements! M1 is almost over: The checkoff is due today (by 9:30PM) Students
More informationAlgebra II Solutions
202 High School Math Contest 6 Algebra II Eam 2 LenoirRhyne University Donald and Helen Schort School of Mathematics and Computing Sciences Algebra II Solutions This eam has been prepared by the folloing
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.
More informationSimulation of Logic Primitives and Dynamic Dlatch with VerilogXL
Simulation of Logic Primitives and Dynamic Dlatch with VerilogXL November 30, 2011 Robert D Angelo Tufts University Electrical and Computer Engineering EE103 Lab 3: Part I&II Professor: Dr. Valencia
More informationand sinθ = cosb =, and we know a and b are acute angles, find cos( a+ b) Trigonometry Topics Accuplacer Review revised July 2016 sin.
Trigonometry Topics Accuplacer Revie revised July 0 You ill not be alloed to use a calculator on the Accuplacer Trigonometry test For more information, see the JCCC Testing Services ebsite at http://jcccedu/testing/
More informationVapor Pressure Prediction for StackedChip Packages in Reflow by ConvectionDiffusion Model
Vapor Pressure Prediction for StackedChip Packages in Reflo by ConvectionDiffusion Model Jeremy Adams, Liangbiao Chen, and Xuejun Fan Lamar University, PO Box 10028, Beaumont, TX 77710, USA Tel: 4098807792;
More informationLecture 3 Frequency Moments, Heavy Hitters
COMS E69989: Algorithmic Techniques for Massive Data Sep 15, 2015 Lecture 3 Frequency Moments, Heavy Hitters Instructor: Alex Andoni Scribes: Daniel Alabi, Wangda Zhang 1 Introduction This lecture is
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Digital Logic
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 Topic Notes: Digital Logic Our goal for the next few weeks is to paint a a reasonably complete picture of how we can go from transistor
More information5. CMOS Gate Characteristics CS755
5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor
More informationEE 330 Lecture 6. Improved SwitchLevel Model Propagation Delay Stick Diagrams Technology Files  Design Rules
EE 330 Lecture 6 Improved witchlevel Model Propagation elay tick iagrams Technology Files  esign Rules Review from Last Time MO Transistor Qualitative iscussion of nchannel Operation Bulk ource Gate
More informationFor smaller NRE cost For faster time to market For smaller highvolume manufacturing cost For higher performance
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS5 J. Wawrzynek Spring 22 2/22/2. [2 pts] Short Answers. Midterm Exam I a) [2 pts]
More informationCMOS Transistors, Gates, and Wires
CMOS Transistors, Gates, and Wires Should the hardware abstraction layers make today s lecture irrelevant? pplication R P C W / R W C W / 6.375 Complex Digital Systems Christopher atten February 5, 006
More informationCPE/EE 427, CPE 527 VLSI Design I L18: Circuit Families. Outline
CPE/EE 47, CPE 57 VLI Design I L8: Circuit Families Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe5705f
More informationSteam injection into watersaturated porous rock
Computational and Applied Mathematics Vol. 22, N. 3, pp. 359 395, 2003 Copyright 2003 SBMAC.scielo.r/cam Steam injection into atersaturated porous rock J. BRUINING 1, D. MARCHESIN 2 and C.J. VAN DUIJN
More informationEEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture. Rajeevan Amirtharajah University of California, Davis
EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture Rajeevan Amirtharajah University of California, Davis Outline Announcements Review: PDP, EDP, Intersignal Correlations, Glitching, Top
More informationName: Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 205 Midterm Wednesday, November 4 Point values
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationInterconnect (2) Buffering Techniques.Transmission Lines. Lecture Fall 2003
Interconnect (2) Buffering Techniques.Transmission Lines Lecture 12 18322 Fall 2003 A few announcements Partners Lab Due Times Midterm 1 is nearly here Date: 10/14/02, time: 3:004:20PM, place: in class
More informationDELAYS IN ASIC DESIGN
DELAYS IN ASIC DESIGN We encounter several types of delays in ASIC design. They are as follows: Gate delay or Intrinsic delay Net delay or Interconnect delay or Wire delay or Extrinsic delay or Flight
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationLecture 5. MOS Inverter: Switching Characteristics and Interconnection Effects
Lecture 5 MOS Inverter: Switching Characteristics and Interconnection Effects Introduction C load = (C gd,n + C gd,p + C db,n + C db,p ) + (C int + C g ) Lumped linear capacitance intrinsic cap. extrinsic
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay
More informationBuffer Insertion for Noise and Delay Optimization
Buffer Insertion for Noise and Delay Optimization Charles J Alpert IBM Austin esearch Laoratory Austin, TX 78660 alpert@austinimcom Anirudh Devgan IBM Austin esearch Laoratory Austin, TX 78660 devgan@austinimcom
More informationLECTURE 28. Analyzing digital computation at a very low level! The Latch Pipelined Datapath Control Signals Concept of State
Today LECTURE 28 Analyzing digital computation at a very low level! The Latch Pipelined Datapath Control Signals Concept of State Time permitting, RC circuits (where we intentionally put in resistance
More informationHightoLow Propagation Delay t PHL
HightoLow Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (nchannel) immediately switches from cutoff to saturation; the pchannel pullup switches from triode to
More informationMMSE Equalizer Design
MMSE Equalizer Design Phil Schniter March 6, 2008 [k] a[m] P a [k] g[k] m[k] h[k] + ṽ[k] q[k] y [k] P y[m] For a trivial channel (i.e., h[k] = δ[k]), e kno that the use of squareroot raisedcosine (SRRC)
More informationEE141Fall 2010 Digital Integrated Circuits. Announcements. An Intel Microprocessor. BitSliced Design. Class Material. Last lecture.
EE4Fall 2 Digital Integrated ircuits dders Lecture 2 dders 4 4 nnouncements Midterm 2: Thurs. Nov. 4 th, 6:38:pm Exam starts at 6:3pm sharp Review session: Wed., Nov. 3 rd, 6pm n Intel Microprocessor
More informationPhysics 220: Worksheet 7
(1 A resistor R 1 =10 is connected in series with a resistor R 2 =100. A current I=0.1 A is present through the circuit. What is the power radiated in each resistor and also in the total circuit? (2 A
More informationIntroduction to Algorithms
Lecture 1 Introduction to Algorithms 1.1 Overview The purpose of this lecture is to give a brief overview of the topic of Algorithms and the kind of thinking it involves: why we focus on the subjects that
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter
More informationVLSI Design Verification and Test Simulation CMPE 646. Specification. Design(netlist) Truevalue Simulator
Design Verification Simulation used for ) design verification: verify the correctness of the design and 2) test verification. Design verification: Response analysis Specification Design(netlist) Critical
More informationChapter 2.  DC Biasing  BJTs
Chapter 2.  DC Biasing  BJTs Objectives To Understand : Concept of Operating point and stability Analyzing Various biasing circuits and their comparison with respect to stability BJT A Review Invented
More informationLecture 1: Gate Delay Models
High Speed CMOS VLSI Design Lecture 1: Gate Delay Models (c) 1997 David Harris 1.0 Designing for Speed on the Back of an Envelope Custom IC design is all about speed. For a small amount of money, one synthesize
More information0 t < 0 1 t 1. u(t) =
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 13 p. 22/33 Step Response A unit step function is described by u(t) = ( 0 t < 0 1 t 1 While the waveform has an artificial jump (difficult
More informationDEVELOPMENT OF DOUBLE MATCHING LAYER FOR ULTRASONIC POWER TRANSDUCER
DEVELOPMENT OF DOUBLE MATCHIN LAYE FO ULTASONIC POWE TANSDUCE unn Hang, WooSub Youm and Sung Q Lee ETI, Nano Convergence Sensor esearch Section, 8 ajeongro, Yuseonggu, Daejeon, 349, South Korea email:
More informationDesign for Manufacturability and Power Estimation. Physical issues verification (DSM)
Design for Manufacturability and Power Estimation Lecture 25 Alessandra Nardi Thanks to Prof. Jan Rabaey and Prof. K. Keutzer Physical issues verification (DSM) Interconnects Signal Integrity P/G integrity
More informationLecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Outline Power and Energy Dynamic Power Static Power 6.2 Power and Energy Power is drawn from a voltage source attached to the V DD
More informationTestability. Shaahin Hessabi. Sharif University of Technology. Adapted from the presentation prepared by book authors.
Testability Lecture 6: Logic Simulation Shaahin Hessabi Department of Computer Engineering Sharif University of Technology Adapted from the presentation prepared by book authors Slide 1 of 27 Outline What
More informationDC & Transient Responses
ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = > = When = > = In between, depends on transistor size and current
More informationSection 8.5. z(t) = be ix(t). (8.5.1) Figure A pendulum. ż = ibẋe ix (8.5.2) (8.5.3) = ( bẋ 2 cos(x) bẍ sin(x)) + i( bẋ 2 sin(x) + bẍ cos(x)).
Difference Equations to Differential Equations Section 8.5 Applications: Pendulums MassSpring Systems In this section we will investigate two applications of our work in Section 8.4. First, we will consider
More informationSignals & Systems  Chapter 6
Signals & Systems  Chapter 6 S. A realvalued signal x( is knon to be uniquely determined by its samples hen the sampling frequeny is s = 0,000π. For hat values of is (j) guaranteed to be zero? From the
More informationVI. Transistor amplifiers: Biasing and Small Signal Model
VI. Transistor amplifiers: iasing and Small Signal Model 6.1 Introduction Transistor amplifiers utilizing JT or FET are similar in design and analysis. Accordingly we will discuss JT amplifiers thoroughly.
More informationLinear Discriminant Functions
Linear Discriminant Functions Linear discriminant functions and decision surfaces Definition It is a function that is a linear combination of the components of g() = t + 0 () here is the eight vector and
More informationCHAPTER 5. Linear Operators, Span, Linear Independence, Basis Sets, and Dimension
A SERIES OF CLASS NOTES TO INTRODUCE LINEAR AND NONLINEAR PROBLEMS TO ENGINEERS, SCIENTISTS, AND APPLIED MATHEMATICIANS LINEAR CLASS NOTES: A COLLECTION OF HANDOUTS FOR REVIEW AND PREVIEW OF LINEAR THEORY
More informationy(x) = x w + ε(x), (1)
Linear regression We are ready to consider our first machinelearning problem: linear regression. Suppose that e are interested in the values of a function y(x): R d R, here x is a ddimensional vectorvalued
More informationBased on slides/material by. Topic 34. Combinational Logic. Outline. The CMOS Inverter: A First Glance
ased on slides/material by Topic 3 J. Rabaey http://bwrc.eecs.berkeley.edu/lasses/icook/instructors.html Digital Integrated ircuits: Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html
More information1 Slutsky Matrix og Negative deniteness
Slutsky Matrix og Negative deniteness This is exercise 2.F. from the book. Given the demand function x(p,) from the book page 23, here β = and =, e shall :. Calculate the Slutsky matrix S = D p x(p, )
More informationEE141 Fall 2002 Lecture 27. Memory EE141. Announcements. We finished all the labs No homework this week Projects are due next Tuesday 9am EE141
 Fall 2002 Lecture 27 Memory Announcements We finished all the labs No homework this week Projects are due next Tuesday 9am 1 Today s Lecture Memory:» SRAM» DRAM» Flash Memory 2 Floatinggate transistor
More informationWeak bidders prefer firstprice (sealedbid) auctions. (This holds both exante, and once the bidders have learned their types)
Econ 805 Advanced Micro Theory I Dan Quint Fall 2007 Lecture 9 Oct 4 2007 Last week, we egan relaxing the assumptions of the symmetric independent private values model. We examined privatevalue auctions
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis  Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationCHAPTER 4: DYNAMICS: FORCE AND NEWTON S LAWS OF MOTION
CHAPTE 4: DYNAMICS: FOCE AND NEWTON S LAWS OF MOTION 4. NEWTON S SECOND LAW OF MOTION: CONCEPT OF A SYSTEM. A 6. kg sprinter starts a race ith an acceleration of external force on him? 4. m/s. What is
More informationComputer organization
Computer organization Levels of abstraction Assembler Simulator Applications C C++ Java Highlevel language SOFTWARE add lw ori Assembly language Goal 0000 0001 0000 1001 0101 Machine instructions/data
More informationE40M. RC Circuits and Impedance. M. Horowitz, J. Plummer, R. Howe
E40M RC Circuits and Impedance Reading Reader: Chapter 6 Capacitance (if you haven t read it yet) Section 7.3 Impedance You should skip all the parts about inductors We will talk about them in a lecture
More informationLecture 25. Semiconductor Memories. Issues in Memory
Lecture 25 Semiconductor Memories Issues in Memory Memory Classification Memory Architectures TheMemoryCore Periphery 1 Semiconductor Memory Classification RWM NVRWM ROM Random Access NonRandom Access
More informationCMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,
More informationChapter 1: Logic systems
Chapter 1: Logic systems 1: Logic gates Learning Objectives: At the end of this topic you should be able to: identify the symbols and truth tables for the following logic gates: NOT AND NAND OR NOR XOR
More information1 Reductions and Expressiveness
15451/651: Design & Analysis of Algorithms November 3, 2015 Lecture #17 last changed: October 30, 2015 In the past few lectures we have looked at increasingly more expressive problems solvable using efficient
More informationLinear models: the perceptron and closest centroid algorithms. D = {(x i,y i )} n i=1. x i 2 R d 9/3/13. Preliminaries. Chapter 1, 7.
Preliminaries Linear models: the perceptron and closest centroid algorithms Chapter 1, 7 Definition: The Euclidean dot product beteen to vectors is the expression d T x = i x i The dot product is also
More information5. TWODIMENSIONAL FLOW OF WATER THROUGH SOILS 5.1 INTRODUCTION
5. TWODIMENSIONAL FLOW OF WATER TROUG SOILS 5.1 INTRODUCTION In many instances the flo of ater through soils is neither onedimensional nor uniform over the area perpendicular to flo. It is often necessary
More informationTHE MUCKENHOUPT A CLASS AS A METRIC SPACE AND CONTINUITY OF WEIGHTED ESTIMATES. Nikolaos Pattakos and Alexander Volberg
Math. Res. Lett. 9 (202), no. 02, 499 50 c International Press 202 THE MUCKENHOUPT A CLASS AS A METRIC SPACE AND CONTINUITY OF WEIGHTED ESTIMATES Nikolaos Pattakos and Alexander Volberg Abstract. We sho
More information. Divide common fractions: 12 a. = a b. = a b b. = ac b c. 10. State that x 3 means x x x, . Cancel common factors in a fraction : 2a2 b 3.
Page 1 of 6 Target audience: Someone who understands the previous Overview chapters and can comfortaly: 2. Divide common fractions: 3 4 5 = 2 3 5 4 = 10 12 a = a 1 c c = a = ac c 1. Find common denominators:
More informationVLSI Circuit Design (EEC0056) Exam
Mestrado Integrado em Engenharia Eletrotécnica e de omputadores VLSI ircuit esign (EE0056) Exam 205/6 4 th year, 2 nd sem. uration: 2:30 Open notes Note: The test has 5 questions for 200 points. Show all
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full railtorail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power
More informationEE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania
1 EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS 2 > ESD PROTECTION CIRCUITS (INPUT PADS) > ONCHIP CLOCK GENERATION & DISTRIBUTION > OUTPUT PADS > ONCHIP NOISE DUE TO PARASITIC INDUCTANCE > SUPER BUFFER
More informationNTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register
NTE74HC165 Integrated Circuit TTL High Speed CMOS, 8 Bit Parallel In/Serial Out Shift Register Description: The NTE74HC165 is an 8 bit parallel in/serial out shift register in a 16 Lead DIP type package
More informationA statistical analysis of the influence of vertical and ground speed errors on conflict probe
A statistical analysis of the influence of vertical and ground speed errors on conflict probe JeanMarc Alliot Nicolas urand Géraud Granger CENA CENA CENA Keyords: air traffic control, conflict probe,
More information