CHAPTER VI COMBINATIONAL LOGIC BUILDING BLOCKS

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1 CHAPTR VI- CHAPTR VI CHAPTR VI BUILDING BLOCKS R.M. Dansereau; v..

2 CHAPTR VI- COMBINAT. LOGIC INTRODUCTION -INTRODUCTION Combinational logic Output at any time is determined completely by the current input. We will later consider circuits where the output is determined by the input and the current state (memory) of the system. In this chapter we will consider some useful building blocks that can be pieced together and used in larger designs. This will include: Multiplexers (selectors) and demultiplexers (distributors) ncoders, priority encoders, decoders Adders (full and half) Parity generators and parity checkers Shifters and rotators Comparators R.M. Dansereau; v..

3 CHAPTR VI- DCODRS BASIC DCODR -INTRODUCTION Standard decoder is an n-to-m-line decoder, where m n. xample: -to-8-line decoder A A -to-8 Decoder D D D D D 4 D 5 D 6 D 7 xample: Input of -to-8 Decoder All outputs are low except for the one corresponding to the binary D m value of the input An AA. R.M. Dansereau; v..

4 CHAPTR VI-4 DCODRS DCODRS WITH NABL DCODRS -BASIC DCODR Often, combinational logic building blocks will also have an enable line that turns on outputs or leaves them off. -to-8 Decoder with nable A A Module nable -to-8 Decoder D D D D D 4 D 5 D 6 D 7 R.M. Dansereau; v..

5 R.M. Dansereau; v.. INTRO. TO COMP. NG. CHAPTR VI-5 DCODRS TRUTH TABLS DCODRS -BASIC DCODR -WITH NABL Truth table for a -to-8-line decoder: D D D 4 D D D 5 D 6 D 7 Outputs Inputs A A

6 CHAPTR VI-6 DCODRS IMPLMNTATION DCODRS -BASIC DCODR -WITH NABL -TRUTH TABLS How can a decoder be implemented? Fill in the circuit! A A D 7 D 6 D 5 D 4 D D D D A A A A A A A A A A A A A A A A R.M. Dansereau; v..

7 CHAPTR VI-7 DCODRS DSIGNING WITH DCODRS DCODRS -WITH NABL -TRUTH TABLS -IMPLMNTATION Any Boolean function can implemented using a decoder and OR gates by ORing together the function s minterms. Inputs A A Outputs F F A F 7 -to-8 Decoder F R.M. Dansereau; v..

8 CHAPTR VI-8 DCODRS DCODR NTWORKS DCODRS -TRUTH TABLS -IMPLMNTATION -DSIGNING W/DCODRS We can also use multiple decoders to form a larger decoder. -to-8 Decoder Implemented with two -to-4 Decoders used with enable input to control which decoder will output the. A A -to-4 Decoder D D D D A and A used to select which output on specific decoder will output. -to-4 Decoder D 4 D 5 D 6 D 7 R.M. Dansereau; v..

9 CHAPTR VI-9 NCODRS BASIC NCODR DCODRS -IMPLMNTATION -DSIGNING W/DCODRS -DCODR NTWORKS Standard binary encoder is an m-to-n-line encoder, where m n. xample: 8-to--line encoder Module nable D D D D D 4 D 5 D 6 D to- ncoder Ac A A xample: Input of to- ncoder Module Active R.M. Dansereau; v..

10 R.M. Dansereau; v.. INTRO. TO COMP. NG. CHAPTR VI- NCODRS NCODR TRUTH TABL DCODRS NCODRS -BASIC NCODR Truth table for an 8-to--line encoder: Assumed that only one input is. What happens if more then one is? D D D 4 D D D 5 D 6 D 7 Outputs Inputs A A

11 CHAPTR VI- NCODRS DSIGNING WITH NCODRS DCODRS NCODRS -BASIC NCODR -TRUTH TABL ncoders are useful when the occurrence of one of several disjoint events needs to be represented by an integer identifying the event. xample: Wind direction encoder N NW N W 4 SW S 5 S to- ncoder R.M. Dansereau; v.. pp of rcegovac, Lang and Moreno, Introduction to Digital Systems, 999.

12 CHAPTR VI- NCODRS PRIORITY NCODRS NCODRS -BASIC NCODR -TRUTH TABL -DSIGN W/ NCODRS A priority encoder takes the input of with the highest index and translates that index to the output. Inputs Outputs D 7 D 6 D 5 D 4 D D D D A A R.M. Dansereau; v..

13 CHAPTR VI- NCODRS DSIGN WITH P-NCODR NCODRS -TRUTH TABL -DSIGN W/ NCODRS -PRIORITY NCODRS Priority encoders are useful when inputs have a predefined priority and we wish to select the input with the highest priority. xample: Resolving interrupt requests Device A Device B Device C Device D Request Lines Lowest Priority Highest Priority -to-4 Priority ncoder Ac Processor pp of rcegovac, Lang and Moreno, Introduction to Digital Systems, 999. R.M. Dansereau; v..

14 CHAPTR VI-4 MULTIPLRS BASIC MULTIPLR (MU) NCODRS -DSIGN W/ NCODRS -PRIORITY NCODRS -DSIGN W/ P-NCODRS Selects one of many inputs to be directed to an output. A A A Module nable 4x Multiplexer S S Y f Y A A A Inputs Output F A = A = = A = A = A = = A = R.M. Dansereau; v..

15 CHAPTR VI-5 MULTIPLRS USING PASS GATS NCODRS MULTIPLRS -BASIC MULTIPLR The 4x mux can be implemented with pass gates as follows. Y A A Out (f) A Only one of A n gets passed to output. Depends on the value of and Y. R.M. Dansereau; v..

16 CHAPTR VI-6 MULTIPLRS DSIGN WITH MULTIPLRS NCODRS MULTIPLRS -BASIC MULTIPLR -USING PASS GATS Any Boolean function can be implemented by setting the inputs corresponding to the function and the selectors as the variables. xample: Y Z F Module nable x Multiplexer S S Y S Z f R.M. Dansereau; v..

17 CHAPTR VI-7 DMULTIPLRS BASIC DMULTIPLR MULTIPLRS -BASIC MULTIPLR -USING PASS GATS -DSIGN W/ MULTIPL. Takes one input and selects one of many outputs to direct the input. W Module nable x4 Demultiplexer S S Y D D D D Inputs Y W D D D D Outputs W= W= W= W= W= W= W= W= R.M. Dansereau; v..

18 CHAPTR VI-8 DMULTIPLRS DSIGN W/ DMULTIPLRS MULTIPLRS DMULTIPLRS -BASIC DMULTIPLR A demultiplexer is useful for routing an input to a desired location. xample: Input Data x4 Demultiplexer Processing Unit Processing Unit Processing Unit S S Processing Unit Selects which PU to send the input data. Y R.M. Dansereau; v..

19 CHAPTR VI- ADDRS HALF- AND FULL-ADDRS DMULTIPLRS SHIFTRS ROTATORS -BASIC ROTATOR Two basic building blocks for arithmetic are half- and full-adders as depicted by the block diagrams below. A B A B C OUT Carry-out HA C OUT Carry-out FA C IN Carry-in S Sum S Sum Half-adder Full-adder R.M. Dansereau; v..

20 CHAPTR VI- ADDRS HALF-ADDR (HA) SHIFTRS ROTATORS ADDRS -HALF- & FULL-ADDRS First of all, how do we add? s complement arithmetic allows us to add numbers normally. Inputs A B Sum Carry-out S = AB+ AB = A B S C OUT A B C OUT = AB S C OUT R.M. Dansereau; v..

21 CHAPTR VI-4 ADDRS FULL-ADDR (FA) () ROTATORS ADDRS -HALF- & FULL-ADDRS -HALF-ADDR (HA) Half-adder missed a possible carry-in. A full-adder (FA) includes this additional carry-in. Inputs Carry-in Sum Carry-out A B C IN S C OUT S = ( A B) C IN C OUT = AB + C IN ( A B) R.M. Dansereau; v..

22 CHAPTR VI-5 ADDRS FULL-ADDR (FA) () ADDRS -HALF- & FULL-ADDRS -HALF-ADDR (HA) -FULL-ADDR (FA) Half-adder S = ( A B) C IN C OUT = AB + C IN ( A B) Half-adder A B S C OUT C IN R.M. Dansereau; v..

23 CHAPTR VI-6 ADDRS BINARY ADDITION ADDRS -HALF- & FULL-ADDRS -HALF-ADDR (HA) -FULL-ADDR (FA) A 4-bit binary adder can be formed with four full-adders as follows. A B B A B A B FA C FA C FA C FA C S S S S C 4 R.M. Dansereau; v..

24 CHAPTR VI-7 COMPARATORS MAGNITUD COMPARATOR ADDRS -HALF-ADDR (HA) -FULL-ADDR (FA) -BINARY ADDITION Given two n-bit magnitudes, A and B, a comparator indicates whether A = B, A > B, or A < B n-bit input magnitudes Cascaded input values from other comparators n A n B Results of comparisons Greater qual Less c in G c in c in L 4-Bit Comparator G Greater (A > B) qual (A = B) L Less (A < B) R.M. Dansereau; v..

25 CHAPTR VI-8 COMPARATORS MAGNITUD COMPARATOR ADDRS COMPARATORS -MAG. COMPARATOR The approach is to use the NOR function (equivalence) on each of the n- bits as follows x i = A i B i + A i B I = A i B i The Boolean functions for a 4-bit magnitude comparator is as follows ( A = B) = x x x x ( A> B) = A B + x B + x x A B + x x x A B ( A< B) = A B + x B + x x A B + x x x A B Note: A i B i indicates whether A i > B i, A i B i indicates whether A i < B i, and x i indicates whether A i = B i. R.M. Dansereau; v..

CHAPTER VI COMBINATIONAL LOGIC BUILDING BLOCKS

CHAPTER VI COMBINATIONAL LOGIC BUILDING BLOCKS CHAPTR VI- CHAPTR VI CHAPTR VI BUILDING BLOCKS R.M. Dansereau; v.. CHAPTR VI- COMBINAT. LOGIC INTRODUCTION -INTRODUCTION Combinational logic Output at any time is determined completely by the current input.