Analysis and Implementation of Charge Recycling for Deep Sub-micron Buses

Transcription

1 Aalysis ad Implemetatio of Charge Recyclig for Deep Sub-micro Buses Paul P. Sotiriadis heodoros Kostatakopoulos Aatha Chadrakasa Departmet of EECS Massachusetts Ist. of echology Departmet of EECS Massachusetts Ist. of echology Departmet of EECS Massachusetts Ist. of echology ABSRAC : Charge recyclig has bee proposed as a strategy to reduce the power dissipatio i data buses. Previous work i this area was based o simplified bus models that igored the couplig betwee the lies. Here we propose a ew Charge Recyclig echique (CR appropriate for sub-micro techologies. CR is aalyzed mathematically usig a bus eergy model that captures the eergy loss due to strog lie to lie capacitive couplig. I theory CR ca result to eergy reductio of a factor of. It becomes eve more eergy efficiet whe combied with Bus Ivert codig (Sta, []. A circuit has bee desiged ad simulated with all parasitic elemets extracted from the layout. akig ito accout the circuit eergy overhead the et result i eergy savig ca be up to %.. IRODUCIO Over the past several years, sigificat emphasis has bee placed o reducig the eergy dissipatio associated with o chip commuicatio. umerous schemes have bee preseted for reducig eergy associated with drivig wires icludig low swig sigalig [],[],[], charge re-cyclig [],[] ad data codig [],[],[]. I this paper we itroduce a ew practical Charge Recyclig echique (CR appropriate for sub-micro techology buses. Its performace is verified by both mathematical aalysis ad circuit implemetatio. he techique, based o charge recyclig betwee the lies, cosists of two steps. Durig the first step, charge redistributio takes place betwee the lies whose logical values are chagig durig the trasitio. All other lies remai coected to their drivers. Durig the secod step, all lies are drive to the voltages correspodig to their ew logical values. A similar techique was preseted i [] ad [] but for the case where there is o couplig betwee the lies. his differece is very essetial. I sub-micro techology the strog capacitive couplig betwee the lies must be take ito accout sice it dramatically chages the eergy cosumptio durig bus trasitios (with or without the CR. For this purpose we use a sub-micro bus eergy equivalet model preseted i []. I this paper we also preset a driver to implemet CR. Its operatio is demostrated o a -lie ad a -lie bus usig HSPICE. he driver works at 00MHz ad results to a et eergy savig of up to %. he circuit is directly expadable to larger buses. Large buses of or lies ad FPGA itercoect etworks are expected to have higher et eergy savigs with CR (Rabaey []. Stadard.µ CMOS techology has bee used. lie lie lie lie. SUB-MICRO BUS MODEL he sub-micro bus eergy model we use to evaluate the differet eergies is show i Figure. It has bee prove i [] that this model has idetical eergy behavior to its distributed versio. is the capacitace betwee each lie ad the groud ad is the capacitace betwee adjacet lies. (he capacitace betwee o-adjacet lies is very weak ad ca be igored. We defie the techology depedet parameter λ =. For.µ techology, λ is about. Also, λ teds to icrease with techology scalig. o simplify the theoretical aalysis we set =. he all eergies calculated uder this assumptio must be multiplied by the factor to give the real eergy value. V V V V. BUS DRIVER MODEL he drivers are modeled as i Figure, []. he resistors ad R i correspod to the PMOS ad MOS trasistors of the drivers. heir values ca be almost arbitrary fuctios of time. he switches s i ad s i are complemetary ad their status correspods to the desirable values of the lies. he parasitic capacitaces of the drivers outputs ca be lumped ito.. CHARGE RECYCLIG I this sectio we preset the two steps of CR. Suppose the bus has lies ad let be the clock cycle period. ew data is tras- Figure : Sub-micro eergy-equivalet Bus Model P R i Permissio to make digital or hard copies of all or part of this work for persoal or classroom use is grated without fee provided that copies are ot made or distributed for profit or commercial advatage ad that copies bear this otice ad the full citatio o the first page. o copy otherwise, or republish, to post o servers or to redistribute to lists, requires prior specific permissio ad/or a fee. ISLPED'0, August -, 00, Hutigto Beach, Califoria, USA. Copyright 00 ACM ---/0/000...$.00. i-th driver : = s i s i P R i R i Figure : Bus Driver Model lie i

2 Lies have settled to their itermediate values st Step 0 It It mitted through the bus every secods. he time iterval [ 0, ] is divided ito the subitervals It ad It. he two steps of CR are timely related as i Figure. Suppose that durig the clock cycle the bus trasitios from its curret values, x = [ x, x,, ], to its ew values, y = [ y, y y ] ( x i, y i correspod to lie i. ormalizig by =, the all x i ad y i belog to { 0, }. he voltages of the lies as fuctios of time t [ 0, ] are deoted by V = [ V, V,, V ]. At t = 0 ad t = it is V( 0 = x ad V ( = y respectively. he CR is preseted i Figure with the modified drivig circuit. We agree that switch w i has value 0 if ode i is coected to the output of driver i, ad value if ode i is coected to the commo ode q. Durig It the lies that chage logical values (durig the trasitio x y are coected to ode q ad ot to their drivers. he lies retaiig their logical values remai coected to their drivers. (his is a major differece to the strategy i []. If there is couplig betwee the lies it makes a differece if the o-chagig lies remai coected to their drivers or ot durig the charge redistributio. Durig It all lies are coected to their drivers.. FirstStep(It d Step Figure : imig of CR Lies have settled to their fial values For every lie i = we set d i = x i y i. We also use the vector d = x y where d = [ d, d d ] ad the diagoal (q V 0 t R P w w w I I I Figure : Example (= matrix, D = diag( d, d d ( Durig the trasitio, lie i chages value if ad oly if d i =. Accordig to CR, durig the time iterval It = ( 0, ] the lies with chagig values are coected to ode q ad therefore the i-th switch must have the value w i = d i = x i y i. he etwork is cofigured respectively. For example let =, x = [ 00,,, ] ad y = [ 00,,, ]. he d = [ 00,,, ] ad durig It the etwork is cofigured as i Figure. Durig It the dyamics of the etwork satisfies the set of differetial equatios (see Figure, (q R V V V V 0 w I I = V + ( V V I k = ( V k V k + V + ( V k V k +, < k< I = V + ( V V V ( If we defie the currets vector I = [ I, I I ] ad the capacitace coductace matrix [] of the etwork i Figure, w w w w I I I I V V V V C = + λ λ 0 0 λ + λ λ : 0 0 λ : : : : : + λ λ 0 0 λ + λ the, equatios ( ca be writte i the compact form, C V ow ote that for i = the curret is draw from the driver if d i = 0 ad from the ode q if d i =. he charge co- = I ( ( Figure : CR - etwork coectios

3 servatio at ode q implies that form, = 0, or i vector I = 0 ( Replacig ( ito ( we get C V = 0 which itegrated over the time iterval It = ( 0, ] of step gives, V( 0 = x = [ x, x,, ] are the iitial coditios of the lies ad V -- ( = [ V, V,, V ] are the itermediate oes. Here we assume that the time legth is sufficiet for the voltages of the etwork to settle. his assumptio is reasoable for the curret techology ad is always used i charge redistributio (ad adiabatic techiques. So for i = the voltage V -- i ( is either x if or if i d i = 0 z V q d i =. he value z is of course the same for all lies that chage logical value. Algebraically we have that V i = ( d i x i + d i z or i vector form that, V( -- = ( I D x+ z d ( where s the idetity matrix. he matrix D ad the vector d are as defied before. From (, ( ad V( 0 = x we have, ( C d z = C D x ( ow ote that matrix is positive defiite. his implies that the quatity ( C d is positive if ad oly if ( d 0 or equivaletly, if ad oly if at least oe lie chage value durig the trasitio x y. If there is o chage durig the trasitio the the eergy dissipated durig the trasitio is zero. For ow we assume that at least oe lie chages value. he from ( we get,. Eergy Dissipatio o Step Here we evaluate the eergy that is draw from o the first step of CR. he curret draw from durig ( It is the sum of the currets draw by the lies that do ot chage logical value durig the trasitio ad remai coected to through their drivers, i.e the lies i = for which x i = y i =. So, writte i matrix form as, i : d i = C ( V( -- V( 0 = 0 C z = = V o C D x C d = = x i ( d i I i i : x i = ad y i = i = = x ( I D It ( ( ( which ca be (0 (Symbol s used for both the curret vector ad the idetity matrix. Is should be clear what I represets each time. Usig equatio ( ad (0 we have that, Because of the ormalizatio ( the eergy draw from durig step is E = dt. By replacig ( i the itegral we have we use ( to get, E = x ( I D C ( V( -- V( 0. Fially Ad by replacig z from ( ito ( we have, E ( x, y x C D x = ( I D C d C d if d 0 ad E = 0 if d = 0.. Secod Step (It ( ( Durig the secod step of the CR, the time iterval It = (, ], every lie is coected to its driver (with the ew value y i. So for all i =,, it is w i = 0. For the example with =, x = [ 00,,, ] ad y = [ 00,,, ], the etwork is cofigured as i Figure. Equatio ( holds durig the secod step as well.. Eergy Dissipatio o Step Durig the curret draw from equals the sum of the currets of the lies coected to (through their drivers. So = x ( I D C V 0 = E = x ( I D C ( z d D x w R w w V V V D x or i vector form,

4 Replacig ( ito ( we get, = y It ( = y C V ( ( he eergy draw from o step is E = dt. Replacemet of ( ito the itegral gives, E = y C ( V ( V( -- Fially, V ( = y, ( ad ( imply, E ( x, y y = C y ( I D x. EERGY PROPERIES OF CR C D x C d ( ( he total eergy Exy (, draw from durig the trasitio x y is of course Exy (, = E ( x, y + E ( xy,. Usig the idetity ( I D x = ( I D y ad expressios ( ad ( we get, ( where z is give by (. he first term of the right part of ( equals the eergy draw from by the bus durig the trasitio x y whe o charge recyclig is applied []. he other terms correspod to the eergy differece (savigs due to CR. For a better ituitio o how CR iflueces the bus eergy trasitio patters, table presets the case of a three lie bus = whe λ =. Five is a represetative value of λ for the case of.µ techologies (with miimal distace betwee the wires. For simplicity we set = =. ( x, x, x with CR ( y, y, y without CR d Exy (, = y C ( y x + y D C ( D x z d able : rasitio eergies with ad without the CR 00% % 0. 0% 0. % 0. 0% 0. 0% 0 = For each trasitio ( x, x, x ( y, y, y the shadowed value (below is the eergy cost without CR, equal to y C ( y x. he umbers o the white backgroud (above are the eergies with CR, i.e. to the values give by (. he eergy with CR is always smaller. Also, the highest percetage of eergy reductio occurs i the most expesive trasitios 00 0 ad 0 00 where adjacet lies trasit i the opposite directio ad the iterlie capacitaces are charged by.. EERGY REDUCIO he result for the trasitio eergy, formula (, allows us to estimate umerically the expected eergy draw by the bus whe the CR is used. We do this for the case of uiformly distributed i.i.d. data. I Figure we see the expected eergy usig CR as a percetage of the expected eergy without CR for the cases of =,,,,,,, ad λ = 00,,.hefiguresuggests that for the umber of lies =,,, the eergy draw from ca be reduced to oe half usig CR. Also, the results are idepedet of the capacitace to groud ad they slightly improve whe λ icreases. I geeral λ teds to icrease with techology scalig.. CR AD BUS-IVER Series λ = 0 Series λ = Series λ = 0 Figure : Eergy with CR / Eergy without CR I the previous sectios we showed how CR reduces eergy cosumptio. I Figure we preset a architecture where CR is combied with Bus-Ivert codig []. iputs u u : : u Bus Ivert Codig + lies x x : ck ( Charge Recyclig Drivig etwork Exteded Bus + lies Figure : Combiatio of CR with Bus Ivert codig he Bus Ivert codig works i the followig way. Let uk ( = [ u, u u ] be the ew iput vector ad xk ( = [ x, x ] be the ew vector of the values of the :

5 00% Series λ = 0 % 0. Series λ = Series λ = 0 0% 0. % 0. 0% 0. 0% 0 = Figure : Eergy with CR ad Bus Ivert / Eergy without them lies. If the vector uk ( xk ( cotais more tha oes the we set xk ( = uk ( ad ck ( =, otherwise we set xk ( = uk ( ad ck ( = 0. he combied performace of CR ad Bus Ivert is show i Figure. We see a small improvemet compared to the results of Figure. For buses with lies or more the eergy savig is more tha 0%.. A CIRCUI FOR CR DRIVERS o verify CR we desiged a circuit that implemets the coceptual etwork of Figure. Our circuit implemetatio cosisted of the bus ad the CR drivers of the lies. he CR driver detects the trasitio of the lie ad coects it either to the commo ode (qortoitsregulardriver(chaiofiverters.heproposed CR driver was desiged ad laid out i.µ techology ad its schematic is show i Figure 0. Usig this driver we tested CR for a -lie ad a -lie bus. he layout of both the CR ad the stadard drivers for the two cases are show i Figure. he CR driver operates as follows. he switches w, w, i Figure are realized here by the pair of trasmissio gates. lie i commo ode (q lie i+ Figure : Layout of the CR drivers he charge recyclig phase begis whe CLK becomes. A egative spike appears at the output of the XOR gate if the iput x i chages value. his sets the latch ad coects the lie to the commo ode q through the trasmissio gate. he charge recyclig phase eds whe CLK becomes 0. his resets the latch, isolates the lie from the commo ode (q ad coects it to the buffer chai. If the iput x i does ot make a trasitio, the latch remais reset durig the whole clock cycle ad the lie remais coected to the buffer chai. he same circuit ca be used uchaged for buses with arbitrary umber of lies.. SIMULAIO AD RESULS CR drivers of Figure 0 were used to drive the lies of a four ad a eight lie bus, =, =. A etlist was extracted from the layout of the drivers for the simulatio with HSPICE. he lies were modeled as i Figure ad for the capacitor we used the values 0fF, 00fF, 0fF ad 00fF. ote that these values could represet ot oly the lie capacitors but all the loads as well. his is particularly the case of recofigurable itercoect etworks (e.g. i FPGAs where log buses are loaded by the parasitic capacitaces of several mosfets resultig to total capacitive loads of the size of a few picofarads []. he clock frequecy i the simulatios was set to 00Mhz ad the buses were fed with uiformly distributed i.i.d. sequeces of data. I w i w w i i + w i + w i w w i i + w i + pj lie bus lie bus without CR pj without CR with CR x i x i + Figure 0: Efficiet CR - Driver i ff with CR Figure : Average eergy per cycle of a ad lie buses with ad without CR i ff

6 % theoretical boud 0. lie bus 0. liebus i ff Figure : ormalized eergy usig CR (HSPICE simulatio Figure we see the average eergy per cycle of the four lie bus (left ad the eight lie bus (right. he curves i the graphs showig higher eergy cosumptio correspod to the stadard buses. he curves showig lower cosumptio correspod to buses with CR drivers. I Figure we see the average eergy usig CR as a percetage of the average eergy without CR for the -lie ad -lie buses. Agai, the ratios are parametrized to. he flat lies correspod to the miimum possible ratios resultig from the theoretical aalysis ad show i Figure. As it should be expected, for higher capacitive loads we get higher percetages of eergy savig. his is because the average eergy per cycle of the additioal circuitry of the drivers is relatively idepedet of the loads. For larger loads this additioal eergy becomes less sigificat. Fially, it is iterestig to look at the waveforms of the idividual lies durig the two steps of the CR. Figure shows the waveforms of the lie voltages of the -lie bus. I this particular case, oe lie experieces a 0 trasitio ad the rest three lies make a 0 trasitio. Sice all lies trasit they are all coected first to the commo ode q. he fial voltage at ode q durig the charge redistributio period is of course z (equatio ( ad correspod to the covergig poit of the waveforms at time = s. It is iterestig to ote that for a idividual trasitio the maximum eergy savig with CR occurs whe all lies trasitio ad Voltage. 0. clock lie voltages durig charge sharig 00 % theoretical boud i ff lie voltages approachig their fial values time e(s Figure : Lie voltage waveforms durig the two steps of CR adjacet lies trasitio i opposite directios. his geeralizes to the fact that CR preforms very well whe the sequeces of the trasitios of adjacet lies are egatively correlated. 0. COCLUSIOS A Charge Recyclig echique (CR for sub-micro buses has bee proposed ad aalyzed. Closed form results for the trasitio eergy have bee give ad used for the theoretical evaluatio of the eergy reductio with CR. Reductio of the average trasitio eergy by a factor of more tha ca result i theory by the applicatio of both CR ad Bus Ivert codig. A lie driver has bee desiged to implemet CR. Usig it i a -lie bus we have demostrated et eergy savigs of up to %. Larger buses of or lies are expected to have higher eergy savigs. Ackowledgemets he authors ackowledge support from the MARCO Focus Research Ceter o Itercoect which is fuded at the Massachusetts Istitute of echology, through a subcotract from the Georgia Istitute of echology. Paul Sotiriadis is partially supported by the Alexader S. Oassis Public Beefit Foudatio, the Greek Sectio of Scholarships ad Research. Refereces [] H. Zhag, J. Rabaey, Low swig itercoect iterface circuits, IEEE/ACM Iteratioal Symposium o Low Power Electroics ad Desig, pp. -, August. [] Y.akagome,K.Itoh,M.Isoda,K.akeuchi,M.Aoki, Sub--V swig iteral bus architecture for future lowpower ULSI s, IEEE Joural of Solid-State Circuits, pp. -, April. [] H. Yamauchi, H. Akamatsu,. Fujita, A asymptotically zero power charge-recyclig bus architecture for batteryoperated ultrahigh data rate ULSI's, Joural of Solid-State Circuits, IEEE, Vol. 0 Issue:, pp. -, April. [] K.Y. Khoo, A. Willso, Jr., Charge recovery o a databus, IEEE/ACM Iteratioal Symposium o Low Power Electroics ad Desig, pp. -,. [] B. Bishop, M. J. Irwi, Databus charge recovery: Practical cosideratio, Iteratioal Symposium o Low Power Electroics ad Desig, pp. -, August. [] M. Sta, W. Burleso, Low-power ecodigs for global commuicatio i cmos VLSI, IEEE rasactios o VLSI Systems, pp. -, Vol., o., Dec.. [] P. Sotiriadis, A. Wag, A. Chadrakasa, rasitio Patter Codig: A approach to reduce Eergy i Itercoect, ESSCIRC 000. [] S. Ramprasad,. Shabhag, I. Hajj, A codig framework for low-power address ad data busses, IEEE rasactios o VLSI Systems, pp. -, Vol., o., Jue. [] J.M. Rabaey, Digital Itegrated circuits. Pretice Hall. [0] H.B. Bakoglou, Circuits, Itercoectios, ad Packagig i VLSI. Addiso-Wesley Pub. Co., 0 [] E. Kusse, J. Rabaey, Low-Eergy Embedded FPGA Structures, ISLPED. August Moterey USA.