Analysis of MOS Capacitor Loaded Annular Ring MICROSTRIP Antenna

Transcription

1 Iteratioal OPEN AESS Joural Of Moder Egieerig Research (IJMER Aalysis of MOS apacitor Loaded Aular Rig MIROSTRIP Atea Mohit Kumar, Suredra Kumar, Devedra Kumar 3, Ravi Kumar 4,, 3, 4 (Assistat Professor, Shri Ram Murti Smarak Womes ollege of Egieerig ad Techology Bareilly (U.P. Abstract: I this paper a ew techique is proposed for achievig icreased frequecy agility by loadig the patch atea with a MOS capacitor. Theoretical ivestigatios have bee carried out for the MOS capacitor loaded Aular Rig microstrip atea, for oxide thickesses from A to 5 A, to predict the achievable rage of operatioal badwidth. I spite of umerous advatages, the simple patch atea has a low operatioal badwidth, which limits its applicability. Hece this techique of MOS capacitor loaded Aular Rig microstrip patch atea is to improve the operatig frequecy rage. I. Itroductio The cocept of microstrip radiator was first proposed by Deschamps as 953. As show i Fig a microstrip atea i its simplest cofiguratio cosists of a radiatig patch o oe side of a dielectric substrate ( r, which has a groud plae o the other side. The patch coductor s steps are geerally used to simplify aalysis ad performace predictio. Ideally the dielectric costat r of the substrate should be low ( r.5, so as to ehace the frigig fields which accout for the radiatio. However, other performace requiremets may dictate the use of substrate materials whose dielectric costats may be greater tha 5. Various types of substrates havig a large of dielectric costats ad loss tagets have bee developed. Flexible substrates are also available which make it possible to fabricate simple coformal ateas. Fig Rectagular Microstrip Atea II. Aalysis of Aular Rig Microstrip Atea A Microstrip patch atea (MPA cosist of a coductig patch of ay plaer geometry of oe side of a dielectric substrate backed by a groud plae o other side. The cavity model for the aular microstrip aalysis is based o E walls ad H walls boudary coditios. avity model for the aular rig microstrip atea is show ad its aalysis for the aular microstrip atea is based o the followig observatios. The close proximity betwee the aular patch ad groud plae suggests that E has oly z compoet ad H oly x-y compoets i the regio bouded by the microstrip ad the groud plae. The fields i the above metioed regio are idepedet of the z co-ordiates for all frequecies of iterest. The electric curret i the microstrip must have o compoet ormal to the edge at poit o the edge.. Fields ad urret: With o curret sources the wave equatio may be writte as, E K Where, k is a wave umber give by, k IJMER ISSN: Vol. 4 Iss. 5 May. 4 56

2 Aalysis of MOS apacitor Loaded Aular Rig Microstrip Atea The field must be solved by the wave equatio ad the magetic wall boudary coditios. Sice, E Z E z, E a ad E b Thus the solutio of the wave equatio i the cylidrical; co-ordiates is E E ( ( ( ( cos j k Y ka j k Y k z E E. Resoat Frequecy: The resoat frequecy ca be calculated by takig accout the effect of frigig field f c k r Here c is the velocity of light ad r the relative dielectric costat.3 Effective Ier ad Outer Radii & Effective Dielectric ostat: To accout the frigig field effects alog the curved edges of the rig it is ecessary to replace the radius a ad b by their effective values, a eff, b eff ad eff ca be calculate as follows h ( ( eff r r ( w Now the resoat wave umber k is the m zero of the trascedetal equatio j ( a k Y ( b k j ( b k Y ( a k e e e e for the TM mode the solutio of the above equatio is give by 5.975ae k ( b a ( 7. 8a b e e e e After solvig the characteristic equatio for k, the resoat frequecy ca be determied from c f k eff It should be poited out that the correctio to the resoat frequecy formula ivolves both the effective permittivity ad the effective radii..4 Iput Impedace: Equivalet circuit is effective to desig for this type of atea because of its simplicity ad ease of uderstadig the physical pheomeo. It is a G-L-G lumped elemet resoator circuit. Usig the mode expasio theory, the iput impedace of the AR-MSA ca be obtaied. The iput impedace from the feed lie ca be expressed as a parallel resoator, Z i j Lt m jc j G L Where, L, ad G are equivalet circuit parameters icludig losses correspodig to each mode. III. Aalysis of Aular Micro strip Atea with MOS apacitor Loaded 3. Mos apacitor: A MOS capacitor of MIS (metal± isulator± semicoductor diode is a voltage variable capacitor. A typical MOS capacitor structure for the proposed aalysis is Au± Si3N4± Si, show i The capacitace is depedet o the oxide thickess, which is evidetly clear from. a d Mos capacitace IJMER ISSN: Vol. 4 Iss. 5 May. 4 57

3 Aalysis of MOS apacitor Loaded Aular Rig Microstrip Atea mos A Vg qna The capacitace of the depletio d per uit area Vg. qna The ratio of o decreases with the gate potetial accordace with the above expressio, ad reaches a miimum value whe iversio layer is formed. 3. Mos apacitor Loaded Aular Rig Microstrip Atea Equivalet circuit for MOS loaded aular rig microstrip atea is show below Fig Equivalet circuit for MOS Loaded aular rig microstrip atea The patch performace will be affected due to its radiatig edge capacitace i additio to the capacitace provided due to the MOS capacitor Uder such coditios the total capacitace will be total MOS SA SB Where a a l (.4.77 t ( SA r r h a b b l (.4.77 t ( SB r r h b Thus the resoace frequecy for the modified mode will be f r ( LEQtotal EQ IV. omputatio of Various Parameters 4. Reflectio coefficiet: It is defied as the ratio of the reflected voltage or curret to the icidet voltage or curret ad is usually deoted by ρ. Reflectio coefficiet is a vector quatity havig magitude ad directio as well. I terms of impedace it ca be expressed as Z Z i Z Z i 4. Voltage stadig wave ratio: It is defied as ratio of maximum to miimum voltage o a lie havig stadig waves ad this ratio is observed as VSWR= 4.3 Iput impedace of the patch: Whe we cosider oly the aular rig patch, tha the iput impedace will be R+iX Z i IJMER ISSN: Vol. 4 Iss. 5 May. 4 58

4 Aalysis of MOS apacitor Loaded Aular Rig Microstrip Atea 4.4 Quality factor: It is a measure of ay selectivity of a resoat or ati resoat curret ad is expressed as Q=ωWP W=Maximum stored eergy P=average power loss Fig 3 Iput Impedace vs Frequecy for differet feed poits Fig 4 VSWR vs Frequecy Fig 5 Retur Loss vs Frequecy Voltage Fig 6 MOS apacitace vs Bias Fig 7 Resoatig Frequecy vs Bias Voltage Fig 8 Iput Impedace vs Frequecy for MOS Loaded ARMSA V. oclusio This paper has described a aalysis of the behavior of Mos capacitor loaded aular rig microstrip atea. Results have bee preseted for resoat frequecies ad radiatio patters. After loadig MOS capacitor o the atea the operatig frequecy ca be easily cotrolled. From above graphical aalysis it is observed that-. The variatio of MOS capacitace is similar for all the five oxide thickess. A larger variatio i capacitace is observed with bias voltage ear zero bias, but it is very small at higher bias.. The maximum frequecy agility of 57.8% is obtaied for miimum oxide thickess (A. However for maximum value of oxide thickess (5 A, the frequecy agility is aroud 38.48% (.96 GHz, IJMER ISSN: Vol. 4 Iss. 5 May. 4 59

5 Aalysis of MOS apacitor Loaded Aular Rig Microstrip Atea which is the lowest value. The frequecy agility obtaied with the MOS capacitor loaded atea (57.8 % is higher tha the varactor loaded patch ( 47.4 %. REFRENES [] I.J. Bhal ad P. Bhartia, Microstrip Atea, Dedham, MA : Arteh House, 98, [] Special issue o microstrip ateas, IEEE Tras. Ateas Propagatio, vol. AP- 9, Ja. 98. [3] I. J. Bhal, S. S. Stuchly, ad M. A.Stuchly, A ew microstrip radiator for medival applicatio, IEEE Tras Microwave Theory Tech., vol. MTT-8, pp , 98. [4] J. W. Mik, ircular rig microstrip atea elemets, preseted at 98 Ateas Propagat. Soc. It. Symp., P.Q, aada, Jue 98. [5] S. Ali, W.. hew, ad J. A. Kog, Vector Hakel trasform aalysis of aular rig microstrip atea, IEEE Tras. Atea Propagat., vol. AP-3 [6] W.. hew, A broad bad aular rig microstrip atea, IEEE Tras. Ateas Propagatio, vol. AP- 3, o. 5, pp. 98-9, Sept. 98. [7] J. S. Dahele ad K. D. Lee, haracteristics of aular rig microstrip atea, Electro. Lett., vol. 8, pp. 5-53, Nov.98. [8] L.. She, aalysis of a circular disc prited circuit atea, Proc. Ist. Elec, Eg., vol, 6,o. pp.-, Dec IJMER ISSN: Vol. 4 Iss. 5 May. 4 6