Minimum Source/Drain Area AS,AD = (0.48µm)(0.60µm) - (0.12µm)(0.12µm) = µm 2
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1 UNIERSITY OF CALIFORNIA College of Egieerig Departmet of Electrical Egieerig ad Computer Scieces Last modified o February 1 st, 005 by Chris Baer (crbaer@eecs Adrei ladimirescu Homewor #3 EECS141 Due Friday, February 11, Cory Problem 1 MOS Capacitace 1A First, fire up Cadece irtuoso with 0.4um techology. Place a miimum sized NMOS trasistor ad examie the dimesios. Determie ad list the followig: Miimum Trasistor Legth L 0.4µm Miimum Trasistor Width W 0.36µm Miimum Source/Drai Area AS,AD (0.48µm(0.60µm - (0.1µm(0.1µm 0.736µm Miimum Source/Drai Perimeter PS, PD (0.60µm 0.48µm 0.1µm 1.8µm 1B We desire a miimum sized CMOS iverter with a symmetrical TC (MDD/ with 0.4um techology. Calculate the followig for the pull-up PMOS trasistor i the desig with the NMOS trasistor miimum sized as i part a: Equatio 5.5: ( L ( W W AT M T p L ATp DD M Tp AT ATp Table 3. gives the values for AT, T, ad : AT AT M W T p W ATp ATp DD M Tp ( ( 0.63( ( ( 1(
2 Miimum Trasistor Legth L 0.4µm Miimum Trasistor Width W (0.36µm( µm Miimum Source/Drai Area AS,AD (1.5µm(0.60µm 0.75µm Miimum Source/Drai Perimeter PS, PD (0.60µm 1.5µm.45µm 1C After buildig your iverter you decide to test it out. You perform a trasiet simulatio of this iverter usig HSPICE ad you got the followig waveform: What causes the output to overshoot? What are the implicatios of this behavior (i.e. with respect to performace? The overshoot is caused by gate-drai capacitaces of the iverter trasistors; the capacitors couple the steep iput voltage to the output before the trasistors have a chace to pull up or dow. With respect to performace, these overshoots mae the propagatio delay through the gate loger. I additio, this behavior ca forward bias the drai-bul diodes, further deterioratig the trasistor operatio. 1D Suppose two of your iverters from above were cascaded together. Draw a schematic diagram of these iverters with explicit capacitors associated with the iverter. Igore wirig capacitace. For each capacitace, briefly describe where it comes from with respect to the MOS structure.
3 C gd1 C db1, C g3,4 Ideally the drai diffusios of each trasistor should ed right at the edge of the gate oxide, however, they ted to exted uder the oxide (lateral diffusio creatig a overlap. This is due to the reverse biased p-juctio. This is the capacitace due to the gate-source/drai overlaps ad chael charge 1E Calculate the total capacitace o the ode where the output of the first iverter coects to the iput of the secod iverter. Igore wirig capacitace ad use table 3-5. Perform this for both high-to-low ( DD - DD / ad low-to-high (0- DD /. Compare these fial values. First, we ll do the calculatios affected by applied voltage (for C db1 : m φ 1 1 m Keq high low ( ( ( m 0 φ ( 0 φ0 high low 1 m Note: use table 3.5 for m, Φ T, etc. NMOS Durig H L, high -.5, low -1.5; for L H, high -1.5, low 0 Bottom Plate (K eq Sidewall (K eqsw H L L H PMOS Durig H L, high -1.5, low 0; for L H, high -.5, low -1.5
4 Bottom Plate (K eq Sidewall (K eqsw H L L H Equatios from the boo (all values idepedet of applied voltage except C db : gd1 ( 0.31 ( gd p p ( 0.7 ( g3 ( ox ( ( ( ( ( C CGDOW f ff C CGDO W f ff C CGDO CGSO W C W L 0.31 f 0.31 f f ff ( C CGDO CGSO W C W L g4 p p p ox p p ( ( ( ( ( 0.7 f 0.7 f f ff H L Cdb 1 Keq ADCJ KeqswPDCJSW ( 0.57( 0.74( f ( 0.61( 1.8( 0.8 f 0.6 ff C K AD CJ K PD CJSW f f 1.59 ff db eqp p eqswp p ( ( ( ( ( ( L H Cdb 1 Keq ADCJ KeqswPDCJSW ( 0.79( 0.74( f ( 0.81( 1.8( 0.8 f 0.84 ff C K AD CJ K PD CJSW f f 1. ff db eqp p eqswp p Fially, we ca calculate the total capacitace: CH L ff C ff L H ( ( ( ( ( ( 1F Suppose you were tryig to speed up a set of iverters which exist i a complex etwor of gates. What could you do to speed this circuit up (i.e. reduce the propagatio delay from v 1 to v? Give advatages ad disadvatages of your proposal with respect to these iverters ad the circuit as a whole. Oe optio is to size the trasistors differetly; sizig the gate larger would icrease its drive capability, reducig its propagatio delay. The advatage of this approach its easy; the disadvatage is that it may affect the gate which drives v1 causig the path to slow dow as a whole. Other techiques might be to attempt to reduce the capacitace coectig the first iverter to the secod iverter via careful layout; aother techique might be to raise DD. Problem More Iverter Aalysis
5 Usig the same set of iverters from the last homewor, we re goig to perform additioal aalysis regardig the iverters relative performace ad M. A Briefly compare/cotrast these iverter styles with respect to the desig metrics discussed i lecture (area, oise margis, speed, power, etc.. A few seteces for each metric should be adequate. Area Iverter C liely cosumes the most area if a symmetric TC is assumed. Iverters A ad B areas will vary depedig o the choices made for the other metrics. Noise Margis Iverter C has better oise margis tha A ad B. Speed Iverter C will have more symmetric pull-up/dow delays; Iverters A ad B will have a fast pull-dow delay relative to the pull-up delay. Power Iverter C has the least power bur due to fact that while holdig a value there is oly oe path to groud or DD; the other iverters have static curret flow. B Derive a equatio showig the relatioship betwee M ad T. For each iverter, calculate M for T0 0.35, 0.45, 0.55 usig the W/L give below, ad table 3-. Iverter A Assume both devices are velocity saturated: AT AT GT AT p GT AT L Lp p ( 1 λ ( 1 λ M T AT M p p DD Tp AT DD M AT AT ( ( 1 λ ( ( 1 λ( W W All the values are ow except for M (usig math software: T ( M ( Iverter B
6 Agai, assume both devices are velocity saturated:. AT AT GT AT GT AT L L ( 1 λ ( 1 λ AT W ( M T AT ( 1 λm W AT ( 0 γ ( φ φ 1 λ( ( DD M T F M F AT DD M All the values are ow except for M (usig math software: T ( M ( Iverter C Agai, assume both devices are velocity saturated: AT AT GT AT p GT AT L Lp p ( 1 λ ( 1 λ M T AT M p p DD M Tp AT DD M AT AT ( ( 1 λ ( ( 1 λ( W W All the values are ow except for M (usig math software: T ( M ( C Now resize iverter C (usig W 0.50µm, L 0.50µm ad T to attai a M ( OH - OL /. Iverter C Sice the CMOS iverter has a full-rail swig, we ca use M DD/. Agai, set size of NMOS to be 0.50µm/0.50µm, solve for PMOS width:
7 AT AT GT AT p GT AT L Lp p ( 1 λ ( 1 λ DD AT DD DD AT DD W T AT 1 λ W p p Tp AT 1 λ W p /L p 1.5µm/0.50µm Problem 3 Iverter i Wea Iversio Regime (Subthreshold The iverter below, operates with DD0.4 ad is composed of t 0.5 devices. The devices have idetical I 0 ad but the chael modulatio costats are differet ad are those give i table 3. 3A Calculate the switchig threshold (M of this iverter. Both devices are i the subthreshold regio assumig 1.5 ad T/q 6m GS GS φt φt φt φt Ie 0 1 e 1 Ie 0 1 e 1 ( λ ( λp M M DD M DD M φt φt φt φt e 1 e 1 e 1 e 1 ( ( λ λ ( M p DD M Solvig this equatio usig a math solver: M 0.4 3B Calculate IL ad IH of the iverter. IH M M /g IL M ( DD - M /g From equatio 5.1: DD 1 φ T g e 1 g IH /( IL M ( DD - M /g 0.399
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