DATASHEETS FOR PARTS DIGITAL ELECTRONICS SYSTEM DESIGN NMOS I-V SUMMARY EXAM SCHEDULE 10/5/2018. cutoff V V. linear.
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1 //8 IGIT EECTRONICS SYSTEM ESIGN F 8 PROFS. IRIS HR & RO ERESFOR OCTOER, 8 ECTURE : CMOS TRNSIENT EHIOR TSHEETS FOR PRTS ll arts rovided for you i our kits come with datasheets Pi layout i ackage Schematic desig Secify oeratig coditios Provide descritio of how to oerate chi correctly to get desired outut The datasheets ca be dowloaded from the course webage (FullataSheets-ENGN.zi) Please feel free to refer to these datasheets to hel aswer some questios you have for the lab assigmets. EXM SCHEUE NMOS I- SUMMRY Two exams i the course that make u ~% of your grade You eed to get a assig grade o the exam ortio as well as the lab ortio to get a assig grade for the class Midterm: Wedesday, :-m Fial: Saturday, 9am-oo Shockley st order trasistor models gs t I ds ds gs t ds ds dsat gs t ds dsat W = Cox cutoff liear saturatio
2 //8 ONG CHNNE I- POT (NMOS) NMOS trasistor:.um techology, d = um, W/ =., =., T =. cut-off X - S = GS - T iear Saturatio GS =. GS =. GS =. GS =.... S () CMOS INERTER I- CURES PMOS X. - i = i =.. i =. i =. i =. NMOS i =. i =. i =. i =. i =. i = i =. i =. i =. i =. out () i =.... i =.um, W/ =., W/ =., =., T =., T = -. CMOS INERTER TC out ()... NMOS off PMOS res NMOS sat PMOS res... i () NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off Takig those itersectio oits from the load curves, we obtai the voltagetrasfer characteristic SWITCHING THRESHO efie M to be the oit where i = out (both PMOS ad NMOS i saturatio sice S = GS ) If M = /, the this imlies symmetric rise/fall behavior for the CMOS gate Recall at saturatio, I =(k /)(W/) ( GS - T ), where k = C ox = ox /t ox Settig I = -I ssumig T =- T k W ( M W / W / k W T) ( M k k ) T
3 //8 MOS STRUCTURE RESISTNCE The simlest model assumes the trasistor is a switch with a ifiite off resistace ad a fiite o resistace R o S GS T However R o is oliear, time-varyig, ad deedet o the oeratio oit of the trasistor How ca we determie a equivalet (costat ad liear) resistace to use istead? R o MOS STRUCTURE RESISTNCE roximate R o as the resistace foud durig liear oeratio Simle to calculate but limited accuracy Istead use the average value of the resistaces, R eq, at the ed-oits of the trasitio (i.e., ad /) Req ( Ro( t) Ro( t)) / I ST I ST I ST I R mid R... / GS = S EQUIENT MOS STRUCTURE RESISTNCE CMOS INERTER: YNMIC EHIOR Req I where C IST so, Req C R eqnmos ST ox ox W (, W W ( T) T) ST R ST eqpmos ST ST W 7 x (for GS =, S = /)... () out = Trasiet, or dyamic, resose determies the maximum seed at which a device ca be oerated. t H = f(, ) R eq is essetially ideedet of as log as >> T + ST / i =
4 //8 SOURCES OF CPCITNCE SOURCES OF CPCITNCE i out out i out out M C C G M M C C G M i C G out C w out i out out M C C G M M C C G M itrisic MOS trasistor caacitaces extrisic MOS trasistor (faout) caacitaces wirig (itercoect) caacitace C +C +C G +C G EY EFINITIONS iut waveform i % INERTER PROPGTION EY Proagatio delay roortioal to time-costat of etwork i out formed by ON resistor ad the load caacitace. Proagatio delay t = (t H + t H )/ t H = f(, ) out outut waveform t H t f % % t H t r t 9% sigal sloes t out = I R R C C C Wat to have equal rise/fall delays make = i =
5 //8 MOEING PROPGTION EY SWITCH EY MOE Model circuit as first-order RC etwork v i R C v out v out (t) = ( e t/ ) i where = RC Time to reach % oit is t = l() =.9 R eq C it t Time to reach 9% oit is t = l(9) =. ( t H t H ) /.9C ( R R ) / NN C it INERTER NOR INPUT PTTERN EFFECTS ON EY Cit elay is deedet o the atter of iuts st order aroximatio of delay: t.9 R eff R eff deeds o the iut atter INPUT PTTERN EFFECTS ON EY trasitio o outut: ossibilities oe iut goes low: what is R eff? delay is.9 both iuts go low: what is R eff? delay is.9 / sice -resistors o i arallel trasitio o outut: ossibility both iuts go high Cit delay is.9 t.9 R eff ddig trasistors i series (without sizig) slows dow the circuit
6 //8 TRNSISTOR SIZING TRNSISTOR SIZING COMPEX GTE How should NMOS ad PMOS devices be sized relative to a iverter with equal rise/fall times? Cit C it C 8 8 C OUT =!( + ( + C)) TRNSISTOR SIZING COMPEX GTE. C lterate sizig: size the shortest ath first C OUT =!( + ( + C))
MORE TUTORIALS FOR VERILOG DIGITAL ELECTRONICS SYSTEM DESIGN HOMEWORK ASSIGNMENTS DATASHEETS FOR PARTS 10/3/2018
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