Key Questions. ECE 340 Lecture 36 : MOSFET II 4/28/14

Transcription

1 Thigs you should kow whe you leae C 40 Lecture 6 : MOSFT Class Outlie: Short Chael ffects Key Questios Why is the mobility i the chael lower tha i the bulk? Why do strog electric fields degrade chael mobility? What is the major differece betwee log chael ad short chael MOSFTs? How ca tur these ito useful logic deices? MOSFT Outut Characteristics This makes sese based o what we already kow about MOSFTs For low drai oltages, the MOSFT looks like a resistor if the MOSFT is aboe threshold ad deedig o the alue of V G. Now we ca obtai the coductace of the chael MOSFT Outut Characteristics So we ca describe the liear regime, but how do we describe the saturatio regime As the drai oltage is icreased, the oltage across the oxide decreases ear the drai ed. The resultig mobile charge also decreases i the chael ear the drai ed. To obtai a exressio for the drai curret i saturatio, substitute i the saturatio coditio Pich off eletio Regio Chael Regio V But agai, this is oly alid i the liear regime. We are assumig that V << V G V T eletio Regio Chael Regio 1

2 MOSFT Outut Characteristics Let s summarize the outut characteristics for NMOS ad PMOS Let s try a simle roblem P-tye Si NMOS For a -chael MOSFT with a gate oxide thickess of 10 m, V T = 0.6 V ad Z =5 m ad a chael legth of 1 m. Calculate the drai curret at V G = 5V ad V = 0.1 V. Reeat the rocess for V G = V ad V = 5 V. iscuss what haes for V = 7 V. Assume a electro chael mobility of 00 cm /Vsec. Let s start by fidig the isulator caacitace i Ci = ε = d 14 (.9)( ) 10 6 = For the first set of gie arameters V < (V G -V T ) so we are i the liear regime 7 F cm N-tye Si PMOS For the secod set of gie arameters Z 1 = Ci ( VG VT ) V V L 4 = A Z sat 1 sat We are i saturatio = Ci ( VG VT ) V ( V ) L = A V = 5 V ad (V G - V T ) =.4 V Nothig haes for V = 7 V as we are well ito the o-liear regime. But all of these models deed o the effectie carrier mobility Remember the mobility? Ad from the defiitio of the curret, we ca defie the mobility Usig the defiitios for the hole ad electro currets: = q = q d d = q = q x We wat to defie a curret, or charge er uit time crossig of obseratio orietated ormal to the directio of curret flow. = q = q = q = q d d Proortioal to: Carrier elocity Carrier cocetratio Carrier charge The electro ad hole mobility the becomes: c = lectro Mobility m = m c uits of: Hole Mobility What ca we say about the mobility i geeral? Refers to the ease with which carriers moe through a host crystal.

3 What does temerature mea to mobility? Silico mobility at 00 K Seems like there are two mai cometig heomea murity (doat) Scatterig: - + th T imurity N A + N N A + N The force actig o the articles is Coulombic. There is less chage i the electro s directio of trael the faster it goes. Phoo (lattice) Scatterig: hoo hoo 1 1 = T 1/ m # T T hoos Phoo scatterig mobility decreases as the temerature icreases. th Lattice Scatterig oized murity Scatterig Sice the scatterig robability is iersely roortioal to the mea free time ad the mobility, we ca add idiidual scatterig mechaisms iersely. 1 1 = hoo + imurity We kow bulk mobility, what makes the chael mobility differet? There are ow more scatterig mechaisms ad the electros are cofied to a smaller sace i the chael V G What does the surface actually look like? Gate Source rai V We hae additioal surface roughess scatterig F SiO Si lectric field eeded to iert surface ulls electros closer to the gate iterface. More field icreases the iteractio with the surface. This leads to a decrease i mobility ot see i the bulk. Parameters Mea V T / Mea V T V T SS Uits (mv) % (mv/ decade ) SS / SS Mea ( o / off ) o / off /( o / off ) % % No SR Fixed SR

4 We are also aware of the fact that there ca be stray charges reset i the isulatig oxide Alkali metals ca easily be icororated i the oxide durig the fabricatio rocess. These metals iduce ositie charges i the oxides which iduce egatie charges i the semicoductor. The magitude of the effect deeds o the umber of sodium atoms ad their distace from the surface. The atoms may i alied fields which leads to a cotiuous chage i the threshold oltage. What about oxide charges? Positie charges arise from iterface states at the Si-SiO iterface. Whe oxidatio is stoed, some ioic silico is left ear the surface. These ios alog with other ucouled bods forms a sheet of ositie charge at the iterface. The charges deed o oxidatio rate, heat treatmet, ad crystal orietatio. Why are deices made o [100] istead of [111]? Because iterface charges are 10x higher o [111] relatie to [100]. So how do they effect the effectie mobility? V G Source Coulomb iteractios betwee the electros i the chael ad the traed oxide charges reset aother scatterig rate ot see i the bulk. f we lot the effectie carrier mobility i a MOSFT as a fuctio of the aerage traserse electric field we get the uiersal mobility degredatio cure. The cure is alid for ay MOSFT ideedet of deice ad structural arameters such as oxide thickess. rai V So how do we determie the traserse electric field? We determie the traserse field by alyig Gauss Law Q = ds = ρ d S From this we ca fid the aerage traserse field i the middle of the chael We ca ofte exress the degradatio by rewritig the drai curret equatio New term causes drai curret to icrease subliearly with gate bias for Mobility degradatio large biases. arameter 4

5 But there is also a strog deedece of the logitudial electric field Carrier elocity icreases liearly with electric field util it saturates. After saturatio, mobility o loger makes ay sese. Let s describe the elocity i the followig way x = m = ± x c, m, The maximum logitudial field is the oltage dro ear the drai ed diided by the legth of the ich-off regio. where ΔL t OX x j x Short Chael ffects Aalyzig must be modified i short chael deices ffectie chael mobility decreases with icreasig traserse eredicular electric field to the gate oxide. For ery high logitudial electric fields i the ich-off regio, the carrier elocity saturates. a short chael deice, the carriers trael at the saturatio elocity for most of the chael. rai curret does ot icrease quadratically with V G V T but ow has a liear deedece. We kow a lot about MOSFTs, ow we seek to uderstad their use i digital logic, the simlest of which is the ierter Oe of the most imortat cocets i ierters is the oltage trasfer characteristic. There are 5 key oits i the oltage trasfer characteristic. Logic high or 1 (V OH ) So how do we determie the oltage trasfer characteristic (VTC)? Cosider the simle ierter circuit show to the right the outut loo of the circuit, we see that from the ower suly to groud, the curret through the resistor is the same as.. Logic low or 0 (V OL ). tersectio of lie with uity sloe (V OUT = V N ). V. Uity gai oit V L V. Uity gai oit V H Uity gai oits are useful because if the iut oltage i i betwee them, the the outut sigal is amlified. mortat for oise cosideratios too. The ower suly oltage is equal to the oltage dro across R L lus V S. This discussio souds just like the load lie discussio we had before begiig our discussio of the BT. 5

6 So we must aalyze the load lie to determie the VTC Remember load lies (LL)?? LL goes through V o oltage axis because whe the outut curret is zero all the oltage aears across the MOSFT. LL goes through V /R L o the curret axis because whe the oltage across the MOSFT is zero, the oltage across R L must be V. We chage V G ad we moe from oe characteristic to the ext. tersectios tell us what drai bias is equialet to the outut oltage (caacitor lays o role here). So look at the VTC cure agai As we the swee V N (V G ) from low to high the outut switches from high to low. We ca sole for ay oit o this cure by usig reious equatios ad recogizig which regio we are comutig (liear or saturatio). Suose we wat to determie V OL or logic leel 0 which occurs whe the iut V G is high ad outut V is low. the C case, the curret through the MOSFT is the same as the curret through the resistor, or We ow hae a desig equatio for the load resistor, R L, i our ierter circuit We kow we wat the trasitio to be ery stee, high gai, ad the trasitio should be aroud V /. We also kow that the system eeds to be tolerat of oise ad haig a trasitio oltage aroud V / esures tolerace of oise. R L whe the outut is low is still ot zero ad this leads to ower dissiatio. So, let s get rid of RL altogether ad use a MOSFT i lace of R L. Ca we still use the same aalysis as before to come u with the ew VTC? Yes, we ca use the same aalysis but the math is much messier ut oltage for NMOS is still V G but V G V for PMOS. f the outut oltage is V of the NMOS there are o issues, but o the PMOS V OUT = V V Load elemet ot a simle resistor but MOSFT with its ow trasfer characteristics. But we still get a VTC which is ery familiar 6

7 Cosider a calculatio the of the curret i regio NMOS is i saturatio ad PMOS is i the liear regime. NMOS PMOS These two currets must be equal for the caacitor to ot lay a role We get aother desig equatio for iut ad oututs 7