Regenerative Property

Transcription

1 DESIGN OF LOGIC FAMILIES Some desirable characteristics to have: 1. Low ower dissiatio. High oise margi (Equal high ad low margis) 3. High seed 4. Low area 5. Low outut resistace 6. High iut resistace 7. Reliability, Ease for testig 8. Low cost 9. High fa-out 10. Low fa-i Other imortat factors are: 1. Sigle ower suly. System must have regeerative roerty 3. System must ossess directivity 4. Circuit fuctioality does ot deed o desig arameters 5. Rail-to-rail outut switchig Regeerative Proerty Directivity Proerty Page 1 of 16

2 Chage eeds to be roagated i oe directio oly. This is very difficult to achieve as there is always coulig ad feedback. We will be lookig for a circuit with miimum feedback or coulig i the system. IDEAL INERTER OLTAGE TRANSFER CHARACTERISTIC (TC) REAL INERTER TC Page of 16

3 Iverters A iverter ca be built with a MOS ad either a resistor, MOS, MOS Deletio or a MOS trasistor. Resultig iverter has differet characteristics deedig o tye of load. I our work although we touch o other tye of iverters however our focus will be o CMOS iverter, usig the MOS as a load. Load CMOS INERTER ( Static Characteristic) AND NON_RATIOED LOGIC A CMOS iverter has the followig attributes: Simle circuit ad hece has miimum silico area Iut to iverter is a caacitace, so ractically o curret flows i or out of the iverter termials. The iverter is i a steady state most of the time ad as such draws miimum ower It has well defied out levels Page 3 of 16

4 Regios of oeratio of the iverter: I the steady state regios oe of the trasistors is off, hece o direct ath betwee dd ad groud exist as show below. I regio A, MOS is i the liear regio while MOS is cut off. Curret will ot flow to groud but the MOS is ON givig full dd at the outut. out=dd. I regio B, MOS is i the liear regio while MOS is i saturatio: I D [ gs t ] igorig modulatio effect. N SAT Page 4 of 16

5 I ds [( i )( t o ( ) o ) ] I d [ gs Also Id = - Id t ] Equate the two ad solve for o o ( i t ) ( i t ) ( i t ) ( i t ) Ca be chaged as desig arameter I regio C, Both NMOS ad PMOS are i saturatio. Id [( i t )] Id [( i t)] Id= -Id, equatig ad maiulatig i t 1 t To obtai the best switchig oit, the gate threshold voltage (i=out at TC) has to be dd/ If =1, the i = dd/. This is our desig criterio hece, maiulatig the exressio to obtai desig arameters W ad W: C C ox ox W L W L 1, Assume L=L, Cox= Cox Page 5 of 16

6 w w w 1 or w 1 N, 3. 1for CMOSIS 4B 3 Geerally, let µr = µn/ µp, the W= µr WN P Coclusio: This meas that we eed to make W µr times greater tha W to get switchig aroud dd/. I ractice, we use W = W. (Due to savig i area ad also due to the fact that the variatio of TC aroud i is ot much.). Makig B > B the TC curve moves to the left ad vice versa as show below: Page 6 of 16

7 EFFECT OF TEMPERATURE A icrease i temerature results i a decrease i mobility ad a dro i curret. I D 1.5 T A icrease i temerature results i a decrease of the Threshold oltage t. Icrease i Tem. Page 7 of 16

8 NOISE MARGIN Iverters are usually made u of trasistors which are themselves based o semicoductor materials. The material ad the trasistors ad cosequetly the gates are affected by chage i voltage, temerature ad rocess variatio. These chages lead to ucertaities i erformace. The best logic family is the oe that is immue to metioed variatio. Also, it is ideal that the logic family characteristics is ot affected by the choice of the desig arameters drastically to be o fuctioal. Lookig back at the iverter, whe drivig a load, we eed to have some tolerace i the voltages corresodig to a logic 1 or logic 0. Noise margi: What is cosidered to be high or low at out from oe stage should be cosidered valid as iut i by aother stage. NM L IL ( MAX ) OL( MAX ) NM H IH ( MIN ) OH ( MIN ) Page 8 of 16

9 If we do the mathematical aalysis, 1 OUT at regio D(iflictio oit) where MOS is i saturatio ad MOS is IN i liear regio Similarly, 1 OUT at regio B (iflictio oit) where MOS is i liear ad MOS is i IN saturatio regio. For CMOS usually OLmax is close to 0 ad OHmi is close to. To determie either ILmax or IHmi we make use of several equatios icludig do/di = 1, I= I, W 1 I DS K' GS t DS L W I DS 1 K' GS t 1 L DS DS 1. MOS i liear regio MOS i Saturatio regio W I DS K' P GS t DS DS L MOS i Saturatio regio W I DS 1 K' P GS t 1 DS L MOS Saturatio regio To determie ILmax we kow MOS is i Saturatio ad MOS is i the liear regio, while determiig IHmi, PMOS is i the saturatio while MOS is i the lier regio. For a give (say dd=5) ad after maiulatio, we obtai: NM L NM L IL( MAX) OL( MAX) 3 3 TP 8 3 TN Page 9 of 16

10 NM H NM H IH( MIN) OH( MIN) 3 5 TP 8 3 TN Desig Guidelies: Usually we like to have IH=IL ad half way through the characteristic. This is to say that we should have fast ad abrut switchig. Kee r=1. \ Page 10 of 16

11 NON-RATIOED LOGIC CMOS I stadard CMOS whe we chage r the characteristic curve is shifted right or left but we always get rail to rail switchig as show i the figure below; However deedig o the load coditio several classes of logic families exist that the voltage outut i articular ol deeds o the ratio of the ull u to the ull dow devices. These are called ratioed logic ad we will review oe such logic family called seudo-mos. Page 11 of 16

12 PSEUDO-NMOS, NON Ratioed Logic The TC of this iverter is show above. Whe i = 0, NMOS is off, MOS is o ad the outut ode is coected to. However whe i is we have a differet sceario. Usig models, Let us look at a resistive model of this iverter: OUT Let R 1 OUT R R R R 1 1 Not a accetable logic level! The W/L ratio affects the behavior of the circuit articularly chages out. Whe i = dd, NMOS is o, MOS is o ad let us have a closer look: MOS is i liear regio as ds<gs-t while MOS is i the saturatio regio. Page 1 of 16

13 Equatig the curret i both trasistors ad lease otice the simlificatio of t = 0. we get: ds ID [( gs t) ds ] [ gs t] Relacig i equatio above,,, 0.,. gs Assume N Now 3 P gs ds CoxN CoxP ad LP LN O t [( 0. ) O ] [ 0. ] [( 0. ) O ] [ 0. ] [0.8 OL 0.8 OL 0. 8 OL 0. 4 C W ] P P ox LP OL * 0. 4 WN NCox LN W P P OL * 0. 4 NWN W P OL *(0.4 / 3) WN For ol to be valid, OL t or If we assume OL to be aroximately t/, say 0.3 the, for =3.3 t O Page 13 of 16

14 WP 0.3 *(0.4 / 3), 3.3 WN 0.3 The WP / WN 1.1* 0.4 Or WN 1.5 WP for our rocess, resectig WP,mi Both trasistors have to meet the miimum criteria for desig rule. Choose WP to the correct ratio ad verify that P W N W ad W are greater thaw. N MIN I this case, we ca kee W P to a miimum ad icrease W N to the aroriate ratio. Alteratively, we assume that both Ls are equal ad if the seed is ot a issue, the we ca icrease L which would imly icreasig resistace of the trasistor. P Page 14 of 16

15 TRANSMISSION GATE (TG) CIRCUITS Examle of circuit voltages: g = 5, t = 0.7 Examle of voltage estimates at Source of NMOS for various voltages at the Drai (t = 0.7). i() out() As oticed from the table, a NMOS TG is ot a good trasmitter of logic 1 (high) sigals. Similarly, for PMOS circuits, i() out() The PMOS is ot a good trasmitter of logic 0 sigal. To remedy to the roblem we ut a air of PMOS ad NMOS trasistor i arallel. Page 15 of 16

16 CMOS TRANSMISSION GATE The above circuit asses low as well as high level sigals without ay loss i the outut level voltage. Page 16 of 16