UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

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1 UNIVESITY OF CLIFONI College of Egieerig Departmet of Electrical Egieerig ad Computer Scieces drei Vladimirescu Homework # EECS141 Due Thursday, February 3, Cory Problem 1 Extractig Uified Model Parameters from Simulatio The objective of this problem is to simulate a complex trasistor model usig SPICE, extract fudametal iformatio from the results to build a approximate trasistor model for use i had calculatios, ad the compare the two models. 1 Usig SPICE, geerate the family of I-V curves for a NMOS trasistor with the followig parameters: W/L = 10u/.5u Sweep VDS from 0V to.0v i 0.1V icremets VGS = 0.4V, 0.8V, 1.V, 1.6V,.0V VSB = 0V, 1.0V For this problem use a geeric 0.5um model by addig the followig lie to your SPICE deck or copyig the same file to your ow accout or workstatio:.lib /home/ff/ee141/models/g5.mod TT Sol: The followig Spice deck is writte to geerate the family of curves: * EE141 SPING 005 HW POB 1 * Geerates family of I-V curves for a give NMOS model * eferece trasistor model.lib '/home/ff/ee141/models/g5.mod' TT * paramters.param sb = 0 * Netlist to probe the trasistor M1 drai gate source bulk NMOS w=10u l=0.5u * three DC voltage sources to apply test sigals VDS drai 0 0 VGS gate source 0 VSB source bulk sb * coect the source to groud with a 0 V source VSOUCE source 0 0 * format output for use i Waves.optios post= * DC sweep with VDS as the ier sweep, ad outer loops * set differet values for VGS ad VSB. ecall * that the source termial is fixed at 0 potetial.

2 .DC VDS VGS plot DC I(M1).alter.param sb = 1.ed The Spice deck is simulated with HSpice, ad the resultig plot is geerated i Waves: 1B Based o the results from the previous part, determie the followig model parameters: VT0, kp, λ, γ. You may assume that velocity saturatio does t play a sigificat role ad -ΦF = 0.6V. Sol: There are multiple ways to extract these parameters, but a simple method is as follows.

3 VT0: Select two poits i the saturatio regio from differet VGS curves, but with VSB=0 ad the same VDS i both cases. This allows us to extract VT0 from the uified model equatios. The poits ca be measured directly i Waves or graphically from the result i 1. Poit VGS VDS ID 0.8V 1.5V 00u B 1.V 1.5V 1.08m VT0=0.49V λ is extracted with the same method, this time pickig two poits with the same VGS but differig VDS: Poit VGS VDS ID 1.6V 1.4V.04m B 1.6V.0V.08m λ = γ is extracted the same way with VDS ad VGS held costat ad varyig VSB Poit VSB VGS VDS ID 0V 1.6V V 1.54m B 1V 1.6V V.08m

4 V T = 0.65V Now, use the body effect formula: γ=0.33v 1/ kp is foud by pluggig a sigle poit ito the saturatio curret equatio: Poit VSB VGS VDS ID 0V V.0V 3.m 3.m = 0.5*0*kp(-0.49) ( *) kp=133u/v 1C Startig with the SPICE deck used i the first part, add your ow simple trasistor model usig the parameters determied above. This should be of the form.model mos_simple NMOS (LEVEL = 1 + VT0=?? KP=?? GMM=?? LMBD=?? PHI=0.6) Geerate the family of I-V curves for a NMOS trasistor with the followig parameters, showig simulatio of both the origial model ad your ow simplified model o the same plot. Commet o ay differeces. Sol: The ew spice deck is as follows: * EE141 SPING 005 HW POB 1C * Geerates family of I-V curves for a give NMOS model * ad a simpler approximate model * eferece trasistor model.lib /home/ff/ee141/models/g5.mod TT * approximate model.model mos_simple NMOS (LEVEL = 1 + VT0=0.49 KP=133e-6 GMM=0.33 LMBD=0.036 PHI=0.6) * paramters.param sb = 0 * Netlist to probe the two trasistors M1 drai gate source bulk NMOS w=10u l=.5u

5 M drai gate source bulk mos_simple w=10u l=.5u * three DC voltage sources to apply test sigals VDS drai 0 0 VGS gate source 0 VSB source bulk sb * coect the sources to groud with 0 V supplies * this fixes the absolute voltage levels i the circuit wrt groud * ad also provides a way to measure the drai curret, because * hspice will save the currets through these supplies VSOUCE source 0 0 VSOUCE source 0 0 * format output for use i Waves.optios post= * DC sweep with VDS as the ier sweep, ad outer loops * set differet values for VGS ad VSB. ecall * that the source termial is fixed at 0 potetial..dc VDS VGS plot DC I(M1) I(M).ed Waves is used to plot the resultig two families o a sigle plot show above. There are two mai differeces:

6 1) I the saturatio regio the level 1 model predicts too much curret for high VGS, too little curret for low VGS ) I most cases the curret i the liear regio is too low i the simple model, eve for gate voltages where the saturatio curret is close to the origial model. other way of lookig at this is that i the liear regio the level 1 model geerally predicts a weaker device, but the liear regio exte to higher values of VDS. These differeces are cosistet with the fact that short chael effects are eglected i the level 1 model, but ot the origial model. Compared with the quadratic level 1 model, we see that I grows slower tha quadratic with VGS-VT i the full model, ad saturatio is reached at lower values of VDS for a give VGS. The slope of the curves i the saturatio regio is similar i both models.

7 Problem Geeratig a Voltage Trasfer Characteristic Draw the VTC for this circuit. Determie (or estimate, if ecessary, from your VTC) the followig parameters: V OH, V OL, V M We are give both load lie plots for the active NMOS device ad the o-liear device of the shaded box. How do we lik the iformatio provided by these curves to geerate iformatio about iput ad output voltages? First, we eed to realize that the output voltage of the NMOS device determies what the voltage drop across the shaded box. That is, Vout = V DS = V DD V shaded-box B C D E F, G Sice we kow I-V relatioships i each device ND also the fact that the curret through oe must be equal to the curret through the other, we ca maipulate the curves to tell us somethig. Usig the relatio above, we ca superimpose a horizotally-flipped versio of the shaded-box s I-V curve oto that of the NMOS curves. The itersectios are the operatig poits of this circuit ad will give us the iput-output voltage relatioships we eed to build our VTC. Below is the revised, superimposed graph with the itersectios labeled:

8 Poit Vi (V GS ) Vout (V DS ).4V 0.57V B.0V 0.7V C 1.6V 0.97V D 1.V 1.4V E 0.8V.V F 0.4V.5V G 0.0V.5V V M V M The resolutio of our plot will ot be as fie as we d like, but you ca see how if we had more poits, the curve becomes more ad more accurate. This VTC is plotted usig Matlab. You ca also do it by had. Lookig at the VTC, it is quite easy to determie what V OH, V OL, ad V M are: V OH.5V -- NMOS off, shaded-box offers resistive path to brig Vout high, assumig the output is drivig a capacitive load or ifiite resistace (which is ofte true for aalysis questios like these)

9 V OL V M B ~0.6V Whe the NMOS trasistor turs o, it tries to pull Vout low. t the same time, the shaded-box is tryig to pull Vout high. Depedig o the ratio of their effective resistaces, V OL will chage. This is somethig that will be discussed later o the semester whe atioed Logic is covered i the course. ~1.3V Slightly off the 1.5V we were hopig to get i a ideal symmetrical VTC for a iverter. This circuit ca be used as a alterative to a traditioal CMOS iverter (where the o-liear device is a PMOS trasistor). From the cocepts discussed thus far i lecture ad from the results of your VTC, what are the disadvatages of this method? Icomplete pull-dow of the output ode meas we do t get full rail-to-rail swig at the output. The oise margi is reduced. There is static power cosumptio whe the iput is high, because there is a direct path from supply to groud whe the NMOS trasistor is o. lso the high V OL lea to static power cosumptio i the gate that it drives. For low power applicatios, we aim to miimize static power. The VTC also is asymmetric, meaig that a risig trasitio ad its associated output have differet large sigal ad timig characteristics as a fallig trasitio. Ueve oise margi is also aother problem.

10 Problem 3 VTC ad Iverter alysis 3 Iverter V OH : First assume that VOL<0.5V because we kow that the NMOS device is much stroger tha the PMOS device for a full VDD iput (MUST remember to verify this assumptio after fidig the solutio). I this case we immediately ote that VOH=VDD=.5V, because whe VIN=VOL the NMOS device is i the cutoff regio (ID=0) ad the PMOS device provides a coductive path to VDD. V OL : Now, we fid VOL by solvig for V out whe V i =V OH =.5V. gai, with the assumptio that VOL<0.5V, ote that the PMOS device will be i saturatio because VDS > VGS-VTH ad VGS > VTH. Followig the same assumptio, the NMOS device is i the triode (liear) regio because VDS<VGS-VTH ad VGS > VTH. Thus, the drai currets are give by: W V DS W V OL Id = k ( VGS VT ) VDS = k ( VDD VT ) VOL L L I kp Wp kp Wp = V V + V = Lp Lp V V + V V I = I ( ) ( 1 λ ) ( ) ( 1 λ( )) dp GSp Tp DSp GSp Tp DD OL d dp Solvig for V OL = 4mV (our assumptio checks out) V M : To fid VM, we follow a similar patter of assumptio followed by verificatio. ssume that VM > 0.5V, i which case the PMOS device will be operatig i the triode regio. Sice Vi=Vout=VM at the midpoit, we see that VGS=VDS for the NMOS device, so it is ow operatig i the saturatio regio. The drai currets are ow give by: k W k W Id = ( VGS VT ) ( 1+ λvds ) = ( VM VT ) ( 1+ λvm ) L L W p V DSp W p ( VDD VM ) Idp = kp ( VGSp VTp ) VDSp = kp ( VDD VTp )( VDD VM ) Lp Lp I = I d dp Solvig umerically, V M =1.7V Iverter B V OH :

11 Set V i = 0, M1 is off. ( ) VT = VT0 + γ φf + VSB φf V = V SB out M off if: V V = V V V = 0 GS T DD out T Solve for V out = V OH = 1.76V V OL : Set V i = V dd =.5V; both M1 ad M are o ad guessig M is i saturatio because V out will likely be small, while M1 likely i liear regio. W 1 V DS W1 Vout Id1 = k ( VGS VT ) VDS = k ( VDD VT ) Vout L1 L1 k W I = V V + V = V V V + V + V V I k W ( ) ( 1 λ ) ( γ ( φ φ )) 1 λ( ) ( ) d GS T DS DD out T 0 F out F DD out L L = I d1 d Solve for V out = V OL = 6mV V M : Similar to the calculatio for V OL above, except M1 is also i saturatio. Equate currets ad solve for V out = V M = 91mV Iverter C V OH : Sice this is a CMOS iverter, V OH =.5V V OL : Similarly, V OL =0V V M : Both devices will be i saturatio k W k W Id = ( VGS VT) ( 1+ λvds) = ( VM VT) ( 1+ λvm ) L L I kp Wp kp Wp = V V + V = Lp Lp V V V + V V I = I ( ) ( 1 λ ) ( ) ( 1 λ( )) dp GSp Tp DSp DD M Tp DD M d dp Solvig for V M =1.19V

12 3B Here s the HSPICE etlist to verify the results from above: * EE141 SPING 005 HW POB 3.model mos NMOS (LEVEL = 1 + VTO = 0.5 KP = 18e-6 GMM = 0.5 LMBD = 0.06 PHI = 0.3).model pmos PMOS (LEVEL = 1 + VTO = -0.5 KP = 5e-6 GMM = 0.5 LMBD = 0.1 PHI = 0.3) *Iverter M1 vout_p 0 vdd vdd pmos W=1u L=0.5u M vout_p vi 0 0 mos W=1.5u L=0.5u *Iverter B M3 vdd vdd vout_ 0 mos W=0.5u L=0.5u M4 vout_ vi 0 0 mos W=.0u L=0.5u *Iverter C M5 vout_std vi vdd vdd pmos w=3u l=0.5u M6 vout_std vi 0 0 mos w=1u l=0.5u *Sources VSUPP vdd 0.5 VSC vi 0 0.optios post=.op.dc VSC END This produces the followig

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14 Problem 4 Propagatio Delay ad Techology scalig 4 Iverter Pull-dow eq_pd : 0 : k W I = ( VOH VT ) ( 1+ λ VOH ) = 850µ L 0 V = OH =.5 =.94kΩ I 850µ mid : k W I = ( VOH VT ) ( 1+ λ VM ) = 795µ L mid V = M = 1.7 = 1.96kΩ I 795µ 1 eq = ( 0 + mid) =.45k Ω Pull-up eq_pu : 0 : kp Wp I = ( VDD VOL VT ) ( 1+ λ ( VDD VOL )) = 17µ L 0 p ( V V ) DD OL = =.5.4 = 17.8kΩ I 17µ mid : kp Wp I = ( VDD VOL VT ) ( 1+ λ ( VDD VM )) = 116µ L mid p ( V V ) DD M = = = 10.6kΩ I 116µ 1 eq = ( 0 + mid) = 14.k Ω

15 t = 0.69 C = 169 ps phl e q _ pd L t = 0.69 C = 980 ps t plh e q _ pu L p = 575 ps Iverter B Pull-dow eq_pd : 0 : k W I = ( VOH VT ) ( 1+ λ VOH ) = 450µ L 0 V = OH = 1.76 = 3.9kΩ I 450µ mid : k W I = ( VOH VT ) ( 1+ λ VM ) = 49µ L mid V = M =.91 =.kω I 49µ 1 eq = ( 0 + mid) = 3.1k Ω Pull-up eq_pu : 0 : k W I = ( VDD VOL VT 0 γ ( φf + VOL φf )) ( 1+ λ ( VDD VOL )) = 117µ L 0 ( V V ) DD OL = =.5.6 = 19.4kΩ I 117µ mid : k W I = ( VDD VOL VT 0 γ ( φf + Vout φf )) ( 1+ λ ( VDD VM )) = 113µ L mid ( V V ) DD M = =.5.91 = 14kΩ I 113µ 1 eq = ( 0 + mid) = 16.7k Ω

16 t = 0.69 C = 14 ps phl e q _ pd L t = 0.69 C = 1.15s t plh e q _ pu L p = 68 ps Iverter C Pull-dow eq_pd : 0 : k W I = ( VOH VT ) ( 1+ λ VOH ) = 567µ L 0 V = OH =.5 = 4.41kΩ I 567µ mid : k W I = ( VOH VT ) ( 1+ λ VM ) = 530µ L mid V = M = 1.5 =.36kΩ I 530µ 1 eq = ( 0 + mid) = 3.39kΩ Pull-up eq_pu : 0 : kp Wp I = ( VDD VOL VT ) ( 1+ λ ( VDD VOL )) = 496µ L 0 p ( V V ) DD OL = =.5 = 5kΩ I 496µ mid : kp Wp I = ( VDD VOL VT ) ( 1+ λ ( VDD VM )) = 448µ L mid p ( V V ) DD M = = =.9kΩ I 448µ 1 eq = ( 0 + mid) = 3.95k Ω

17 t = 0.69 C = 33ps phl e q _ pd L t = 0.69 C = 7 ps t plh e q _ pu L p = 5 ps 4B Here s the HSPICE file to geerate curves for the iverters: * EE141 SPING 005 HW POB 4.model mos NMOS (LEVEL = 1 + VTO = 0.5 KP = 18e-6 GMM = 0.5 LMBD = 0.06 PHI = 0.3).model pmos PMOS (LEVEL = 1 + VTO = -0.5 KP = 5e-6 GMM = 0.5 LMBD = 0.1 PHI = 0.3) *Iverter M1 vout_p 0 vdd vdd pmos W=1u L=0.5u M vout_p vi 0 0 mos W=1.5u L=0.5u *Iverter B M3 vdd vdd vout_ 0 mos W=0.5u L=0.5u M4 vout_ vi 0 0 mos W=.0u L=0.5u *Iverter C M5 vout_std vi vdd vdd pmos w=3u l=0.5u M6 vout_std vi 0 0 mos w=1u l=0.5u *Sources VSUPP vdd 0.5.optios post=.op VSC vi 0 pulse p 100p 1.tra 500p 4s.END uig this you ll fid that the measuremets above for propagatio delay are i the same order of magitude as what HSPICE will give you, however, its clear that this approximatio is t that accurate. Showig the HSPICE is good eough for this problem. 4C Here s the HPSICE code for a rig oscillator (5 iverters of type C, iverters ad B ca be costructed similarly): * EE141 SPING 005 HW POB 4c.model mos NMOS (LEVEL = 1 + VTO = 0.5 KP = 18e-6 GMM = 0.5 LMBD = 0.06 PHI = 0.3).model pmos PMOS (LEVEL = 1 + VTO = -0.5 KP = 5e-6 GMM = 0.5 LMBD = 0.1 PHI = 0.3) *Iverter C.subckt INV i out iv_vdd iv_gd M5 out i iv_vdd iv_vdd pmos w=3u l=0.5u

18 M6 out i iv_gd iv_gd mos w=1u l=0.5u.e i * use subckts X1 vi com1 vdd 0 INV X com1 com vdd 0 INV X3 com com3 vdd 0 INV X4 com3 com4 vdd 0 INV X5 com4 vi.ic V(vi)=0 V(com1)=.5 V(com)=0 V(com3)=.5 V(com4)=0 *Sources VSUPP vdd 0.5.optios post=.op.tra 500p 4s UIC.END