MORE TUTORIALS FOR VERILOG DIGITAL ELECTRONICS SYSTEM DESIGN HOMEWORK ASSIGNMENTS DATASHEETS FOR PARTS 10/3/2018

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1 //8 DIGITA EECTRONICS SYSTEM DESIGN FA 8 PROFS. IRIS BAHAR & ROD BERESFORD OCTOBER, 8 ECTURE 9: CMOS TRANSIENT BEHAIOR MORE TUTORIAS FOR ERIOG O the course website you ca fid some useful liks to additioal erilog examles Examle of a bit couter Blockig vs. o-blockig assigmets withi always blocks State machie desig for a Coke diseser DATASHEETS FOR PARTS HOMEWORK ASSIGNMENTS All arts rovided for you i our kits come with datasheets Pi layout i ackage Schematic desig Secify oeratig coditios Provide descritio of how to oerate chi correctly to get desired outut The datasheets ca be dowloaded from the course webage (FullDataSheets-ENGN.zi) Please feel free to refer to these datasheets to hel aswer some questios you have for the lab assigmets. Two (otioal!) homework assigmets are rovided o the course webage (with solutios) HW# covers k-mas, Boolea logic, gate-level imlemetatio, trasistor-level desig ad aalysis, fiite state machie desig HW# covers biary arithmetic, erilog, recofigurable logic, sequetial logic, more trasistor-level desig ad aalysi, A/D coverters. Please feel free to work through these roblems to reare for the exams Note that I will (mostly) cover this same material, through sometimes slightly differetly.

2 //8 EXAM SCHEDUE NMOS I- SUMMARY Two exams i the course that make u ~% of your grade You eed to get a assig grade o the exam ortio as well as the lab ortio to get a assig grade for the class Midterm: Wedesday, :-m Fial: Saturday, 9am-oo Shockley st order trasistor models gs t I ds ds gs t ds ds dsat gs t ds dsat W = Cox cutoff liear saturatio ONG CHANNE I- POT (NMOS) SHORT CHANNE I- POT (NMOS) NMOS trasistor:.um techology, d = um, W/ =., =., T =. cut-off X - DS = GS - T iear Saturatio GS =. GS =. GS =. GS =.... DS () d = um X - DS... DS () GS =. GS =. GS =. GS =. X - Early elocity.saturatio DS () d =.um GS =. GS =. GS =. GS =. I has a liear deedece with resect to GS (as oosed to quadratic) so a reduced amout of curret is delivered for a give cotrol voltage.....

3 //8 x 7 TRANSISTOR MODEED AS A SWITCH S GS T R o D Model as a switch with ifiite off resistace ad a fiite o resistace, R o CMOS INERTER: STEADY STATE RESPONSE R Resistace iversely roortioal to W/ (doublig W halves R o ) = R =... () Oce aroaches T, R o icreases dramatically (for GS =, DS = /) i = i = OTAGE TRANSFER CHARACTERISTICS TRANSFORMING PMOS I- INES Wat commo coordiate set i,, ad I D I D What haes whe iut voltage is ot at rail i < dd, or i > Gd? If the trasistor is ON, the voltage at outut will chage, but will ot go to rail. I DS = -I DS GS = i ; GS = i DS = ; DS = i = i =. i = i =. GS = - GS = -. Mirror aroud x-axis i = + GS I D = -I D Horiz. shift over = + DS

4 //8 CMOS INERTER I- CURES CMOS INERTER TC PMOS X. - i = NMOS i =.. NMOS off PMOS res NMOS sat PMOS res Takig those itersectio oits from the load curves, we obtai the voltagetrasfer characteristic i =.. i =. i =. i =. i =. i =. i = i = i =.. i =. i =. i =. i =. i =.. ().. i =.um, W/ =., W/ =., =., T =., T = -. ()..... i () NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off CMOS INERTER: SWITCH MODE OF DYNAMIC BEHAIOR SWITCHING THRESHOD R Defie M to be the oit where i = (both PMOS ad NMOS i saturatio sice DS = GS ) If M = /, the this imlies symmetric rise/fall behavior for the CMOS gate Recall at saturatio, I D =(k /)(W/) ( GS - T ), where k = C ox = ox /t ox R Settig I D = -I D k W ( M k W T) ( M ) T i = i = Gate resose time is determied by the time to charge through R (discharge through R ) Assumig T =- T W / W / k k

5 //8 REATIE TRANSISTOR SIZING IMPACT OF UNMATCHED DRIE STRENGTHS Whe desigig static CMOS circuits, balace the drivig stregths of the trasistors by makig the PMOS sectio wider tha the NMOS sectio to. β= β=w /W maximize the oise margis ad obtai symmetrical characteristics (). β= Nomial: β=.... i () Skewig the β ratio will shift the switchig threshold MOS STRUCTURE RESISTANCE The simlest model assumes the trasistor is a switch with a ifiite off resistace ad a fiite o resistace R o S GS T However R o is oliear, time-varyig, ad deedet o the oeratio oit of the trasistor How ca we determie a equivalet (costat ad liear) resistace to use istead? R o D MOS STRUCTURE RESISTANCE Aroximate R o as the resistace foud durig liear oeratio Simle to calculate but limited accuracy Istead use the average value of the resistaces, R eq, at the ed-oits of the trasitio (i.e., ad /) Req ( Ro( t) Ro( t)) / I I I I D R mid R... / GS = DS

6 //8 EQUIAENT MOS STRUCTURE RESISTANCE CMOS INERTER: DYNAMIC BEHAIOR Req I where C I so, Req C R eqnmos ox ox W (, W W ( T) T) R eqpmos W 7 x (for GS =, DS = /)... () R R = Trasiet, or dyamic, resose determies the maximum seed at which a device ca be oerated. t H = f(r, ) R eq is essetially ideedet of as log as >> T + / i = SOURCES OF CAPACITANCE SOURCES OF CAPACITANCE i i M C DB C G M M C DB C G M i C GD C w i M C DB C G M M C DB C G M itrisic MOS trasistor caacitaces extrisic MOS trasistor (faout) caacitaces wirig (itercoect) caacitace C DB +C DB +C G +C G