LECTURE 5 PART 2 MOS INVERTERS STATIC DESIGN CMOS. CMOS STATIC PARAMETERS The Inverter Circuit and Operating Regions

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1 LECTURE 5 PART 2 MOS INVERTERS STATIC ESIGN CMOS Objectives for Lecture 5 - Part 2* Uderstad the VTC of a CMOS iverter. Uderstad static aalysis of the CMOS iverter icludig breakpoits, VOL, V OH,, V IH, N MH, N ML ad V th. Assigmet Kag ad Leblebici: pp * *Lecture legth - 75 miutes /3/96 2/8/02 The Iverter Circuit ad Operatig Regios To show circuit parameters, we use the simplest circuit, a iverter. V GS G S V S Vi G V out S The PFET source S ad substrate B are both at, so o body effect for either FET. For the PFET, V GS V i ad V S V out. Operatig Regios NFET Cutoff: V i < V T Liear: V i V T, V out < V i V T Saturatio: V i V T, V out V i V T PFET Cutoff: V i > Liear: V i, V out > V i V Tp Saturatio: V i, V out V i V Tp 2 /3/96 2/8/02

2 See the 3- figures i Kag ad Leblebici pp The IV characteristics itersect to form the VTC: I I p, V GSp V GS ad V Sp V S. See VTC o the ext page. Note operatig regios; liear-liear regio does ot exist, ad if < V T V Tp ad regio exists i the ceter i which both the NMOS ad PMOS devices are i the Cutoff regio. See pp of Kag ad Leblebici for a possible VTC i this abormal case. The Parameters ue to cutoff of the N ad P devices respectively, V OH V OL 0 is at the slope poit. The authors fid by simultaeous solutios, but without iteratio ecessary sice there is o body effect. The equatios used: 3 /3/96 2/8/02 V out OP V OH A N OFF N SAT B P LIN 2 V out V i V Tp P SAT N SAT V out V i V out V i V T C V th 3 N LIN P SAT P OFF V Tp V OL 0 V T V V IH th E OP V i 4 /3/96 2/8/02

3 2V V out + V T0, p + V IL T0, + k R av out + b V T0, 2 ( V V T0, ( V p out ( V out 2 The first equatio, after beig evaluated to the a V out + b form is substituted ito the secod equatio ad the secod equatio is solved for V out. V out ca the be substituted back ito the first equatio to fid. For V IH, the equatios are: V + V T0, p + ( 2V out + V T0, IH k R cv out + d 2 ([ 2 ( V IH V T0, ] V out V out ( V IH V T0, p 2 5 /3/96 2/8/02 The first equatio, after beig evaluated to the c V out + d form is substituted ito the secod equatio ad the secod equatio is solved for V out. V out ca the be substituted back ito the first equatio to fid V IH. Additioal breakpoits ad V th are give o the ext page V th is solved for by equatig the currets i saturatio for the two devices i terms of V i ad solvig for V th V i : I, SAT ( V i I p, SAT ( V i It is iterestig to ote that, betwee poits 2, V th ad 3, the VTC is vertical which implies ifiite voltage. This was also true for the NMOS VTC. Is this real? Actually ot. If chael legth modulatio is icluded, the slope is high, but less tha ifiite. The text authors focus o the special case i which V th /2. For this case, the CMOS VTC approach the ideal VTC. I this case, for V T0, V T0, p (Cotiued o page after ext: 6 /3/96 2/8/02

4 V Tp V T0,p < 0, V T V T0, k k p V th + V T V i2 V i V out2 + V T V + Tp V out3 + V T V + T 7 /3/96 2/8/02 -- ( 3V, 8 + 2V T0, -- ( 5V ad 8 2V T0, + V IH which does give quite good oise margis sice, i geeral for CMOS, N ML ad N MH V IH. How does oe achieve this ear idea situatio? W ---- L µ p Make > W ---- µ L p Recall these are effective values of the dimesios, ot draw. Assumig equal L s, with µ 2 to 3 µ p, W p is typically 2 to 3 times W. But, for small devices where velocity saturatio is a problem, a iterestig thig happes. 8 /3/96 2/8/02

5 Static (C Power issipatio ad Area The device velocity saturatio occurs at lower fields tha for the p device, so over higher rages of V S, the mobility differece is less apparet ad this ratio may be overkill to ceter V th. Some views of optimum sizig suggest that the widths should be equal, igorig the mobility differeces. Static (C Power issipatio Fially, for CMOS, P C ( I leakage + I subthreshold Quite small ad a major advatage of CMOS over NMOS. Area I terms of area, a CMOS primitive gate with iputs requires 2 devices whereas a NMOS gate requires oly + devices! Plus, there are more complex local itercoectios. The itegratio desity of fully-complemetary MOS is govered by greater area requiremets whereas NMOS desity is govered by power dissipatio ad heat problems. 9 /3/96 2/8/02 Summary Uderstad the VTC cocept ad the regios of operatio for the MOSFETs i a NMOS iverter. Kow how to fid all of the static circuit parameters, i.e., perform static aalysis for a NMOS iverter. Kow how to fid all of the static circuit parameters, i.e., perform static aalysis for a CMOS iverter. 0 /3/96 2/8/02