Digital Integrated Circuits

Transcription

1 Digital Itegrated Circuits YuZhuo Fu Office locatio:417 room WeiDiaZi buildig,no 800 DogChua road,mihag Camus Itroductio

2 Review cotet Tye Cocet 15, Comutig 10 hours Fri. 6 th 10:00-1:00 Cotet Itroductio Device Iverter /48

3 itroductio CMOS circuit layout ad area Why NMOS/PDN PMOS/PUN 3/48

4 Juctio ricile PN juctio Caacitace domiat 4/48

5 Juctio caacitace P - + N + - The boudary of PN-juctio could accumulate charge whe bias voltage was chaged, which show caacitace characteristic Whe forward voltage imroved/decreased, more/less charges ass,just like these charges are saved/leaved 5/59

6 Juctio Caacitace 6/59

7 Diode Model R S + D - I D C D C diode T I T D 1 C D j0 Φ m 0 More kowledage: Microelectroic Circuits:Aalysis ad Desig Muhammad H.Rashid 7/59

8 Juctio ad diffusio caacitace Forward-bias mode small RC effect for igorig Juctio ca. Diffusio ca. Is domiat Reverse-bias mode Miority carrier cocetratio is very small, so its diffusio ca. Ca be igored large RC effect Juctio ca. Is domiat 8/59

9 PN juctio switchig model R src D 1 src I D t = 0 t = T Excess charge Sace charge D ON OFF ON Time 9/59

10 Device All state ad ricile elocity saturatio I- formula (Hight-K Low-K material ) Gate Caacitace 10/59

11 MOS threshold voltage MOS Cutoff No chael,i ds = 0 t > gs >0 deletio regio(iversio) is formed below the gate gs = t A strog iversio is built u, the otetial at the silico surface reaches a critical value Further icreases the gate voltage roduce o further chages i the deletio layer width 11/59

12 I D (A) Curret-oltage Relatios The Dee-Submicro Era.5 x 10-4 Early Saturatio GS= GS=.0 1 GS= 1.5 Liear Relatioshi 0.5 GS= DS () 1/59

13 Attetio : velocity ositio μ = 3800cm /v.s,μ = 1800cm /v.s Charge er uit area: I D I Qi ( x) C [ gs ( x) T ] ox v( x) Qi ( x W v( x) E( x) d ID C [ gs ( x) T ] W ox dx D ) L 0 I D dx C ox DS 0 W ( L C GS o x [ gs ) T ( x) DSAT DSAT T ] Wd ( DSAT ) d dx 13/59

14 A uified model for maual aalysis G S D B 14/59

15 I D (A) Simle Model versus SPICE.5 x 10-4 DS = DSAT 1.5 elocity Saturated Liear DSAT = GT DS = GT Saturated DS () 15/59

16 Caacitace comoets MOS structure caacitaces Overla ca. G Chael caacitaces C GS C GD Gate-body ca. S D Gate-source ca. C SB C GB C DB Gate-drai ca. Juctio/diffusio caacitaces B Bottom-late ca. Side-well ca. 16/41

17 The Gate Caacitace Polysilico gate C GSO C GDO C ox x d W C W o Source + x d x d W Drai + L d To view Gate-bulk overla t ox Gate oxide + L + Cross sectio 17/41

18 Gate chael Caacitace G G G S C GC C GC C GC D S D S D Cut-off Resistive Saturatio Most imortat regios i digital desig: saturatio ad cut-off

19 Gate Caacitace C GC WLC ox WLC ox C GC WLC ox WLC ox C GC B C GCS = C GCD WLC ox C GCS C GCD 3 GS 0 DS /( GS - T ) 1 Caacitace as a fuctio of GS (with DS = 0) Caacitace as a fuctio of the degree of saturatio

20 High K GeSi I D C ox W L ( GS T ) DSAT DSAT RC I leakage Low K SOI Cu FiFET

21 Iverter Fudametal DC cocet Dyamic chara. Ideal iverter Trasitio state of MOS/MOS Power tye Iverter chai 1/48

22 oltage Trasfer Characteristic Plots the outut voltage as a fuctio of the iut voltage out f ( i ) /91

23 Switchig threshold voltage M 3/91

24 Noise Margis Divide voltage ito discrete regios logic 0/logic 1 X - betwee 0 ad 1 out of rage may damage devices Each logic gate restores the sigal oise is ot cumulative outut voltage rage is arrower tha iut rage 4/91

25 Noise Margi IH =miimum HIGH iut voltage IL =maximum LOW iut voltage OH =miimum HIGH outut voltage OL =maximum LOW outut voltage Logical High Outut Rage Outut Characteristics DD OH NM H Iut Characteristics Logical High Iut Rage IH IL Idetermiate Regio Logical Low Outut Rage OL NM L GND Logical Low Iut Rage 5/91

26 NM H Maig aalog/digital sigals OH IH 1 OH IH DD out Uity Gai Poits Sloe = -1 OH Udefied Regio / > 1 i out IL 0 OL OL 0 t IL IH DD - t DD i NM L IL OL 6/91

27 Regeerative Proerty Do oises accumulate with trasfer? Gai of udefied rage greater tha 1 i absolute(regeeratio coditio) Gai of outside trasiet rage less tha 1 i absolute

28 Regeerative Proerty Regeerative No-Regeerative 8/91

29 Regeerative Proerty v 0 v 1 v v 3 v 4 v 5 v 6 A chai of iverters Simulated resose 9/91

30 Iut&outut resistace The voltage of the iut sigal comes,the gate could be regarded as load of frot gate Set Emty load of curret gate,calcutate I rate Iut resistace i R s r i r i s Greater iut resistace, sigal trasfer,less sigal atteuatio Outut resistace o r o R L R L ' o What is its meaig? Less of the gate outut resistace, smaller affect with load 30/91

31 Fa-i ad Fa-out N M Fa-out N Fa-i M 31/91

32 Delay Defiitios Low to high time(t LH )[50% voltage oit] High to low time(t HL )[50% voltage oit] Proagatio delay time, t d =MAX(t LH,t HL ) Cotamiatio delay time, t cd =MIN(t LH,t HL ) Outut fall time(t f ) [10%-90% voltage oit] Outut rise time(t r ) [10%-90% voltage oit] Edge rate, td=(t f + t r )/ 3/91

33 A First-Order RC Network R v out out (t) = i (1 e t/τ ) v i C out (t) = dd e t/τ t = l () = 0.69 RC Imortat model matches delay of iverter 33/91

34 Delay sec. out (t) = i (1 e t/τ ) out (t) = dd e t/τ t l(1 ) l out out 50%:50% oit time t=l= %:10% oit time t=l10=.3 80%:0% oit time t=l5=1.6 0%:80% oit time t=l10/8=0. 10%:90% oit time t=l10/9=0.1 34/91

35 The Ideal Gate out g = R i = R o = 0 Faout = NM H = NM L = DD / i 35/91

36 CMOS Iverter Load Characteristics I D i = 0 i =.5 PMOS i = 0.5 i = NMOS i = 1 i = 1.5 i = 1.5 i = 1 i = i = 1.5 i = 1 i = 0.5 i =.5 i = 0 out 36/48

37 CMOS Iverter TC Summary of CMOS iverter oeratio Regio Coditio P-device N-device outut A [0,t] liear cutoff DD B [t,dd/] liear saturated DD/ C =DD/ saturated saturated X dro D [DD/,DD- TP ] saturated liear <DD/ E [DD- TP, DD] cutoff liear 0 37/48

38 CMOS static behavior CMOS threshold voltage CMOS oise margi CMOS gai DC robust 38/48

39 I D Switchig Threshold as a fuctio of k C DSAT M M ox Trasistor Ratio DSAT DSAT ( M T ) k DSAT ( ) M DD T ( W ( L T GS DSAT r 1 r DD ) ) r( DD 1 r SAT DSAT cl GT T Lv DSAT T ( W ( W DSAT ) L ) L DSAT k ) ' v k r ' sat DSAT C k k DSAT ( ox W DD DSAT DSAT GS M v v sat sat T T W W DSAT ( M T ) DSAT DSAT ) 0 39

40 Switchig threshold of CMOS iverter Assumig W /W =8, calculatig M =? r k k ' ' W W L L DSAT DSAT 30*( 1) * *0.63 DSAT DSAT ( r T ) ( DD T ) M 1 r (0.43 ) 3.3( ) * /48

41 Switchig threshold of CMOS iverter ( W ( W ) L ) L ' k k ' DSAT DSAT ( ( DD M M DSAT ) T T DSAT ) ( ) ( ) 3.5 This rate let M = dd /! 41/48

42 Switchig Threshold as a fuctio of Trasistor Ratio M M is relatively isesitive to variatios i the device ratio Icreasig the width of the PMOS or NMOS moves M toward DD or GND (3, 1.) (.5, 1.18) (, 1.13) W/W 4/48

43 Determiig IH ad IL out A simlified aroach! OH IH IL ( OH g OL ) g DD M IH M g M, IL M DD g M NM H DD IH, NM L IL i OL IL IH 43/48

44 Examle g=-30, dd =.5, M =1.0 Please estimate NM H ad NM L IH = M - M /G=1.0*(1+1/30)=1.03 IL =( DD - M )/G+ M =-1.5/30+1.0=0.95 NM H = OH - IH = =1.47 NM L = IL - OL = /48

45 Imact of Process ariatios out () Good NMOS Bad PMOS The variatios of device maily cause a shift i the switchig threshold, this robust behavior esures fuctioality of the gate over a wide rage of coditios Nomial Good PMOS Bad NMOS i () 45/48

46 Comutig the Caacitaces NMOS ad PMOS almost is same for uit caacitace C J C JSW C ox (ff/um ) C o (ff/um) C j (ff/um ) m j Φ b () C jsw (ff/um) m jsw NMOS PMOS CDG0 W/L AD(um ) PD(um) AS(um ) PS(um) NMOS 3/ PMOS 9/ Φbsw () 46

47 Comutig the Caacitaces PMOS DD AD=4*4+3*1=16+3=19λ PD= =15λ I Out 1. m =l Metal1 Polysilico NMOS GND Slide 47

48 48 Iverter Chai C L If C L is give: - How may stages are eeded to miimize the delay? - How to size the iverters? I Out ) ( C C t t L ) ( C C C C t t L ) ( 0.69 ) ( C C t C C C C C C t t t L L L

49 CMOS Eergy & Power Equatios E = C L DD P 01 + t sc DD I eak P 01 + DD I leakage 1/f clock f 01 = P 01 * f clock P = C L DD f 01 + t sc DD I eak f 01 + DD I leakage Dyamic ower Short-circuit ower Leakage ower

50 Lowerig Dyamic Power Caacitace: Fuctio of fa-out, wire legth, trasistor sizes Suly oltage: Has bee droig with successive geeratios P dy = C L DD P 01 f Activity factor: How ofte, o average, do wires switch? Clock frequecy: Icreasig