Charge Recycling in MTCMOS Circuits: Concept and Analysis Ehsan Pakbaznia University of Southern California

Transcription

1 Charge Recyclig i MTCMOS Circuits: Cocept ad Aalysis hsa akbazia Uiversity of Souther Califoria pakbazi@usc.edu Farza Fallah Fujitsu Labs of America farza@us.fujitsu.com Massoud edram Uiversity of Souther Califoria pedram@usc.edu ABSTRACT Desigig a eergy efficiet power gatig structure is a importat ad challegig task i Multi-Threshold CMOS (MTCMOS circuit desig. I order to achieve a very low power desig, the large amout of eergy cosumed durig mode trasitio i MTCMOS circuits should be avoided. I this paper, we propose a appropriate charge recyclig techique to reduce eergy cosumptio durig the mode trasitio of MTCMOS circuits. The proposed method ca save up to 46% of the mode trasitio eergy while, i most cases, maitaiig, or eve improvig, the wake up time of the origial circuit. It also reduces the peak egative voltage value ad the settlig time of the groud bouce.. INTRODUCTION As CMOS techology scales dow, the supply voltage is reduced so as to avoid device failure due to high electric fields i the gate oxide ad the coductig chael uder the gate. Voltage scalig reduces the circuit power cosumptio because of the quadratic relatioship betwee dyamic power cosumptio ad supply voltage, but it also icreases the delay of logic gates. To compesate the resultig performace loss, trasistor threshold voltages are decreased, which causes expoetial icrease i the sub-threshold leakage curret []. MTCMOS techology provides low leakage ad high performace operatio by utilizig high speed, low Vt (LVT trasistors for logic cells ad low leakage, high Vt (HVT devices as sleep trasistors. Sleep trasistors discoect logic cells from the supply ad/or groud to reduce the leakage i the sleep mode. I this techology, also called power gatig, the wake up latecy ad power plae itegrity are key issues. Assume a sleep/wake up sigal is supplied by a o-chip power maagemet module. A key questio is how to miimize eergy cosumptio while doig the mode trasitio, i.e., whe switchig from active to sleep mode or vice versa. Aother importat questio is how to miimize the time required to tur o the circuit upo receivig the wake up sigal sice the legth of the wake up time ca affect the overall performace of the VLSI circuit. Furthermore, the large curret flowig to groud whe sleep trasistors are tured o ca become a major source of oise i the power distributio etwork, which ca adversely impact the performace ad/or fuctioality of the other parts of the circuit. Hece, there is a trade off betwee the geerated oise due to the curret flowig to groud ad the trasitio time from the sleep mode to the active mode. Sleep trasistors cause logic cells to slow dow durig the active mode of the circuit operatio. This is due to the voltage drop across the fuctioally-redudat sleep trasistors ad the icrease i the threshold voltage of logic cell trasistors as a result of the body effect. The performace pealty of a sleep trasistor depeds o its size ad the amout of curret that goes through it. Several researchers have proposed methods for optimal sizig of sleep trasistors i a give circuit to meet a performace costrait []- [4]. I [5], the authors propose a power gatig structure to support a itermediate power-savig mode ad the traditioal power cutoff mode. The idea is to add a MOS trasistor i parallel with each NMOS sleep trasistor. By applyig zero voltage to the gate of the MOS trasistor, the circuit ca be put i the itermediate power savig mode whereby leakage reductio ad data retetio are both realized. Furthermore, by trasitioig through this itermediate mode while chagig betwee sleep ad active modes, the magitude of power supply voltage fluctuatios durig power-mode trasitios is reduced. I the cut-off mode, the gate of the MOS trasistor is coected to. Noe of these works attempt to miimize the power cosumptio durig the sleep-to-active ad active-to-sleep trasitios, or reduce wake up time ad the oise geerated by the power gatig structure. I cotrast, we apply a charge recyclig techique to miimize the power cosumptio durig the mode trasitio i a power gatig structure while maitaiig, or sometimes eve improvig, the wake up time. We show that how the proposed techique also helps us reduce the groud bouce (B i the sleep to active trasitio. The remaider of this paper is orgaized as follows. I sectio, we itroduce the cocept of usig charge recyclig techique i power gatig MTCMOS circuits, ad we fid the optimal coditios to achieve the maximum ergy Savig Ratio (SR. I sectio 3, we study the effect of the threshold voltages ad sizig of the trasistors used i the trasmissio gate (T o the savig ratio ad wake up time of the circuit. I sectio 4 we aalyze the ifluece of the proposed charge recyclig techique o the wake up time, leakage ad B of the circuit. Sectio 5 represets the simulatio results, ad fially sectio 6 cocludes the paper.. CHAR RCYCLIN TCHNIQU Cosider the cofiguratio show i Figure. There are two differet blocks i the circuit; oe is power-gated by a NMOS sleep trasistor which coects the virtual groud, i.e., ode i C C Coectios betwee C ad C S Figure. Covetioal power gatig structure usig a NMOS or a MOS sleep trasistor for each circuit block.

2 the figure, to the groud, whereas the other is power-gated by a MOS sleep trasistor which coects the virtual supply, i.e., ode i the figure, to the supply. Durig the active period, sleep trasistors ad S are i the liear regio ad the voltage values of the virtual groud ad virtual supply are equal to 0 ad, respectively. Durig the sleep time, sleep trasistors ad S are tured off, ad sice they are chose to be high threshold devices, they allow very little subthreshold leakage curret to flow through them. Now, if the duratio of the sleep period is sufficietly log, all iteral odes of the gates i block C ad the virtual groud ode,, will be charged up to some voltage value very close to [6]. This is due to beig floated ad leakage curret causig its voltage level to rise toward. Similarly, if the duratio of the sleep period is log eough, all the iteral odes of C ad virtual supply ode,, will be discharged to some voltage value very close to 0. Whe the sleep-to-active trasitio edge arrives at the gates of the sleep trasistors to tur them o, starts to fall toward 0, whereas starts to rise toward. If we deote the total capacitace i the virtual groud ad supply by C ad C, respectively, we observe that durig the active-to-sleep trasitio, C is charged up from 0 to while C is discharged from to 0. The situatio is reversed for the sleep-to-active trasitio, that is, i this case C will be discharged from to 0, while C will be charged to from its iitial value of 0. These charge ad discharge evets o the virtual groud ad odes are wasteful from a circuit eergy dissipatio poit of view. Our goal is to reduce the eergy as we switch betwee active ad sleep modes of the circuit. More precisely, we propose to use a charge recyclig techique to reduce the switchig power cosumptio durig the active-to-sleep ad sleep-to-active trasitios by addig a T betwee the virtual groud ad supply odes as show i Figure. The proposed charge recyclig strategy works as follows. We tur o the T (i immediately before turig o the sleep trasistors while goig from sleep to active mode, ad (ii just after turig off the sleep trasistors while goig from active to sleep. By turig o the T at the ed of the sleep mode as the circuit is about to go from sleep to active mode, we allow charge sharig betwee the completely charged up capacitace C ad the completely discharged capacitace C. After the charge recyclig is completed, the commo voltage of the virtual groud ad virtual supply is α, where α is a positive real umber less tha. The value of α depeds o the relative sizes of C ad C. As a result of this step, power cosumptio due to switchig o the sleep trasistors is reduced. This is because i this case we have a trasitio from α to 0 at the virtual groud, ad from α to at the virtual supply; whereas i the covetioal MTCMOS circuit without the charge recyclig, the trasitio was from to 0 ad from 0 to at the virtual groud ad supply odes, respectively. A similar aalysis proves that the charge recyclig techique helps reduce power cosumptio i the trasitio from active to sleep mode as well. I the followig, we calculate the maximum achievable power savig ad the coditios we eed to achieve this maximum savig. To do this, we cosider two differet trasitios: sleep-toactive ad active-to-sleep. tt a tt s tt s0 >t s tt a0 <t a C C Coectios betwee C ad C Figure. The proposed charge recyclig cofiguratio i power gatig structures. Case A: Wake-up Trasitio I Figure 3, C ad C represet the total capacitace i the virtual groud ad supply odes, respectively. We assume that the sleep period is log eough such that C has had time to charge up to some value close to, while C has had time to completely discharge to some small value close to 0. This is a good assumptio i most circuits. Otherwise, the voltage of C ad C will be a fuctio of the legth of the sleep period. As stated earlier, to go from sleep mode to the active mode, istead of simply turig o sleep trasistors, we first allow charge recyclig betwee C ad C. To do that, we close switch M at the time tt a0. Assumig ideal charge sharig betwee C ad C, the commo voltage value of odes ad after charge sharig is calculated by equatig the total charge i both capacitaces before ad right after charge recyclig: V f _ sa αv C ( α C + C The commo voltage value of the virtual groud ad virtual supply at the ed of the charge sharig is α. After the charge sharig is complete, i.e., at time tt a, we ope switch M, ad the tur o the SN ad S sleep trasistors. As a result, there will be a path from the virtual groud to the (actual groud goig through SN which forces C to be discharged to 0. We will also have a path from the virtual supply to the (actual supply goig through S which causes C to be charged to. If we eglect the eergy cosumptio i the switch itself, for ow, the total eergy draw from the power supply is due to the process of chargig capacitace C which ca be obtaied as follows: sleep active C V ( V ( C V V V ( f _ sa Substitutig from ( for V f_sa, we obtai the eergy cosumptio from the power supply i sleep-active trasitio: sleep active V ( V αv ( α C V S C (3 Next we cosider the trasitio from active to sleep.

3 tt s tt a C C g M tt a0 <t a tt s0 >t s S C d C Figure 3. Charge recyclig techique. T is replaced by a ideal switch. C ad C are total capacitace i virtual groud ad virtual supply, respectively. Case B: Sleep Trasitio Cosider the circuit show i Figure 3. As metioed earlier, to go from active mode to the sleep mode, istead of simply turig off the sleep trasistors, we do charge recyclig betwee C ad C as soo as the circuit eters the sleep mode. I particular, we close switch M at tt s0 which is the time whe we tur off sleep trasistors. The voltage values of the virtual groud ad virtual supply odes at this time are 0 ad, respectively. Assumig ideal charge sharig betwee C ad C, the commo voltage value of odes ad after charge sharig is calculated by equatig the total charge i both capacitaces right before ad after the charge sharig: V f _ as βv C β C + C Based o the above equatio, the commo voltage value of the virtual groud ad virtual supply at the ed of the charge sharig is β. By the time the charge recyclig is complete, tt s, we ope the switch. After opeig the switch, there is a leakage path from the power supply to the virtual groud goig through logic block C which evetually causes C to be charged up to. We also have a leakage path from the virtual supply to the groud goig through logic block C which evetually causes C to be completely discharged ito the groud. Agai, if we eglect the power cosumptio i the switch, the total eergy cosumed from the power supply is due to the chargig up the capacitace C i this case, ad we ca calculate this eergy cosumptio as follows: active sleep C V ( V (5 C V V V ( Substitutig from (4 for V f_as, we obtai: active sleep f _ as V ( V βv ( β C V (4 C (6 Sice α+β, we ca calculate the total eergy cosumptio by addig active-sleep ad sleep-active which results i: cr _ total active sleep + sleepactive α C V + β C V (7 where cr-total is eergy cosumptio with charge recyclig. We ca calculate the total eergy cosumptio whe we do ot perform ay charge recyclig betwee ad, yieldig: C V + C V (8 total From (7 ad (8, ad after substitutig for α ad β from ( ad (4, we fid the eergy savig ratio (SR as follows: SR( X total cr _ total X total ( + X where X is defied as the ratio of the virtual groud capacitace to the virtual supply capacitace, or XC /C. The optimum value for X which maximizes SR(X is obtaied by equatig the derivative of this ratio to zero which results i X, or C C. I other words, i order to obtai the best eergy savig, we eed to have equal capacitaces i virtual groud ad virtual supply. The the maximum eergy savig is: (9 SRmax SR( X X 0.5 (0 This meas that we ca obtai a maximum eergy savig of 50% by usig the charge recyclig method. However, cosiderig the power eeded to tur o or off the T, the total savig ratio is less tha 50%. Figure 4 shows a example of the balaced (i.e., C C charge recyclig operatio whe trasitioig from sleep to active mode for a iverter chai i 70m CMOS techology geerated i HSIC. I this figure we ca see the virtual groud voltage, V, the virtual supply voltage, V, ad the charge recyclig sigal, V CR. 3. THRSHOLD VOLTAS AND SIZS OF TRANSISTORS IN T All the equatios we derived i the previous sectio were based o the assumptio of havig a ideal charge recyclig process betwee C ad C. Uder this sceario, we assume that o eergy is cosumed to switch the T o ad off. We also assume that the T is ON while the charge recyclig is i process. However, because of the dyamic power cosumptio i the T, ad also the possibility of havig icomplete charge sharig (cf. sectio 3., this is ot a perfect replacemet i practice. I this sectio we study the effects of the T threshold voltage ad sizig o the eergy savig ratio ad the wake up time of the charge recyclig cofiguratio. o lt g e(v V olta V(g V(d V(CR Time (s Figure 4. Charge recyclig operatio for a iverter chai i 70 m CMOS techology.

4 3. ffect of Threshold Voltage We cosider a more realistic charge recyclig sceario where we replace the ideal switch with a practical circuit model of a CMOS T. Next, we discuss the effect of trasistor threshold voltages o the power savig ad the delay of the circuit. Cosider the charge sharig cofiguratio show i Figure 5. To have a complete charge sharig, the T has to stay ON for the whole duratio of the charge sharig process. I order to have this property, the absolute values of the threshold voltages of the N ad trasistors of the T have to be small eough. To guaratee this, the commo fial voltage value of virtual groud ad virtual supply, i.e., V f, has to satisfy at least oe of the followig two iequalities: Vt, V V f or ( Vt, p V f where V t, ad V t,p deote threshold voltages of the NMOS ad MOS trasistors i the T accoutig for the body effect. Notice that V f ca be obtaied from ( for the active to sleep case ad from (4 for the sleep to active case. The iequalities guaratees that at least oe of the trasistors i the T remais ON for the complete duratio of charge sharig process. I the case of equal capacitive loads i virtual groud ad virtual supply, C C, a complete charge sharig i both active-tosleep ad sleep-to-active cases results i a commo fial voltage value of V f /, ad ( traslates ito Mi{V t,, V t,p } /. If this coditio is ot satisfied, the charge recyclig is ot complete, ad the eergy savig ratio (SR will be less tha what we have predicted. I this case, if V t V tp, we ca simply use a pass trasistor istead of a T. V (t V f V (t0 V gate_p 0 V C gate_ C V (t V f V (t00 Figure 5. Charge sharig betwee C ad C usig a T. 3. Trasmissio ate Sizig ffect Sizig of the T is aother factor that affects the SR as well as the wake up time of the circuit. I case of the origial cofiguratio whe there is ot ay charge recyclig, the wake up time may be defied as the time betwee whe we tur o the sleep trasistors to whe the voltage of the virtual groud reaches withi 0% of its fial value. However, i a circuit that uses charge recyclig, the wake up time may be defied as the time betwee whe we tur o the T to whe the virtual groud voltage goes below 0% of its fial value. I the followig discussio, we cosider the effect of the dyamic power cosumptio of the T o the eergy savig ratio, SR, which we previously calculated i sectio. Figure 6 shows the T alog with its tur o circuit. Assume a iput capacitace of C tg for the NMOS trasistor of the T ad the same iput capacitace for the MOS trasistor of the T. I 0 Figure 6. Drive circuitry for the charge recyclig T. each active-sleep-active cycle, we eed to switch o the T twice, oce before turig the sleep trasistors o, ad oce after turig them off. very time we tur the T o, we are actually turig o both NMOS ad MOS trasistors i the T, i.e., the switched capacitace is C tg. Clearly, we tur off the T after the charge sharig is complete. Therefore, we ca calculate the dyamic eergy cosumptio of the T for oe complete active-sleep cycle as follows: tg total 4 ( Ctg V 4CtgV ( Therefore, to calculate the actual eergy savig ratio (SR, we eed to subtract the correctio ratio tg-total / total from the ideal SR i (9. The correctio ratio ca be calculated as: tg total 4CtgV 4 total ( C + C V C + C C tg (3 This correctio ratio is proportioal to the size of the T, sice C tg itself is proportioal to the size of the T. However, because there are usually too may gates coected to the virtual groud ad virtual supply, C +C is usually much larger tha C tg, i.e., the correctio ratio is usually i the order of few percets which makes the actual SR to be less tha the ideal SR, 50%, by oly a few percetage poits. By icreasig the size of the T, we ca speed up the charge sharig process, ad as a result, reduce the wake up time; however, this will also icrease the correctio ratio give i (3, hece, decreasig the eergy savig ratio of the circuit. Therefore, there is a trade off betwee the wake up time ad eergy savig ratio. 4. WAK U TIM, LAKA AND ROUND BOUNC ANALYSIS We aalyze three importat issues i power gatig structures, amely the wake up time, leakage currets, ad B for our proposed charge recyclig MTCMOS cofiguratio. 4. Wake Up Time I charge recyclig MTCMOS, the larger the T size is, the smaller the wake up time of the circuit is. The icreased size, however, icreases the dyamic power cosumptio of the T. If we use a large eough T, we ca make the charge sharig time small eough such that we obtai a wake up time which is as small as, or sometimes eve less tha, that of the origial circuit where we do ot use ay charge recyclig. However, as see from equatio (, by icreasig the size of the T, we are also icreasig its eergy cosumptio. Our experimets o a umber of real circuits demostrate that the size we eed for the T i order to maitai, or sometimes improve, the origial wake up time is such that we will loose oly a very small percetage of the ideal SR.

5 4. Leakage Cosider Figure 7 a where r ad r represet resistaces of logic blocks C ad C, respectively, ad R N ad R represet resistaces of NMOS ad MOS sleep trasistors, respectively. For covetioal MTCMOS cofiguratio, durig the sleep period, there exist two differet paths from to groud. Sice C ad C cosist of LVT trasistors, ad sleep trasistors are HVT trasistors, we ca assume that R N, R >> r, r. Without loss of geerality, ad to simplify the discussio, we assume that R N R R. The total resistace from the power supply to the groud is thus R total-cov. R/, ad the leakage power cosumptio is calculated as: V leakage cov. (4 R Next we calculate leakage power cosumptio for the charge recyclig (CR MTCMOS cofiguratio. As see i Figure 7 b, i this case, there is a ew path from to the groud goig through r, RT ad r. As we metioed earlier, sice C ad C cosist of LVT trasistors, r ad r are small resistaces. I order to avoid havig a high leakage path from the power supply to the groud, we have to make RT as large as possible; this is possible by usig HVT trasistors i the T. Let s assume that R T R for some. Kowig that R >> r, r, ad by doig -Y trasformatio for r, RT ad R, we arrive at the ew resistive etwork show i Figure 7 c where r *, r * * ad r 3 are calculated as: * r R r r r + RT + R + * r RT r r (5 r + RT + R + * RRT r3 R r + R + R + T Total resistace from the supply to groud is calculated as: Rtotal CR R (6 + The leakage power i this case ca be writte as: leakagecr V + R (7 As see from (7, the leakage power cosumptio has icreased by a factor of (+/ compared to the covetioal power gatig method. If R T R, is equal to, ad we have a 5% icrease i the leakage power. If the sleep period of the circuit is small, the this 5% icrease i leakage eergy cosumptio is egligible compared to the 50% switchig eergy savig that we achieve by usig the charge recyclig MTCMOS structure. O the other had, if the sleep period is very log, we must use larger by icreasig resistace of the T. This is possible by choosig trasistors with smaller W/L ratios i the T (which is also beeficial from the layout area poit of view. The potetial disadvatage is that the charge cyclig will take loger time to complete ow sice the T will have a larger ON resistace. 4.3 roud Bouce roud ad power lie bouces are oe of the most importat desig cocers with regard to power gatig structures [6][7]. B occurs i power gatig structures at the sleep to active trasitio edge. Cosider Figure 8. After we tur o the sleep trasistor at the r R N R r r R N r R R T r r * R N (a (b (c r * r r * 3 Figure 7. (a Leakage paths for a covetioal MTCMOS structure, (b Leakage paths for CR MTCMOS structure (c - Y coverted model of (b. ed of the sleep period, a large amout of curret flows ito the groud. We adopt a simple RL model for the purpose of B aalysis. Because of the large di/dt at the tur-o time, there is a large voltage, Ldi/dt, appearig across the iductace. We ext study the effect of the proposed charge recyclig techique o the B of the circuit. Figure 8 shows the virtual groud capacitace, C, coected to the RL circuit (modelig the pi-package parasitics of the IC, via the sleep trasistor,. We tur o the sleep trasistor at t0, ad assume that the iitial voltage of C at this time is V 0, i.e., V (t0v 0. Based o the results of referece [8], the positive peak value of the B occurs durig the time whe operates i the saturatio regio. Although the peak value does ot deped o voltage V 0, it depeds o R, L, C, V T ad values. Therefore, we expect that the proposed charge recyclig techique, which simply chages V 0 from to /, does ot chage the positive peak value of the B. However, the egative peak value of the B, ad the B settlig time both deped o V 0 [8]. Furthermore, both of these quatities decrease as V 0 is reduced. Therefore, both the egative peak value, ad the settlig time of the B voltage are expected to decrease for the charge recyclig MTCMOS. Degrees of improvemet i the egative peak ad settlig time are depedet o the relative values of L, C, R,, ad the sleep trasistor parameters. Figure 9 compares B waveforms resultig from covetioal ad charge recyclig power gatig structures for a iverter chai i 70m CMOS techology. As expected, the positive peak value remais the same for both cases; however, the egative peak value ad the settlig time are smaller for the charge-recyclig MTCMOS structure. t0 L R C + V (t0v 0 Figure 8. RL equivalet model of the groud used to aalyze B effect i MTCMOS. -

6 o lt g e(v V olta L ie d rou Covetioal Charge Recyclig Time (s Figure 9. B waveforms i covetioal ad CR structures for a iverter chai usig 70m CMOS techology. 5. SIMULATION RSULTS We used HSIC to fid the wake up time ad eergy cosumptio durig mode trasitio for a umber of circuits from ISCAS bechmark suite for a 90m CMOS techology. Table shows the experimetal results i terms of the wake up time ad eergy cosumptio for a umber of bechmarks whe we use the covetioal MTCMOS as well as the charge recyclig MTCMOS. We observe from the table that eergy savig durig the mode trasitio is always more tha 40% while the wake up time usually remais the same or improves slightly. However, for some cases e.g., C908, we see that the eergy savig ratio is 46% which is still more tha 40%, but the wake up time has bee icreased by about 4%. 6. CONCLUSIONS I this paper we itroduced the cocept of charge recyclig (CR i MTCMOS circuits. We showed that by applyig the proposed CR techique to the MTCMOS circuits, we ca save up to 50% of the mode trasitio eergy while maitaiig the wake up time of the origial circuit. We also showed that by usig the proposed techique, we ca reduce the egative peak voltage value ad the settlig time of the groud bouce. Although leakage i the sleep mode of the circuit ca go up as a result of the CR structure, the effect ca be very well cotrolled by sizig dow the T, by judiciously selectig the HVT level to be used for both sleep trasistors ad charge recyclig T trasistors i the first place, or eve by usig higher V t values for the trasistors i the T compared to those for the sleep trasistors. Sice the subthreshold leakage curret of a MOS trasistor is expoetially depedet o the threshold voltage of the trasistor, a slight icrease i the threshold voltage value of the T will result i a large differece i the resistace value of the gate, or i a large value i equatio (7, which makes the icrease i the leakage power cosumptio egligible. 7. ACKNOWLDMNTS The authors would like to thak Tom Sidle, the V of Advaced CAD Techology at Fujitsu Labs of America, for his support. Circuit 9Sym C43 C355 C908 Table. Wake up time ad eergy cosumptio results. Wake up Time (pico secod Mode Trasitio ergy Cos. (pico Jules Cov. CR Cov. CR ergy Savig Wake up Time Reductio 6 45% 0.9% % 3% 7. 40% 5% % -3% C % 0.9% C % -3% C % 0.% C %.5% C % -4% 8. RFRNCS [] J. Kao, S. Naredra, ad A. Chadrakasa, Subthreshold leakage modelig ad reductio techiques, roc. ICCAD, pp. 4 48, Nov. 00. [] J. Kao, A. Chadrakasa ad D. Atoiadis, Trasistor Sizig Issues ad Tool for Multi Threshold CMOS Techology, roc. DAC, pp , 997. [3] J. Kao, S. Nareda ad A. Chadrakasa, MTCMOS hierarchical sizig based o mutual exclusive discharge patters, roc. DAC, pp , 998. [4] M. Ais, S. Areibi, M. Mahmoud ad M. lmasry, Dyamic ad leakage power reductio i MTCMOS circuits usig a automated efficiet gate clusterig techique, roc. DAC, pp , 00. [5] S. Kim, S.V. Kosoocky, D. R. Kebel, ad K. Stawiasz, xperimetal measuremet of a ovel power gatig structure with itermediate power savig mode, roc. ISLD, pp. 0-5, 004. [6] A. Abdollahi, F. Fallah ad M. edram, A effective power mode trasitio techique i MTCMOS, roc. DAC, pp. 37-4, 005. [7] S. Kim, S.V. Kosoocky, Stephe, ad D.R. Kebel, Uderstadig ad miimizig groud bouce durig mode trasitio of power gatig structures, roc. ISLD, pp. - 5, 003. [8]. Heydari ad M. edram, roud bouce i digital VLSI circuits, I Tras. o VLSI systems, pp , Apr. 003.