Week 5, Lectures 12-14, February 12-16, 2001

Transcription

1 Week 5, Lectures 1-14, February 1-16, 001 EECS 105 Microelectroics Devices a Circuits, Sri 001 Arew R. Neureuther Toics: M:NMOS sall-sial a two-ort; PMOS sall-sial a CMOS two-ort W: Caacitace/Layout ( orer hysics) F: HW Quiz a review Aalo Iterate Circuits Reai for week: M: 8.3, 4.5.6, 5.3; W: 4.5.4, 4.5.5, 4.6 (4.4.1, 4.4.) F: oly review Versio /13/01

2 NMOS: Lare Sial Moel V T V TO cutoff I D 0 trioe VGS V VT W I D µ C OX 1+ L saturatio V VGS VT 1 W I D µ COX VGS VT 1+ λv L Aalo Iterate Circuits ( ) φ V φ + γ VGS V T [ V ( )]( ) GS V T V / λ V V ( ) ( ) Tyical values: V T 1V µ C OX 50 µa/v W/L 4 γ 0.6V -1/ λ 0.1V -1 See. 39 a Table

3 Alterate View 600 i D (v GS, V 4 V) i D i Q i / v s (µa) v GS V GS 3 V v GS V GS + v s v GS (V) Aalo Iterate Circuits

4 Sall-Sial Ters as Derivatives Aalo Iterate Circuits i i i I D + i I D + vgs + v + v + GS trascouctace GS i v + v + b i GS backate trascouctace outut couctace b o i i o v H. O. T. Alebraic exressios ee uo the curret equatio for the reio of oeratio.

5 NMOS Sall-Sial Moel o 1 r i o GS i W, trioe µ OX, Q L W W µ C [ V V V ] o, trioe COX GS, Q T, Q, Q L V ( V V )( V ), sat µ COX GS, Q T 1+ λ, Q L W W µ ( V ) GS, Q VT COXI D, Q, sat COX µ L L o, sat 1 W L OX ( ) VGS Q VT Q λ λi D Q µ C, λ 0, λ 0, Aalo Iterate Circuits

6 Backate Effect: via Chai Rule b i i V T V T i V GS V T V T I W µ COX L [ VGS VT ( V / )] V b V T γ φ V φ γ V Aalo Iterate Circuits

7 Sall-Sial Moel: Su Currets ate source v s Aalo Iterate Circuits i v + v + v bs GS boy Coratulatios o a four terial oel! b v s o v b v bs r o i Three currets > three arallel aths rai

8 Two-Port for Resistive Loa MOS v i r i v i r out v i v i r out r o R D Geeral two-ort Aalo Iterate Circuits Secific two-ort

9 PMOS: I D vs. V a Reios (trioe V SD < V SG +V T ) (saturatio V SD > V SG +V T ) Aalo Iterate Circuits (cutoff V SG < -V T )

10 PMOS Lare-Sial Moel V T V TO cutoff I D 0 trioe V SD VSG + VT W I D µ C OX 1+ L saturatio V SD VSG + VT 1 W I D µ COX VSG + VT 1+ λ VSD L Aalo Iterate Circuits ( ) φ V φ γ VSG V T SB [ V ( )]( ) SG + V T V SD / λ V SD V SD Tyical values: V T -1V µ C OX 5 µa/v W/L 4 γ 0.6V -1/ λ 0.1V -1 ( ) ( ) See. 37 a Table

11 b o PMOS Sall-Sial Moel ( i ) 1 r o SG, sat ( i ) ( i ) SD W W µ COX SG, Q T µ L L b o, sat 1 γ W L φ ( V + V ) C ( I ) V SB µ COX OX ( ) VSG, Q + VT, Q λ λ I D, Q D Aalo Iterate Circuits

12 PMOS Sall-Sial Circuit i v + v + SG b SB o v SD source ate v s v bs v s b v sb r o -i rai boy Aalo Iterate Circuits

13 CMOS Iverter Circuit -i,os 5V source ate PMOS Moels v s ( V V ) ( λ V ) W I D µ COX SG T 1+ L SD v bs v s b v sb r o -i boy rai v i i,os v out NMOS Moels I W µ COX GS T 1+ L ( V V ) ( λ V ) ate source v s v bs v s b v bs i rai r o boy Aalo Iterate Circuits

14 CMOS Iverter: Lare Sial I I D, NMOS I D, PMOS Set V GS V IN 0 V 0 Relace source, rai a V V OUT 0 V SB 5 5 ate voltaes with circuit VSG 5 V IN 0 voltaes VSD 5 V OUT Deterie oe NMOS a PMOS a lu i D D 1 W COX VGS VT L 1 W COX SG T L ( ) ( λ ) µ 1+ ( V + V ) ( λ V ) I µ 1+ V SD Aalo Iterate Circuits

15 CMOS Iverter: Sall-Sial source ate v s a.c. v bs v s 0 b v sb ro -i rai v i ate source v s v bs a.c. boy v s 0 b v bs i rai r o v out boy Aalo Iterate Circuits

16 CMOS Iverter s.s. Solutio v i v i r o v i r o v out Noe Equatio v v out i 0 vout vi + + vi + r ( + )( r r ) o o o ( + ) o v r + out o o Aalo Iterate Circuits