Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) Prof. Ali M. Niknejad Prof. Rikky Muller

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1 EECS 105 Spring 2017, Modue 3 Meta Oxide Semiconductor Fied Effect Transistors (MOSFETs) Prof. Ai M. Niknejad Prof. Rikky Muer Department of EECS University of Caifornia, Berkeey

2 Announcements Prof. Rikky Muer Pick up Midterm 1 if you haven t aready! Two options: (1) from my office hours, or (2) from ecture today 2 University of Caifornia, Berkeey

3 MOSFET Cross Section Prof. Rikky Muer gate body source drain diffusion regions p+ n+ n+ L p-type substrate 3 Add two junctions around MOS capacitor The regions forms PN junctions with substrate MOSFET is a four termina device The body is usuay grounded (or at a DC potentia) For ICs, the body contact is at surface University of Caifornia, Berkeey

4 MOSFET Layout Prof. Rikky Muer B S G D contact B S G D poy gate p+ n+ n+ L x j W p-type substrate L 4 Panar process: compete structure can be specified by a 2D ayout Design engineer can contro the transistor width W and L Process engineer contros t ox, N a, x j, etc. University of Caifornia, Berkeey

5 PMOS & NMOS Prof. Rikky Muer B S G D B S G D p+ n+ n+ L x j n+ p+ p+ L x j p-type substrate n-type substrate NMOS PMOS 5 A MOSFET by any other name is sti a MOSFET: NMOS, PMOS, nmos, pmos NFET, PFET IGFET Other favors: JFET, MESFET CMOS technoogy: The abiity to fabricate NMOS and PMOS devices simutaneousy University of Caifornia, Berkeey

6 CMOS Prof. Rikky Muer B S G D B S G D p+ n+ n+ L x j n+ p+ p+ L x j n-type we NMOS PMOS p-type substrate 6 Compementary MOS (CMOS): Both P and N type devices Create a n-type body in a p-type substrate through compensation. This new region is caed a we. To isoate the PMOS from the NMOS, the we must be reverse biased (p-n junction) University of Caifornia, Berkeey

7 Circuit Symbos Prof. Rikky Muer NMOS PMOS The symbos with the arrows are typicay used in anaog appications The body contact is often not shown The source/drain can switch depending on how the device is biased (the device has inherent symmetry) 7 University of Caifornia, Berkeey

8 Circuits! Prof. Rikky Muer 8 When the inventors of the bipoar transistor first got a working device, the first thing they did was to buid an audio ampifier to prove that the transistor was actuay working! University of Caifornia, Berkeey

9 A Simpe Circuit: An MOS Ampifier Prof. Rikky Muer Input signa RD VDD Suppy Rai v o v s I DS vgs = VGS + vs V GS Output signa 9 University of Caifornia, Berkeey

10 Pot of Output Waveform (Gain!) Prof. Rikky Muer output input mv 10 University of Caifornia, Berkeey

11 Prof. Rikky Muer Observed Behavior: I D -V GS I DS I DS V DS V GS 11 Current zero for negative gate votage Current in transistor is very ow unti the gate votage crosses the threshod votage of device (same threshod votage as MOS capacitor) Current increases rapidy at first and then it finay reaches a point where it simpy increases ineary V T V GS University of Caifornia, Berkeey

12 Prof. Rikky Muer Observed Behavior: I D -V DS IDS / k VGS = 4V non-inear resistor region constant current I DS V DS resistor region VGS = 3V V GS VGS = 2V V DS 12 For ow vaues of drain votage, the device is ike a resistor As the votage is increases, the resistance behaves non-ineary and the rate of increase of current sows Eventuay the current stops growing and remains essentiay constant (current source) University of Caifornia, Berkeey

13 Operating Points Prof. Rikky Muer Input signa RD VDD Suppy Rai v o v s I DS vgs = VGS + vs V GS Output signa 13 Which bias votages you operate the MOSFET at wi make a big difference in how it functions. We wi expore these regions of operation in this ecture. If we operate with a sufficienty high V GS AND a sufficienty high V DS, we can make a very good sma-signa ampifier! University of Caifornia, Berkeey

14 Sma Signa vs. Large Signa Prof. Rikky Muer I DS I DS V DS V GS V T V GS We observe I DS vs. V GS to be quadratic for V GS > V T Large changes in v GS resut in quadratic changes at the output However, for sma changes in v GS (denoted as v gs ) wi produce inear changes at the output! We can show this using Tayor series expansion: i DS = k(v GS V T ) 2 ;v GS = V GS + v gs 14 TS :i DS (v GS ) VGS = k(v GS V T ) k(V GS V T )v gs + kv gs University of Caifornia, Berkeey

15 Simpe Sma Signa Mode for MOSFET Prof. Rikky Muer NMOS 15 This is a simpified, 3-termina sma-signa mode for a MOSFET In ater ectures we wi deveop a more compete mode g m = transconductance defined as di ds /dv gs, units [Ohms] -1 r o = output resistance defined as [di ds /dv ds ] -1, units Ohms University of Caifornia, Berkeey

16 Sma Signa Gain Exampe Prof. Rikky Muer Input signa RD VDD Suppy Rai v o v s I DS vgs = VGS + vs V GS Output signa 16 Steps to anayze sma signa ampifiers: 1. Cacuate bias points using DC sources As you wi see in ater ecture, you wi use these bias points to determine the MOSFET region of operation as we as to cacuate sma-signa parameters 2. Turn off DC sources 3. Pug in the sma-signa mode for a MOSFET University of Caifornia, Berkeey

17 Sma Signa Gain Exampe Prof. Rikky Muer Cacuate the gain (v out /v in ) of the circuit University of Caifornia, Berkeey

18 EECS 105 Spring 2017 MOSFET Large Signa Modes and Regions of Operation Department of EECS University of Caifornia, Berkeey

19 Prof. Rikky Muer Cut-off, V GS < V T 19 p+ NMOS V GS <V T S n+ n+ p-type G Depetion Region 100mV This structure shoud ook famiiar! It is an MOS capacitor with two n+ diffusion regions on each side. When V GS < V T, the device is either in accumuation or in depetion. Since there are no (or few) inversion charges at the surface, therefore no current wi fow regardess of the vaue of V DS. University of Caifornia, Berkeey D VDS x y

20 Linear Region Current Prof. Rikky Muer p+ NMOS V GS >V T S p-type G n+ n+ D Inversion ayer channe VDS 100mV x y 20 If the gate is biased above threshod, the surface is inverted This inverted region forms a channe of inversion charges (in this case eectrons) that connects the drain and source inversion charges originate from n+ diffusion If a drain-source votage (V DS ) is appied positive, eectrons wi fow from source to drain Note: eectrons fow S à D, current fows D à S University of Caifornia, Berkeey

21 MOSFET Linear Region Prof. Rikky Muer The current in this channe is given by I = Wv Q DS y N The charge proportiona to the votage appied across the oxide over threshod Q = C ( V V ) N ox GS Tn 21 I = Wv C ( V V ) DS y ox GS Tn If the channe is uniform density, ony drift current fows v V y = µ ne DS y Ey = W I = DS ncox ( VGS VTn) VDS VGS > VTn L µ VDS 100mV L University of Caifornia, Berkeey

22 MOSFET: Variabe Resistor Prof. Rikky Muer Notice that in the inear region, the current is proportiona to the votage I = W C ( V V ) V L µ DS n ox GS Tn DS Can define a votage-dependent resistor R eq VDS 1 L L = = = RW( VGS ) I µ C ( V V ) W W DS n ox GS Tn This is a nice variabe resistor, eectronicay tunabe! 22 University of Caifornia, Berkeey

23 Finding I D = f (V GS, V DS ) Prof. Rikky Muer Approximate inversion charge Q N (y): drain votage is higher than the source à ess charge at drain end of channe V GS > V Tn S G D V DS p+ n+ n+ VGS VTn p-type NMOS 23 y=0 y=l University of Caifornia, Berkeey

24 Inversion Charge at Source/Drain Prof. Rikky Muer Q ( y) Q ( y = 0) + Q ( y L) N N N = Q N ( y Tn = 0) = Cox( VGS V ) Q N ( y = L) = C V V ) ox( GD Tn V GD = V GS V DS 24 University of Caifornia, Berkeey

25 Average Inversion Charge Prof. Rikky Muer Source End Drain End Cox( VGS VT ) + Cox( VGD VT ) QN ( y) 2 Cox( VGS VT ) + Cox( VGS VSD VT ) QN ( y) 2 Cox(2VGS 2 VT ) CoxVSD VDS QN( y) = Cox( VGS VT ) 2 2 Charge at drain end is ower since the vertica fied is ower at that point 25 University of Caifornia, Berkeey

26 Drift Veocity and Drain Current Prof. Rikky Muer Use mobiity to find veocity v Substituting: µ nvds vy ( ) = µ ney ( ) µ n( ΔV/ Δ y) = L VDS VDS ID = WvQN Wµ Cox( VGS VT ) L 2 I D = W L µc ox (V GS V T V DS 2 )V DS Famiy of Inverted Paraboas 26 University of Caifornia, Berkeey

27 Square-Law Characteristics Prof. Rikky Muer Boundary: what is I D,SAT? TRIODE REGION 27 University of Caifornia, Berkeey

28 The Saturation Region Prof. Rikky Muer When V DS > V GS V Tn, there isn t any inversion charge at the drain what happens? SATURATION REGION Why do curves fatten out? 28 University of Caifornia, Berkeey

29 Why does current saturate? Prof. Rikky Muer The charge at drain end goes to zero once V GD < V T We say that the drain end is pinched off If you pinch a hose, water fow stops! But then how does current fow? 29 University of Caifornia, Berkeey

30 Pinch Off Prof. Rikky Muer Excess fied beyond E dsat drops across tiny region between drain and channe Huge fied means that eectrons fow at very high veocity across the high fied region. They are injected from source end and are coected at the drain end Increasing the drain votage does not increase current (appreciaby) because the current is imited by the suppy of eectrons from channe side 30 University of Caifornia, Berkeey

31 Square-Law Current in Saturation Prof. Rikky Muer Current stays at maximum (where V DS = V GS V Tn = V DS,SAT ) W VDS I = C ( V V ) V L µ 2 D ox GS T DS W VGS VT IDS, sat Cox ( VGS VT )( VGS VT ) L µ = 2 W µ Cox 2 IDS, sat = ( VGS VT ) L 2 31 University of Caifornia, Berkeey

32 Actua Saturation Current Prof. Rikky Muer Measurement: I D increases sighty with increasing V DS : The physics is compicated, but a simpe way to see this is that the channe is getting shorter as the drain votage depetes away more eectrons from the drain end We mode this with an additiona inear factor: W µ C I V V V L 2 ox 2 DS, sat = ( GS T ) (1 +λ DS ) 32 University of Caifornia, Berkeey

33 Channe Length Moduation Prof. Rikky Muer When v DS = v GS -V T, the channe pinches off near the drain. With further increase in v DS, the pinch-off point moves toward the source, effectivey reducing the channe ength from L to L-ΔL. I D = 1 2 µ C W n ox ( L ΔL V V GS T ) 2 The continua increase of I D with V DS is modeed by I D = 1 2 µ n C ox W ( L V V GS tn) 2 ( 1+ λv DS ) 33 University of Caifornia, Berkeey

34 Summary: Regions of Operation Prof. Rikky Muer Cut-off: V GS < V T I DS = 0 Note: this is an approximation we wi make in EE105, in ater courses you wi earn about sub-threshod conduction Linear: V GS > V T, V DS << V GS V T I DS = W L µ n C ox (V GS V T )V DS 34 Triode: V GS > V T, V DS < V GS V T I DS = W L µ C (V V V DS n ox GS T 2 )V DS Saturation: V GS > V T, V DS > V GS V T W µ C I V V V L 2 ox 2 DS, sat = ( GS T ) (1 +λ DS ) University of Caifornia, Berkeey

35 PMOS Device Prof. Rikky Muer So far, we ve derived a of our equations for an NMOS device PMOS devices work exacty the same way, but with an n-type body and a channe made of positive charges (hoes) The direction of the votages and currents are inverted, for exampe: I SD,sat = W L µc ox 2 (V SG V Tp )2 (1+ λv SD ) 35 University of Caifornia, Berkeey

36 Next Lecture Prof. Rikky Muer In the next ecture we wi earn how to anayze sma-signa ampifiers, incuding Computation of bias points How to derive and compute sma signa mode parameters (g m, r o ) How to cacuate sma signa gain 36 University of Caifornia, Berkeey