EE105 - Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues
|
|
- Blaise Butler
- 6 years ago
- Views:
Transcription
1 EE105 - Fall 006 Microelectronic evices and Circuits Prof. Jan M. Rabaey (jan@eecs Lecture 8: MOS Small Signal Model Some Administrative Issues REIEW Session Next Week Tu Sept 6 6:00-7:30pm; 060 alley LSB MITERM 1 next week Th will cover everything up to and including MOSCAP Th Sept 8 6:30-8pm; Sibley Auditorium Some old midterm posted on website 1
2 Overview Last lecture MOS Capacitor; MOS Transistor Intro This lecture MOS Transistor (cntd Small signal model 3 MOSFET: Observed Behavior: I - I / k = 4 non-linear resistor region constant current I resistor region = 3 = For low values of drain voltage, the device is like a resistor As the voltage is increases, the resistance behaves non-linearly and the rate of increase of current slows Eventually the current stops growing and remains essentially constant (current source 4
3 Linear Region Current p+ NMOS > S n+ n+ p-type G Inversion layer channel 100m If the gate is biased above threshold, the surface is inverted This inverted region forms a channel that connects the drain and gate If a drain voltage is applied positive, electrons will flow from source to drain x y 5 MOSFET Linear Region The current in this channel is given by I = Wv Q y N The charge proportional to the voltage applied across the oxide over threshold Q = C ( N ox I = Wv C ( y ox If the channel is uniform density, only drift current flows v L y = μne y Ey = W I = ncox( > L μ 100m 6 3
4 MOSFET: ariable Resistor Notice that in the linear region, the current is proportional to the voltage I = W C ( L μ n ox Can define a voltage-dependent resistor R eq 1 L L = = = R ( I μ C ( W W n ox This is a nice variable resistor, electronically tunable! 7 Finding I = f (, Approximate inversion charge Q N (y: drain is higher than the source less charge at drain end of channel 8 4
5 Inversion Charge at Source/rain ( Q Q ( y = 0 + Q ( y = L / N N N Q N ( y = 0 = Cox ( Q N ( y = L = C ox ( G G = 9 Average Inversion Charge Source End rain End Cox( T + Cox( G T QN ( y Cox ( T + Cox ( T QN ( y Cox ( T CoxS QN( y = Cox( T Charge at drain end is lower since field is lower Simple approximation: In reality we should integrate the total charge minus the bulk depletion charge across the channel 10 5
6 rift elocity and rain Current Long-channel assumption: use mobility to find v Substituting: μn vy ( = μney ( μn( Δ/ Δ y = L I = WvQN Wμ Cox( T L W I C ( L μ ox T Inverted Parabolas 11 Square-Law Characteristics TRIOE REGION Boundary: what is I,SAT? SATURATION REGION 1 6
7 The Saturation Region When >, there isn t any inversion charge at the drain according to our simplistic model Why do curves flatten out? 13 Square-Law Current in Saturation Current stays at maximum (where = =,SAT W I = C ( L μ ox T W T I, sat Cox( T ( T L μ = W μcox I, sat = ( T L Measurement: I increases slightly with increasing model with linear fudge factor W μc I L ox, sat= ( T(1 +λ 14 7
8 Pinching the MOS Transistors epletion Region > S G p+ n+ n+ p-type NMOS Pinch-Off Point When >,sat, the channel is pinched off at drain end (hence the name pinch-off region rain mobile charge goes to zero (region is depleted, the remaining electric field is dropped across this high-field depletion region As the drain voltage is increases further, the pinch off point moves back towards source Channel Length Modulation: The effective channel length is thus reduced higher I 15 Short-Channel MOSFET Model Channel (inversion charge: neglect reduction at drain elocity saturation defines,sat =E sat L = constant rain current: -v sat / μ n I = WvQ = W ( v [ C (, SAT N sat ox E sat = 10 4 /cm, L = 0.1 μm,sat = 0.1! ], I = v WC ( (1 + λ, SAT sat ox n 16 8
9 Linear I- Characteristics: short-channel MOSFET 17 I versus 6 x Resistive =.5 Saturation = x =.5 =.0 I (A 3 = - T = 1.5 I (A 1 = = = ( Long Channel ( Short Channel 18 9
10 A Simple Circuit: An MOS Amplifier v in Input signal R Supply Rail v O = O + v o v = + v s v s i = I + i ds Output signal v o 19 Large Signal Analysis OUT = = I R Load Line 0 10
11 Sweep Input oltage v IN + MOSFET is saturated high slope v O = v MOSFET is triode low slope 0 (negative supply, SS = 0 v IN = v 1 Finding the Input Bias oltage Hand calculation: use I,SAT I W μ C = L n ox, SAT ( Typical numbers: W = 40 μm, L = μm, R = 5 kω μ n C ox = 100 μa/, = 1, = 5 I 1 = = = I, SAT = ( 1 R Want ~.5: I,SAT = /R = 0.1mA, =
12 Applying the Small-Signal oltage Approach 1. Just use v IN in the equation for the total drain current i and find v OUT v = v = + v v s IN ( t = cos( ωt sm s Result: v OUT = R i = R W μnc L ox ( + v s 3 Solving for the Output oltage v OUT v OUT = R W μ ( 1 ncox vs + L I v OUT = R I 1+ vs 4 1
13 Output oltage v O = v t 0 v IN = v t 5 Small-Signal Case Linearize the output voltage for the small-signal case: Expand (1 + x = 1 + x + x last term can be dropped when x << vs v s = 1+ v s + vs 6 13
14 Linearized Output oltage For this case, the total output voltage is v O = = ( R I = O R + v o I vs 1+ RI The output voltage is the sum of the C voltage O and the smallsignal voltage v o. RI vo = v RI A = s = A v s v s 7 Plot of Output Waveform (Gain! Numbers: / ( T = 5/ 0.3 = 16 output input m 8 14
15 There is a Better Way! What s missing: didn t include device output impedance or charge storage effects (must solve nonlinear differential equations Approach. o problem in two steps. C voltages and currents (ignore small signals sources: set bias point of the MOSFET... we had to do this to pick already Substitute the small-signal model of the MOSFET and the smallsignal models of the other circuit elements This constitutes small-signal analysis 9 An MOS Amplifier Input signal R Supply Rail v o v s I v = + vs Output signal 30 15
16 Small-Signal Analysis Step 1. Find C Bias ignore small-signal source I,Q,BIAS 31 Which Operating Region? TRIOE = = 3 3 SAT OFF 3 16
17 I / k Changing One ariable at a Time Square Law Saturation Region = 3 = 1 T Linear Triode Region Slope of Tangent: Incremental current increase Assumption: >,SAT = (square law 33 The Transconductance g m efined as the change in drain current due to a change in the gate-source voltage, with everything else constant W μc I L ox, sat = ( T (1 +λ Δi i W g = = = μc ( (1 + λ m ox T Δv v L,, 0 W gm = μcox ( T L Gate Bias W I W g = μc = μc I L W μc L ox L m ox ox g m I = ( T rain Current Bias rain Current Bias and Gate Bias 34 17
18 Output Resistance r o efined as the inverse of the change in drain current due to a change in the drain-source voltage, with everything else constant Non-Zero Slope δ I δ 35 Evaluating r o W μc i L ox = ( T (1 +λ o = v, r i r0 = W μc L ox 1 1 ( λ 1 r0 λi T 36 18
19 Total Small Signal Current i ( t = I + i ds i i i = v + v ds gs ds vgs vds 1 i = g v + v r ds m gs ds o Transconductance Conductance 37 Putting Together a Circuit Model 1 i = g v + v r ds m gs ds o 38 19
EE105 - Fall 2006 Microelectronic Devices and Circuits
EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationEE105 - Fall 2005 Microelectronic Devices and Circuits
EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More informationAnnouncements. EE105 - Fall 2005 Microelectronic Devices and Circuits. Lecture Material. MOS CV Curve. MOSFET Cross Section
Announcements EE0 - Fall 00 Microelectronic evices and Circuits ecture 7 Homework, due today Homework due net week ab this week Reading: Chapter MO Transistor ecture Material ast lecture iode currents
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated
More informationToday s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
- Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationLecture 11: MOS Transistor
Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout
More informationECE315 / ECE515 Lecture-2 Date:
Lecture-2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS I-V Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cut-off Linear/Triode
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing
More informationLecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson
Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal
More information3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti
Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +
More informationPractice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
More informationChapter 13 Small-Signal Modeling and Linear Amplification
Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors
More informationEE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors
EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationLecture 28 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 18, 2007
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 28-1 Lecture 28 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 18, 2007 Contents: 1. Second-order and
More informationLecture 18. Common Source Stage
ecture 8 OUTINE Basic MOSFET amplifier MOSFET biasing MOSFET current sources Common source amplifier eading: Chap. 7. 7.7. EE05 Spring 008 ecture 8, Slide Prof. Wu, UC Berkeley Common Source Stage λ =
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationImportant! EE141- Fall 2002 Lecture 5. CMOS Inverter MOS Transistor Model
- Fall 00 Lecture 5 CMO Inverter MO Transistor Model Important! Lab 3 this week You must show up in one of the lab sessions this week If you don t show up you will be dropped from the class» Unless you
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationMOS Transistor I-V Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationLecture 10 MOSFET (III) MOSFET Equivalent Circuit Models
Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;
More informationSECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University
NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationMOSFET Physics: The Long Channel Approximation
MOSFET Physics: The ong Channel Approximation A basic n-channel MOSFET (Figure 1) consists of two heavily-doped n-type regions, the Source and Drain, that comprise the main terminals of the device. The
More informationECEN474/704: (Analog) VLSI Circuit Design Spring 2018
ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & Mixed-Signal Center exas A&M University Announcements If you haven t already, turn in your 0.18um
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationIntroduction and Background
Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat Abu-Taha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments
More informationChapter 4 Field-Effect Transistors
Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationLong Channel MOS Transistors
Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended to Metal-Oxide-Semiconductor Field-Effect transistors (MOSFET) by considering the following structure:
More informationQuantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.
Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More informationLecture 11: J-FET and MOSFET
ENE 311 Lecture 11: J-FET and MOSFET FETs vs. BJTs Similarities: Amplifiers Switching devices Impedance matching circuits Differences: FETs are voltage controlled devices. BJTs are current controlled devices.
More informationLecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.)
Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.) Outline 1. The saturation region 2. Backgate characteristics Reading Assignment: Howe and Sodini, Chapter 4, Section 4.4 6.012 Spring 2009 Lecture
More informationECE315 / ECE515 Lecture 11 Date:
ecture 11 Date: 15.09.016 MOS Differential Pair Quantitative Analysis differential input Small Signal Analysis MOS Differential Pair ECE315 / ECE515 M 1 and M are perfectly matched (at least in theory!)
More informationLecture 10 MOSFET (III) MOSFET Equivalent Circuit Models
Lecture 1 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;
More informationMOS Transistor. EE141-Fall 2007 Digital Integrated Circuits. Review: What is a Transistor? Announcements. Class Material
EE-Fall 7 igital Integrated Circuits MO Transistor Lecture MO Transistor Model Announcements Review: hat is a Transistor? Lab this week! Lab next week Homework # is due Thurs. Homework # due next Thurs.
More informationEE 330 Lecture 17. MOSFET Modeling CMOS Process Flow
EE 330 Lecture 17 MOSFET Modeling CMOS Process Flow Review from Last Lecture Limitations of Existing Models V DD V OUT V OUT V DD?? V IN V OUT V IN V IN V DD Switch-Level Models V DD Simple square-law
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationFIELD-EFFECT TRANSISTORS
FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation
More informationECE606: Solid State Devices Lecture 23 MOSFET I-V Characteristics MOSFET non-idealities
ECE66: Solid State evices Lecture 3 MOSFET I- Characteristics MOSFET non-idealities Gerhard Klimeck gekco@purdue.edu Outline 1) Square law/ simplified bulk charge theory ) elocity saturation in simplified
More informationMetal Oxide Semiconductor Field Effect Transistors (MOSFETs) Prof. Ali M. Niknejad Prof. Rikky Muller
EECS 105 Spring 2017, Modue 3 Meta Oxide Semiconductor Fied Effect Transistors (MOSFETs) Prof. Ai M. Niknejad Prof. Rikky Muer Department of EECS University of Caifornia, Berkeey Announcements Prof. Rikky
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
More informationHW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7
HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7 2 What do digital IC designers need to know? 5 EE4 EECS4 6 3 0< V GS - V T < V DS Pinch-off 7 For (V GS V T )
More informationElectronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices
Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Three-terminal device whose voltage-current relationship is controlled by a third voltage
More informationChapter 6: Field-Effect Transistors
Chapter 6: Field-Effect Transistors slamic University of Gaza Dr. Talal Skaik FETs vs. BJTs Similarities: Amplifiers Switching devices mpedance matching circuits Differences: FETs are voltage controlled
More informationMicroelectronics Part 1: Main CMOS circuits design rules
GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!
More informationEE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow
EE 330 Lecture 16 MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow Review from Last Time Operation Regions by Applications Id I D 300 250 200 150
More informationEE 330 Lecture 16. MOSFET Modeling CMOS Process Flow
EE 330 Lecture 16 MOSFET Modeling CMOS Process Flow Model Extensions 300 Id 250 200 150 100 50 300 0 0 1 2 3 4 5 Vds Existing Model 250 200 Id 150 100 50 Slope is not 0 0 0 1 2 3 4 Actual Device Vds Model
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationEECS 105: FALL 06 FINAL
University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 2-3:30 Wednesday December 13, 12:30-3:30pm EECS 105: FALL 06 FINAL NAME Last
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationEE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits
EE 330 Lecture 22 Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits Exam 2 Friday March 9 Exam 3 Friday April 13 Review Session for Exam 2: 6:00
More informationELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model
ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current
More informationEE 330 Lecture 14. Devices in Semiconductor Processes. Diodes Capacitors MOSFETs
EE 330 Lecture 14 Devices in Semiconuctor Processes Dioes Capacitors MOSFETs Reminer: Exam 1 Friay Feb 16 Stuents may bring one page of notes (front an back) but no electronic ata storage or remote access
More informationBiasing the CE Amplifier
Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th
More information1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012
/3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOS Capacitor with External Bias
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 5: Januar 6, 17 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation! Level
More informationThe Gradual Channel Approximation for the MOSFET:
6.01 - Electronic Devices and Circuits Fall 003 The Gradual Channel Approximation for the MOSFET: We are modeling the terminal characteristics of a MOSFET and thus want i D (v DS, v GS, v BS ), i B (v
More informationMetal-oxide-semiconductor field effect transistors (2 lectures)
Metal-ide-semiconductor field effect transistors ( lectures) MOS physics (brief in book) Current-voltage characteristics - pinch-off / channel length modulation - weak inversion - velocity saturation -
More informationFundamentals of the Metal Oxide Semiconductor Field-Effect Transistor
Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationCircuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number
EE610: CMOS Analog Circuits L: MOS Models- (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3 NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS >
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationLecture 28 Field-Effect Transistors
Lecture 8 Field-Effect Transistors Field-Effect Transistors 1. Understand MOSFET operation.. Analyze basic FET amplifiers using the loadline technique. 3. Analyze bias circuits. 4. Use small-signal equialent
More informationECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Open-loop Gain: g m r o
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationMOSFETs - An Introduction
Chapter 17. MOSFETs An Introduction Sung June Kim kimsj@snu.ac.kr http://helios.snu.ac.kr CONTENTS Qualitative Theory of Operation Quantitative I Relationships Subthreshold Swing ac Response Qualitative
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis
More informationMOS Device Modeling. C.K. Ken Yang UCLA Courtesy of Agilent eesoft EE 215B
MOS Device Modeling C.K. Ken Yang UCLA yangck@ucla.edu Courtesy of Agilent eesoft 1 Overview Reading Rabaey 3.3 W&H 2.2-2.4 Overview This class will look at the iv and CV characteristics of an MOS device
More informationEE5311- Digital IC Design
EE5311- Digital IC Design Module 1 - The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM
More informationEE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET
EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: n-channel MOSFET Source Gate L Drain W L EFF Poly Gate oxide n-active p-sub depletion region (electrically
More informationMicroelectronic Circuit Design 4th Edition Errata - Updated 4/4/14
Chapter Text # Inside back cover: Triode region equation should not be squared! i D = K n v GS "V TN " v & DS % ( v DS $ 2 ' Page 49, first exercise, second answer: -1.35 x 10 6 cm/s Page 58, last exercise,
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationLecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER
Lecture 24 Multistage Amplifiers (I) MULTISTAGE AMPLIFIER Outline. Introduction 2. CMOS multi-stage voltage amplifier 3. BiCMOS multistage voltage amplifier 4. BiCMOS current buffer 5. Coupling amplifier
More informationMetal-Oxide-Semiconductor Field Effect Transistor
Symbols Structure Operating principle Terminal characteristics Operating regions Quiescent point position Metal-Oxide-Semiconductor Field Effect Transistor n-channel and p-channel enhancement-type MOSFET
More informationStudio 3 Review MOSFET as current source Small V DS : Resistor (value controlled by V GS ) Large V DS : Current source (value controlled by V GS )
Studio 3 Review MOSFET as current source Small V DS : Resistor (value controlled by V GS ) Large V DS : Current source (value controlled by V GS ) 1 Simulation Review: Circuit Fixed V GS, Sweep V DS I
More informationEE 435. Lecture 3 Spring Design Space Exploration --with applications to single-stage amplifier design
EE 435 ecture 3 Spring 2019 Design Space Exploration --with applications to single-stage amplifier design 1 Review from last lecture: Single-ended Op Amp Inverting Amplifier V IN R 1 V 1 R 2 A V V OUT
More informationUsing MOS Models. C.K. Ken Yang UCLA Courtesy of MAH EE 215B
Using MOS Models C.K. Ken Yang UCLA yangck@ucla.edu Courtesy of MAH 1 Overview Reading Rabaey 5.4 W&H 4.2 Background In the past two lectures we have reviewed the iv and CV curves for MOS devices, both
More informationLecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen
Lecture 5 Followers (1/11/4) Page 51 LECTURE 5 FOLLOWERS (READING: GHLM 344362, AH 221226) Objective The objective of this presentation is: Show how to design stages that 1.) Provide sufficient output
More informationEE40 Lec 20. MOS Circuits
EE40 Lec 20 MOS Circuits eading: Chap. 12 of Hambley Supplement reading on MOS Circuits http://www.inst.eecs.berkeley.edu/~ee40/fa09/handouts/ee40_mos_circuit.pdf Slide 1 Bias circuits OUTLINE Smallsignal
More informationEE105 - Fall 2006 Microelectronic Devices and Circuits
EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 21: Bipolar Junction Transistor Administrative Midterm Th 6:30-8pm in Sibley Auditorium Covering everything
More informationP. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions
P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the
More informationTransistors - a primer
ransistors - a primer What is a transistor? Solid-state triode - three-terminal device, with voltage (or current) at third terminal used to control current between other two terminals. wo types: bipolar
More informationA Compact Analytical Modelling of the Electrical Characteristics of Submicron Channel MOSFETs
ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY Volume 11, Number 4, 2008, 383 395 A Compact Analytical Modelling of the Electrical Characteristics of Submicron Channel MOSFETs Andrei SEVCENCO,
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationElectronics Fets and Mosfets Prof D C Dube Department of Physics Indian Institute of Technology, Delhi
Electronics Fets and Mosfets Prof D C Dube Department of Physics Indian Institute of Technology, Delhi Module No. #05 Lecture No. #02 FETS and MOSFETS (contd.) In the previous lecture, we studied the working
More informationFigure 1: MOSFET symbols.
c Copyright 2008. W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical and Computer Engineering. The MOSFET Device Symbols Whereas the JFET has a diode junction between
More informationJFET Operating Characteristics: V GS = 0 V 14. JFET Operating Characteristics: V GS = 0 V 15
J Operating Characteristics: V GS = 0 V 14 V GS = 0 and V DS increases from 0 to a more positive voltage: Gate and Source terminals: at the same potential Drain: at positive potential => reverse biased
More informationELEC 3908, Physical Electronics, Lecture 27. MOSFET Scaling and Velocity Saturation
ELEC 3908, Physical Electronics, Lecture 27 MOSFET Scaling and Velocity Saturation Lecture Outline Industry push is always to pack more devices on a chip to increase functionality, which requires making
More informationEE 435. Lecture 3 Spring Design Space Exploration --with applications to single-stage amplifier design
EE 435 Lecture 3 Spring 2016 Design Space Exploration --with applications to single-stage amplifier design 1 Review from last lecture: Single-ended Op Amp Inverting Amplifier V IN R 1 V 1 R 2 A V V OUT
More informationCharge Storage in the MOS Structure. The Inverted MOS Capacitor (V GB > V Tn )
The Inverted MO Capacitor (V > V Tn ) We consider the surface potential as Þxed (ÒpinnedÓ) at φ s,max = - φ p φ(x).5 V. V V ox Charge torage in the MO tructure Three regions of operation: Accumulation:
More informationLecture #25. Due in class (5 PM) on Thursday May 1 st. 20 pt penalty for late submissions, accepted until 5 PM on 5/8
ecture #5 Design Project: Due in class (5 PM on hursday May 1 st 0 pt penalty for late submissions, accepted until 5 PM on 5/8 Your J design does not need to meet the performance specifications when and
More informationECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution
ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown
More information