EE 330 Lecture 16. MOSFET Modeling CMOS Process Flow

Transcription

1 EE 330 Lecture 16 MOSFET Modeling CMOS Process Flow

2 Model Extensions 300 Id Vds Existing Model Id Slope is not Actual Device Vds

3 Model Extensions Id 150 I D 0 μc μc OX OX W V L W 2L GS 0 V V 2 V 2 V V 1 V GS T T DS DS DS Note: This introduces small discontinuity (not shown) in model at SAT/Triode transition V GS V V GS V GS T V V T T Vds V V DS DS V V GS GS V V T T

4 Further Model Extensions Existing model does not depend upon the bulk voltage! Observe that changing the bulk voltage will change the electric field in the channel region! V DS V GS ID V BS I B I G E (V BS small)

5 Further Model Extensions Existing model does not depend upon the bulk voltage! Observe that changing the bulk voltage will change the electric field in the channel region! V DS V GS ID V BS I B I G E (V BS small) Changing the bulk voltage will change the thickness of the inversion layer Changing the bulk voltage will change the threshold voltage of the device V V V T T 0 B S

6 Typical Effects of Bulk on Threshold Voltage for n-channel Device V T V T 0 V B S 1 0.4V V V T V T0 ~ -5V V BS Bulk-Diffusion Generally Reverse Biased (V BS < 0 or at least less than 0.3V) for n-channel Shift in threshold voltage with bulk voltage can be substantial Often V BS =0

7 Typical Effects of Bulk on Threshold Voltage for n-channel Device V T V T 0 V B S 1 0.4V V V T ΔV=? V T0 ~ -5V V BS V V -V V T T T 0 B S V V T

8 Typical Effects of Bulk on Threshold Voltage for p-channel Device T T 0 B S V V V 1 0.4V V V BS V T0 V T Bulk-Diffusion Generally Reverse Biased (V BS > 0 or at least greater than -0.3V) for n-channel Same functional form as for n-channel devices but V T0 is now negative and the magnitude of V T still increases with the magnitude of the reverse bias

9 Model Extension Summary I I G B V V GS T W V L 2 W 2 μc V V 1 V V V V V V 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T OX GS T DS GS T DS GS T V T V T0 V BS Model Parameters : {μ,c OX,V T0,φ,γ,λ} Design Parameters : {W,L} but only one degree of freedom W/L

10 Id Operation Regions by Applications I D Triode Region Saturation Region Analog Circuits Cutoff Region Vds Digital Circuits V DS Most analog circuits operate in the saturation region (basic VVR operates in triode and is an exception) Most digital circuits operate in triode and cutoff regions and switch between these two with Boolean inputs

11 Model Extension (short devices) 0 V V GS T W V L 2 W 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T 2 μc V V V V V V V OX GS T GS T DS GS T As the channel length becomes very short, velocity saturation will occur in the channel and this will occur with electric fields around 2V/u. So, if a gate length is around 1u, then voltages up to 2V can be applied without velocity saturation. But, if gate length decreases and voltages are kept high, velocity saturation will occur 0 V V GS T W I μc V V V V V V V D OX GS T DS GS T DS 1 GS L 1 W μc V V V V V V 2 OX GS T GS T DS 1 GS L V V α is the velocity saturation index, 2 α 1 T T 2

12 Model Extension (short devices) 0 V V GS T W I μc V V V V V V V D OX GS T DS GS T DS 1 GS L 1 W μc V V V V V V 2 OX GS T GS T DS 1 GS L V V α is the velocity saturation index, 2 α 1 T T 2 No longer a square-law model (some term it an α-power model) For long devices, α=2 Channel length modulation (λ) and bulk effects can be added to the velocity Saturation as well Degrading of α is not an attractive limitation of the MOSFET

13 Model Extension (BSIM model)

14 Model Errors with Different W/L Values I D Actual Modeled with one value of L, W Modeled with another value of L, W V GS3 V GS2 V GS1 V DS Binning models can improve model accuracy

15 BSIM Binning Model - Bin on device sizes - multiple BSIM models! With 32 bins, this model has 3040 model parameters!

16 Model Changes with Process Variations (n-ch characteristics shown) I D TT FS or FF (Fast n, slow p or Fast n, fast p ) SS or SF (Slow n, slow p or Slow n, fast p ) V GS3 V GS2 V GS1 V DS Corner models can improve model accuracy

17 BSIM Corner Models with Binning - Often 4 corners in addition to nominal TT, FF, FS, SF, and SS - bin on device sizes With 32 size bins and 4 corners, this model has 15,200 model parameters!

18 How many models of the MOSFET do we have? Switch-level model (2) Square-law model Square-law model (with λ and bulk additions) α-law model (with λ and bulk additions) BSIM model BSIM model (with binning extensions) BSIM model (with binning extensions and process corners)

19 The Modeling Challenge I D Actual Modeled with one model V GS3 (and W/L variations or Process Variations) Local Agreement with Any Model V GS2 (and W/L variations or Process Variations) V GS1 (and W/L variations or Process Variations) V DS (and W/L variations or Process Variations) I G I D V DS I = f V,V D 1 GS DS I = f V,V G 2 GS DS I = f V,V B 3 GS DS V GS I B V BS = 0 Difficult to obtain analytical functions that accurately fit actual devices over bias, size, and process variations

20 Model Status Simple dc Model Square-Law Model Small Signal Better Analytical dc Model Sophisticated Model for Computer Simulations BSIM Model Square-Law Model (with extensions for λ,γ effects) Short-Channel α-law Model Frequency Dependent Small Signal Simpler dc Model Switch-Level Models Ideal switches R SW and C GS

21 In the next few slides, the models we have developed will be listed and reviewed Square-law Model Switch-level Models Extended Square-law model Short-channel model BSIM Model BSIM Binning Model Corner Models

22 Square-Law Model I D V GS4 V GS3 V DS V GS2 V GS1 0 VGS VT W V L 2 W 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T 2 μc V V V V V V V OX GS T GS T DS GS T Model Parameters : {μ,c OX,V T0 } Design Parameters : {W,L} but only one degree of freedom W/L

23 Switch-Level Models Drain Gate G D Source R SW C GS V GS Switch closed for V GS = 1 S Switch-level model including gate capacitance and drain resistance C GS and R SW dependent upon device sizes and process For minimum-sized devices in a 0.5u process 2KΩ n channel C GS 1.5fF R sw 6KΩ p channel Considerable emphasis will be placed upon device sizing to manage C GS and R SW Model Parameters : {C GS,R SW }

24 Extended Square-Law Model I I G B V V GS T W V L 2 W 2 μc V V 1 V V V V V V 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T OX GS T DS GS T DS GS T V T V T0 V BS Model Parameters : {μ,c OX,V T0,φ,γ,λ} Design Parameters : {W,L} but only one degree of freedom W/L

25 Short-Channel Model 0 V V GS T W I μc V V V V V V V D OX GS T DS GS T DS 1 GS L 1 W μc V V V V V V 2 OX GS T GS T DS 1 GS L V V T T 2 α is the velocity saturation index, 2 α 1 Channel length modulation (λ) and bulk effects can be added to the velocity Saturation as well

26 BSIM model Note this model has 95 model parameters!

27 BSIM Binning Model - Bin on device sizes - multiple BSIM models! With 32 bins, this model has 3040 model parameters!

28 BSIM Corner Models - Often 4 corners in addition to nominal TT, FF, FS, SF, and SS - five different BSIM models! TT: typical-typical FF: fast n, fast p FS: fast n, slow p SF: slow n, fast p SS: slow n, slow p With 4 corners, this model has 475 model parameters!

29 Accuracy Complexity Hierarchical Model Comparisons BSIM Binning Models Analytical Numerical (for simulation only) L Number of Model Parameters BSIM Models Number of Model Parameters Square-Law Models Number of Model Parameters Switch-Level Models Approx 3000 (for 30 bins) Approx to 6 W Number of Model Parameters 0 to 2

30 Corner Models Basic Model FF (Fast n, Fast p) FS (Fast n, Slow p) TT Typical-Typical SF (Slow n, Fast p) SS (Slow n, Slow p) Corner Model Applicable at any level in model hierarchy (same model, different parameters) Often 4 corners (FF, FS, SF, SS) used but sometimes many more Designers must provide enough robustness so good yield at all corners

31 n-channel. p-channel modeling Source Gate Drain Bulk I D 3 V GS4 2.5 D n-channel MOSFET D V GS3 V GS2 G S G D S VDS GS4 GS3 GS2 GS1 V GS1 V V V V > 0 V DS G B (for enhancement devices) G I G V GS I D D S I B B S V BS V DS 0 VGS VTn W V L 2 W 2L I =I =0 DS I μ C V V V V V V V V D n OX GS Tn DS GS Tn DS GS Tn G B 2 μ C V V V V V V V n OX GS Tn GS Tn DS GS Tn Positive V DS and V GS cause a positive I D

32 Bulk Source n-channel. p-channel modeling Gate Drain (for enhancement devices) VTp 0 p-channel MOSFET S S G G D S D V GS G I G G I D B S D I B D V BS B V DS 0 V V GS Tp W V L 2 W 2L I =I =0 DS I -μ C V V V V V V V V D p OX GS Tp DS GS Tp DS GS Tp G B 2 -μ C V V V V V V V p OX GS Tp GS Tp DS GS Tp Negative V DS and V GS cause a negative I D Functional form of models are the same, just sign differences and some parameter differences (usually mobility is the most important)

33 Bulk Source n-channel. p-channel modeling Gate Drain (for enhancement devices) VTp 0 p-channel MOSFET S S G G S D G D S D B 0 V V GS Tp W V L 2 W 2L I =I =0 DS I -μ C V V V V V V V V D p OX GS Tp DS GS Tp DS GS Tp G B 2 -μ C V V V V V V V p OX GS Tp GS Tp DS GS Tp V GS G I G I D B D I B V BS V DS V GS G I G S B I B -I D D V BS V DS Actually should use C OXp and C OXn but they are usually almost identical in most processes μ n 3μ p May choose to model I D which will be nonnegative

34 n-channel. p-channel modeling Bulk Source Gate Drain V GS G I G I D S B D I B V BS V DS p-channel MOSFET (for enhancement devices) 0 V V GS Tp W V L 2 W 2L I =I =0 DS I -μ C V V V V V V V V D p OX GS Tp DS GS Tp DS GS Tp G B 2 -μ C V V V V V V V p OX GS Tp GS Tp DS GS Tp 0 V V GS Tp W V L 2 W 2L I =I =0 DS I μ C V V V V V V V V D p OX GS Tp DS GS Tp DS GS Tp G Alternate equivalent representation B 2 μ C V V V V V V V p OX GS Tp GS Tp DS GS Tp These look like those for the n-channel device but with

35 D n-channel. p-channel modeling D S S G G G G S D S D D D G B G B S S G I G V GS I D D I B B V BS V DS V GS G I G S B I B V BS V DS S I D D I D V GS4 V GS3 Models essentially the same with different signs and model parameters 1 V GS V GS V DS VDS VGS4 VGS3 VGS2 V GS1> 0 0 VGS VTn W V L 2 W 2 μ C V V V V V V V 2L I =I =0 DS I μ C V V V V V V V V D n OX GS Tn DS GS Tn DS GS Tn G B n OX GS Tn GS Tn DS GS Tn 0 V V GS Tp W V L 2 W 2L I =I =0 DS I -μ C V V V V V V V V D p OX GS Tp DS GS Tp DS GS Tp G B 2 -μ C p OX VGS VTp VGS VTp VDS VGS VTp

36 Model Relationships Determine R SW and C GS for an n-channel MOSFET from square-law model In the 0.5u CMOS process if L=1u, W=1u (Assume μc OX =100μAV -2, C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) 0 V V GS T W V L 2 W 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T 2 μc V V V V V V V OX GS T GS T DS GS T when SW is on, operation is deep triode

37 Model Relationships Determine R SW and C GS for an n-channel MOSFET from square-law model In the 0.5u CMOS process if L=1u, W=1u (Assume μc OX =100μAV -2, C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) When on operating in deep triode W V W L 2 L DS I μc V V V μc V V V D OX GS T DS OX GS T DS V 1 1 DS R = 4K SQ I W 1 D V GS =VDD μc V V ( E 4) OX GS T L V GS =3.5V 1 C GS = C OX WL = (2.5fFµ -2 )(1µ 2 ) = 2.5fF

38 Model Relationships Determine R SW and C GS for an p-channel MOSFET from square-law model In the 0.5u CMOS process if L=1u, W=1u ( C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) Observe µ n \ µ p 3 0 V V GS T W V L 2 W 2L DS -I μc V V V V V V V V D OX GS T DS GS T DS GS T 2 μc V V V V V V V OX GS T GS T DS GS T When SW is on, operation is deep triode

39 Model Relationships Determine R SW and C GS for an p-channel MOSFET from square-law model In the 0.5u CMOS process if L=1u, W=1u ( C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) Observe µ n \ µ p 3 W V W L 2 L DS -I μ C V V V μ C V V V D p OX GS T DS p OX GS T DS -V 1 1 DS R = 12K SQ -I W 1 1 D V GS =VDD μ C V V ( 4) p OX GS T L E V GS =3.5V 3 1 C GS = C OX WL = (2.5fFµ -2 )(1µ 2 ) = 2.5fF Observe the resistance of the p-channel device is approximately 3 times larger than that of the n-channel device for same bias and dimensions!

40 Modeling of the MOSFET Goal: Obtain a mathematical relationship between the port variables of a device. I f V,V,V I I D G B 1 f f 2 3 GS DS BS VGS,V DS,VBS V GS,V DS,VBS Drain V DS I D I B Gate Bulk I D Simple dc Model V GS V BS Small Signal Better Analytical dc Model Sophisticated Model for Computer Simulations Frequency Dependent Small Signal Simpler dc Model

41 Small-Signal Model Goal with small signal model is to predict performance of circuit or device in the vicinity of an operating point Operating point is often termed Q-point

42 Small-Signal Model y Y Q Q-point X Q x Analytical expressions for small signal model will be developed later

43 Design Rules Technology Files Process Flow (Fabrication Technology) Model Parameters

44 n-well n-well n- p-

45

46

47 Bulk CMOS Process Description n-well process Single Metal Only Depicted Double Poly This type of process dominates what is used for high-volume lowcost processing of integrated circuits today Many process variants and specialized processes are used for lowervolume or niche applications Emphasis in this course will be on the electronics associated with the design of integrated electronic circuits in processes targeting highvolume low-cost products where competition based upon price differentiation may be acute Basic electronics concepts, however, are applicable for lower-volume or niche applicaitons

48 Components Shown n-channel MOSFET p-channel MOSFET Poly Resistor Doubly Poly Capacitor

49 C D A A B B C D

50 Consider Basic Components Only Well Contacts and Guard Rings Will be Discussed Later

51 A A B B

52 A A B B

53 Metal details hidden to reduce clutter A A D G S B D B S B n-channel MOSFET G

54 A A D G S B B B W L

55 A A Capacitor Resistor p-channel MOSFET B B n-channel MOSFET

56 n-well n-well n- p-

57 N-well Mask A A B B

58 N-well Mask A A B B

59 Detailed Description of First Photolithographic Steps Only Top View Cross-Section View

60 ~ Blank Wafer Implant n-well Photoresist Mask p-doped Substrate Will use positive photoresist (exposed region soluble in developer) A A B Develop Expose B

61 Develop N-well Exposure Photoresist Mask A-A Section B-B Section

62 Implant A-A Section B-B Section

63 N-well Mask A-A Section B-B Section

64 n-well n-well n- p-

65 Active Mask A A B B

66 Active Mask A A B B

67 Active Mask Field Oxide A-A Section Field Oxide Field Oxide Field Oxide B-B Section

68 n-well n-well n- p-

69 Poly1 Mask A A B B

70 Poly1 Mask A A B B

71 Poly plays a key role in all four types of devices! A A Capacitor Resistor P-channel MOSFET B B n-channel MOSFET

72 Poly 1 Mask A-A Section Gate Oxide Gate Oxide B-B Section

73 n-well n-well n- p-

74

75 Poly 2 Mask A A B B

76 Poly 2 Mask A A B B

77 Poly 2 Mask A-A Section B-B Section

78 n-well n-well n- p-

79

80 P-Select A A B B

81 P-Select A A B B

82 P-Select Mask p-diffusion p-diffusion A-A Section Note the gate is self aligned!! B-B Section

83 n-select Mask n-diffusion A-A Section n-diffusion B-B Section

84 n-well n-well n- p-

85

86

87 Contact Mask A A B B

88 Contact Mask A A B B

89 Contact Mask A-A Section B-B Section

90 n-well n-well n- p-

91

92

93 Metal 1 Mask A A B B

94 Metal 1 Mask A A B B

95 Metal Mask A-A Section B-B Section

96 A A B B

97 A A Capacitor Resistor P-channel MOSFET B B n-channel MOSFET

98 End of Lecture 16