Optimum Conditions of Body Effect Factor and Substrate Bias in Variable Threshold Voltage MOSFETs

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1 Jp. J. Appl. Phys. Vol. 39 (2000) pp Part 1, No. 4B, April 2000 c 2000 The Japa Society of Applied Physics Optimum Coditios of Body Effect Factor ad Substrate Bias i Variable Threshold Voltage MOSFETs Hiroshi KOURA 1,, Makoto TAKAMIYA 1 ad Toshiro HIRAMOTO 1,2 1 Istitute of Idustrial Sciece, Uiversity of Tokyo, Roppogi, Miato-ku, Tokyo , Japa 2 VLSI Desig ad Educatio Ceter, Uiversity of Tokyo, Hogo, Bukyo-ku, Tokyo , Japa (Received October 8, 1999; accepted for publicatio Jauary 28, 2000) The effects of body effect factor ( ) ad substrate bias (V bs ) i a variable threshold voltage metal oxide semicoductor field effect trasistor (VTMOS) have bee systematically examied by device simulatio. The characteristics of a VTMOS are sigificatly affected by the value of ad the V bs differece ( V bs ) betwee the active mode ad the stadby mode. Optimal ad V bs to obtai higher o-curret i the active mode ad lower off-curret i the stadby mode are derived. Whe offcurret i the active mode is limited, a larger V bs ad smaller are preferable to obtai a higher drive curret. Whe is fixed, V bs should be as large as the breakdow ad leakage curret permits. Whe V bs is fixed for some reaso, such as breakdow, the optimum depeds o the relatioship betwee V bs ad V dd : should be larger whe a large V bs ca be applied, while it should be smaller whe the V bs is small. The scalability of VTMOS is also discussed ad it is foud that chael egieerig is strogly required i a scaled VTMOS. These results will greatly help i desigig ultra-low power VTMOS VLSIs, ad the VTMOS could be expected to survive i the 50 m geeratio depedig o the scalig sceario ad applicatios. KEYWORDS: body effect, variable threshold voltage metal oxide semicoductor field effect trasistor (VTMOS), substrate bias, low power, active mode, stadby mode, chael egieerig 1. Itroductio The variable threshold voltage metal oxide semicoductor field effect trasistor (VTMOS) has recetly attracted much attetio for ultra-low power very large scale itegratio (VLSI) applicatios at low supply voltage (V dd ). 1 3) Utilizig the body effect, the substrate bias (V bs ) is cotrolled to shift the threshold voltage (V th ), ad a high V th i the stad-by mode ad low V th i the active mode are obtaied. V th fluctuatios betwee chips are also suppressed by V bs cotrol. 1) The V th shift ( V th ) is give by V th = V bs = V bs (s) V bs, (1) where is the body effect factor, V bs the differece of substrate bias betwee the active mode ad the stadby mode, V bs (s) the substrate bias i the stadby mode, ad V bs the substrate bias i the active mode. Therefore, ad V bs are the most importat device parameters i relatio to VTMOS ad their optimizatio is essetial to take full advatage of VTMOS. However, o study has previously bee made o the optimum coditios of ad V bs. I this study, the depedece of VTMOS performace o ad V bs is systematically ivestid by device simulatio ad the optimum coditios are discussed. It is foud that V bs should be as large as possible, while the optimum value of depeds o the relatioship betwee V bs ad V dd. The scalability of VTMOS is also discussed. It is foud that egieerig of the dopig profiles i the chael regio (chael egieerig) 4) is strogly required i scaled VTMOS. 2. Simulatio ad Results 2.1 Defiitio of the body effect factor I this study, the body effect factor is defied as V th V bs = V th(s) V th V bs (s) V bs = C d, C ox (2) address: koura@ao.iis.u-tokyo.ac.jp V th (s) V th V V bs =0V (s) log I ds slope: V bs active mode V bs =0V V th = V bs Stadby mode th V th V bs (s) I o V dd A B B V bs A A < B V gs Fig. 1. A schematic of the relatioship amog V th, V bs ad i a value of VTMOS. is give by the slope of V th / V bs. Schematic of the characteristics of a VTMOS with differet at (device A has smaller tha device B). The off-curret i the stadby mode ( (s)) is set costat at A/µm. The off-curret i the active mode ( ) is also set to be the same i this figure. Device A has higher o-curret (I o ) due to the smaller S factor ad higher mobility but requires large V bs to attai low (s) due to the small. 2312

2 Jp. J. Appl. Phys. Vol. 39 (2000) Pt. 1, No. 4B H. KOURA et al where V th (s) ad V th are the threshold voltage i the stadby ad active modes, respectively, C d is the depletio capacitace ad C ox is the oxide capacitace, so that V th is give by eq. (1). 5) Geerally, V th is depedet o the square root of V bs ad the body effect factor is give by 6) 2qεNA =, (3) C ox where q is the electric charge, ε is the permittivity i silico ad N A is the chael dopig cocetratio. However, i eq. (3) is valid oly i MOSFETs with uiform chael cocetratio. Moreover, the relatio betwee V th ad is ot clear. Therefore, we adopted the defiitio of eq. (2). Figure 1 shows a schematic of the relatioship amog, V bs, ad V th. is give by a slope of V th / V bs. Please ote that the value of chages with V bs whe V th is ot proportioal to V bs as show i the figure. However, eq. (1) is always valid whe the defiitio of eq. (2) is used. O the other had, subthreshold swig (S factor) is give at room temperature by ( S = C ) d [mv/dec]. (4) C ox The, the relatio betwee ad S is give from eqs. (2) ad (4) as S = 60(1 + )[mv/dec]. (5) This equatio idicates that a device with larger has a larger S factor. 2.2 Qualitative predictios Figure 1 shows a schematic of the characteristics of VTMOS s with differet value of. Device A has a smaller tha device B. Whe the off-curret i the stadby mode ( (s)) is the same for the two devices, device A requires a larger V bs to attai a certai V th due to smaller tha device B. However, device A with a smaller will have a higher o-curret (I o ) as show i Fig. 1. This is because device A has a steeper S swig (hece low V th ) ad higher mobility due to the weaker vertical electric field. Therefore, the optimal value of is ot clear from this the qualitative discussio aloe. More detailed discussio based o device simulatio 7) is preseted i the followig subsectios. 2.3 Simulated device structures Figure 2 shows a schematic of the device structures used i the simulatio. Figure 2 shows the uiformly doped MOSFET (uiform MOS) where the chael dopig profile is uiform. Uiform MOS geerally has a small due to the large depletio layer width. Figure 2(c) shows the deltadoped MOSFET () where the chael dopig profile is step-like as show i figure. 8) Delta MOS has a twice as large as uiform MOS, because the depletio layer width of is half of that of the uiform MOS at a fixed V th. 8) O the other had, the state-of-the-art MOSFETs with high p p p - t -- - N D t p ++ p ++ Na Na Na Na p p + p ++ p p - l d depth l d depth l d depth t t p l d depth Uiformly-doped MOS (uiform MOS) Retrograde MOS Delta-doped MOS* () (c) Couter-doped MOS (couter MOS) (d) Fig. 2. Schematic of the device structures used i the device simulatio. Gate legth is 0.18 µm, oxide thickess is 3 m, source/drai juctio depth is 50 m, ad supply voltage is 1.5 V Uiformly doped MOSFET (uiform MOS), i which the chael cocetratio is varied to chage ad V th. Retrograde chael MOSFET with a low dopig cocetratio at the surface ad a high cocetratio i depth (retrograde MOS). Although this structure is ot simulated i this study, the characteristics are itermediate betwee those of uiform MOS ad. (c) Delta-doped MOSFET 8) (), i which the thickess (t) of the low cocetratio layer is varied to vary ad V th. (d) Couter-doped MOSFET (couter MOS), i which the thickess (t) ad cocetratio (ND) of the middle layer is varied to chage ad V th over a wide rage.

3 2314 Jp. J. Appl. Phys. Vol. 39 (2000) Pt. 1, No. 4B H. KOURA et al. short chael effect immuity have a gradual chael profile with a low cocetratio at the surface ad high cocetratio i depth due to the chael egieerig as show i Fig. 2, which is geerally referred to as a MOSFET with a retrograde chael profile (retrograde MOS). 9) Although the characteristics of a retrograde MOS deped o the actual chael profile, they are itermediate betwee those of a uiform MOS ad. 5, 9) Therefore, we first simulated the characteristics of these two extreme device structures: uiform MOS ad. I uiform MOS, the chael cocetratio is varied to chage the value of ad V th. I, the thickess of the low cocetratio layer (t) is varied to chage the value of ad V th. Figure 3 shows the relatio betwee the off-curret i the active mode ( ) ad I o, ad Figure 3 shows the relatio betwee V th ad of the two devices. The umbers idicated i Fig. 3 are the values of. The device parameters used are based o the 180-m techology ode i the Iteratioal Techology Roadmap for Semicoductors (ITRS). 10) Uiform MOS has a higher I o but the required V bs would be extremely high due to the very small. The retrograde MOS covers the area betwee the two lies. It is suggested from Fig. 3 that the covered rage of ad V th is limited whe oly uiform MOS ad delta (A/µm)@V gs =0V V th (V)@V bs =0V 1x10-6 1x10-7 1x10-8 1x10-9 1x V dd Retrograde MOS =9 7 3 uiform MOS (s)=10-13 A/µm I o (ma/µm)@v gs uiform MOS Retrograde MOS Fig. 3. Relatio betwee ad I o i a uiform MOS ad delta MOS. (s) of each device is fixed at A/µm. The value of each device are show. Relatio betwee V th ad i a uiform MOS ad. The chael-egieered MOSFETs, such as retrograde MOS, cover the area betwee the two lies. V bs ad caot be varied widely by usig oly uiform, retrograde or. MOS are simulated. I order to ivesti the effect of systematically over a wider rage of I o ad, therefore, couter-doped MOSFETs (couter MOS) are also simulated. Figure 2(d) shows the structure of the couter MOS where the polarity of chael dopig is the opposite ear the surface. The couter MOS has a lower V th (higher ) tha uiform MOS ad due to the couter-dopig, ad a larger at a fixed V th. is varied over a wide rage by chagig the thickess of the couter-doped layer ad V th is varied by chagig the cocetratio of the couter doped layer. 2.4 Simulatio coditios ad method The off-curret i the stadby mode ( (s)) is set at A/µm, ad the o-curret i the active mode (I o ) is compared i this study. The same results are obtaied whe I o is fixed ad (s) is compared. V bs i the active mode (V bs ) is set to 0 V i the simulatio, sice V bs is usually almost 0 V i the VTMOS. 1) Therefore, V bs correspods to V bs i the stadby mode (V bs (s)) i this study. The I V characteristics are simulated for a device parameter set at V bs = 0 (active mode), ad the o-curret (I o ), off-curret ( ), ad V th i the active mode are derived. The, V bs is applied (the stadby mode), ad V bs is obtaied so that (s) is A/µm i the stadby mode. The, V th is derived from V th s i the active ad stadby modes, ad is obtaied from eq. (2). The simulatio is carried out for various device parameters. I o,,, V bs are derived for each parameter set by the above-metioed method. The, I o ad of each device are plotted i a -I o plae, ad cotour lies of ad V bs are obtaied. 2.5 Simulated results Figure 4 shows the device simulatio results. (s) is fixed at A/µm. This figure shows the cotour lies of V bs (solid lies) ad (dashed lies) as a fuctio of ad I o. Sice this figure is rather complicated, we discuss the results i the followig three boudary coditios Costat I the first boudary coditio, is set at a costat value i additio to the costat (s). Whe V th is extremely (A/ µm)@v gs =0V solid lie=cotour lie of V bs dashed lie=cotour lie of V bs =-0.3V = V V V -1.2V -1.5V -2V -3V (s)=10-13 (A/µm) 0V =0 0.8 I o (ma/µm)@v gs Fig. 4. Cotour lies of V bs (solid lies) ad (dashed lies) i a VTMOS as a fuctio of ad I o. (s) is set at (A/µm). = 10 8 A/µm uder the first boudary coditio (costat ), = 0.3 uder the secod boudary coditio (costat ), ad V bs = 2Vad 0.3 V uder the third boudary coditio (costat V bs ) are show by bold lies. -5V

4 Jp. J. Appl. Phys. Vol. 39 (2000) Pt. 1, No. 4B H. KOURA et al low, becomes very large ad the circuits cosume a lot of power ad sometimes do ot work properly. 11, 12) Therefore, should be limited to a certai maximum value. This coditio roughly correspods to a costat V th. Figure 5 shows the simulatio results of VTMOS uder the coditio of fixed (s) ad. Figure 5 shows the relatio of I o ad to obtai a costat (s) of A/µm ad costat of 10 8 A/µm, ad Figure 5 shows the V bs depedece of I o uder this coditio. This coditio is show by a horizotal lie i Fig. 4. Uder this coditio, V bs should be large ad a device with relatively small is preferable, as show i Fig Costat The secod boudary coditio is a costat. Whe the device is fixed, is also fixed. The relatio betwee ad I o is expressed i the correspodig cotour lie of, as show i Fig. 4 with = 0.3 as a example. It is evidet from the cotour lies that V bs should be as large as possible to achieve a higher I o, although also icreases. I actual devices, V bs is usually limited by juctio leakage curret or jucito breakdow. Uder this coditio, V bs should be set to a value as large as is permitted by the leakage or breakdow Costat V bs The third boudary coditio is a costat V bs. As me- I o (ma/µm)@v gs I o (ma/µm)@v gs (s)=10-13 (A/µm) =10-8 (A/µm) V bs (V) (s)=10-13 (A/µm) =10-8 (A/µm) Fig. 5. Simulatio results for the first boudary coditio: costat. (s) is also costat (10 13 A/µm). Relatio betwee I o ad. Relatio betwee I o ad V bs. To obtai larger I o, should be small ad V bs should be large uder the coditio of costat. Vbs (V) X X10-4 6X X10-4 5X10-4 I o =7.5X10-4 (A/µm) (s)=10-13 (A/µm) V dd 4.5X10-4 4X Fig. 6. Cotour lies of I o i a VTMOS as a fuctio of V bs ad. The V dd is 1.5 V. Whe V bs is larger tha 1.2 V, a higher I o is obtaied for larger. O the other had, whe V bs is less tha 1.2 V, higher I o is obtaied for smaller. tioed above, V bs is limited by leakage curret or breakdow of the p juctios ad the maximum V bs strogly depeds o the device structures ad process. Please ote that all the cotour lies of V bs coverge to oe poit i Fig. 4. This poit correspods to the device with = 0. The lie of V bs = 0 V is also show i Fig. 4. Whe V bs =0V, equals to (s) ad oly I o chages because V th = 0 V. It should be also oted that at a certai value of V bs, I o becomes costat regardless of the value of, as show i Fig. 4. This V bs is defied as V o. I this case, V o is about 1.2 V. Whe V bs is larger tha V o, for example V bs = 2V, a larger I o is obtaied for larger. O the other had, whe V bs is smaller tha V o, for example V bs = 0.3 V, a larger I o is obtaied for a smaller. Figure 6 shows the same results i a differet way, where the cotour lies of I o are show as a fuctio of V bs ad. The slope of the cotour lies chages from positive to egative at V bs = V o. Whe V bs is larger tha V o, the slope is egative. Thus, a higher I o is achieved for larger. However, whe V bs is smaller tha V o, the result is the opposite Optimum coditio of This iterestig result is well explaied qualitatively as follows. Figure 7 shows a schematic of the relatio betwee I o ad. (s) is fixed. I a ormal MOSFET (V bs = 0 V), I o decreases with icreasig due to degradatio of the S factor ad smaller mobility. 5) The slope of the I o - curve is egative. Whe V bs is applied, I o icreases ad the icrease of I o is larger for larger. Therefore, whe V bs is sufficietly large, I o becomes larger for larger ad the slope of the I o - curve becomes positive. The value of V o is slightly smaller tha that of V dd as show i Fig. 6. The reaso is discussed qualitatively i the followig. Here, let us cosider a device with V bs = V dd ad a device with V bs = V dd. Note that the device with V bs = V dd is the dyamic-threshold MOS (DTMOS) where the is coected to the body. 13) Although the V dd of the DTMOS should be lower tha the forward voltage of the p juctio, it has bee reported that the I o of a DTMOS icreases with icreasig. 5, 14) O the other had, the device with V bs = V dd would show almost the same characteristeics as

5 2316 Jp. J. Appl. Phys. Vol. 39 (2000) Pt. 1, No. 4B H. KOURA et al. I o (s)=10-13 A/ m V bs >V o 0.4 V dd 1.3V 0.3 V th =0.3V 0.26V 1.0V 0.2V 0.7V 0.14V 0.5V 0.1V I o small large V bs =V dd (DTMOS) V bs =V o V bs <V o V bs =0V (ormal MOS) uiform MOS Retrograde MOS year Fig. 7. Schematic of the relatioship betwee I o ad that qualitatively explais the optimum coditio of uder the coditio of costat V bs. Four solid lies show the VTMOS. The dashed lie shows the DTMOS. Sice a larger I o is obtaied for larger i DTMOS, V o is slightly smaller tha Vdd. Whe V bs > V o, a larger I o is obtaied larger, while whe V bs < V o, a larger I o is obtaied for smaller. this DTMOS whe the V bs depedece of is liear. Therefore, the device with V bs = V dd roughly correspods to the dashed lie i Fig. 7. The horizotal lie i Fig. 7 correspods to V bs = V o. Therefore, V o is slightly smaller tha V dd. As show i this figure, I o becomes larger with icreasig whe V bs is larger tha V o, while I o becomes smaller with icreasig whe V bs is smaller tha V o. 3. Scalability of VTMOS Oe of the major cocers about regardig a VTMOS is its scalability. 15) We discuss the scalability of VTMOS s i this sectio. The device parameters i each techology geeratio are maily based o ITRS. 10) Two scalig scearios of VTMOS s are cosidered i this study: V th i the active mode (V th ) is scaled like other device parameters i the first sceario, while V th is kept costat i the secod oe. 3.1 A Scalig sceario with scaled V th I the first scalig sceario, V th is scaled. The other device parameters are also scaled based o ITRS. 10) Figure 8 shows the variatio of with the techology geeratio. The supply voltage V dd ad V th i each geeratio are show i the figure. The chael-egieered MOS, such as retrograde chael MOS, is just betwee the two lies (the lies of uiform MOS ad ). Figure 8 idicates that becomes larger by the chael egieerig. However, i this sceario, decreases as the device is scaled. Figure 8 shows the variatio of V bs that is required to obtai (s) = A/µm. V bs rapidly icreases i uiform MOS, as also i. This is a serious problem because the breakdow voltage would decrease as the device is scaled. It must be oted that the required V bs is greatly suppressed by the chael egieerig. The advatage of chael-egieered MOS is ot oly i the large but also the V bs depedece of. Figure 9 shows V th as a fuctio of V bs i a uiform MOS ad. I the uiform MOS, V th is proportioal to the square root of V bs, ad the effect of back bias is ot effective. I the delta MOS, o the other had, V th is almost proportioal to V bs. V bs (obtai (s) of10-13 (A/µm)) uifom MOS Retrograde MOS year Fig. 8. Scalability of VTMOS i the scalig sceario with scaled V th. Variatio of i each geeratio. Required V bs to obtai a (s) of A/µm. becomes larger by the chael egieerig ad the required V bs ca be suppressed by chael egieerig. Vth(V) This is because i, the depletio layer width is kept almost costat eve if V bs is applied. Therefore, the chael profile of VTMOS should be as steep as that of the, ad a super steep chael profile is strogly desired. 3.2 A Scalig sceario with costat V th I the secod sceario,, ad hece V th, are kept costat, while other parameters such as V dd, legth ad oxide thickess are scaled accordig to ITRS. 10) I VTMOS, V th ca be extremely low because subthreshold leakage is suppressed i the stadby mode. Therefore, this sceario is more practical tha the first sceario. Figure 10 shows the variatio of ad the required V bs for a uiform MOS V th =0.3V (@ V bs =0V) V bs (V) Fig. 9. Relatio betwee V th ad V bs. I a uiform MOS, V th is proportioal to the square root of V bs. I, V th is almost proportioal to V bs. Chael profile should be as steep as i the, ad a super steep chael profile is strogly desired i scaled VTMOS.

6 Jp. J. Appl. Phys. Vol. 39 (2000) Pt. 1, No. 4B H. KOURA et al ig o the scalig sceario ad applicatios. 4. Coclusios The effects of ad V bs i a VTMOS have bee systematically examied by simulatio uder a coditio of fixed off-curret i the stadby mode, ad the optimal ad V bs are derived to obtai a higher o-curret i the active mode by meas of device simulatio. Whe off-curret i the active mode is limited, a larger V bs ad smaller are preferable to obtai a higher drive curret. Whe is fixed, V bs should be as large as is permitted by the breakdow ad leakage curret. Whe V bs is fixed for some reaso, such as the breakdow, the optimum depeds o the relatioship betwee V bs ad V dd. The same optimal coditios are obtaied for a lower off-curret ad fixed o-curret. The scalability of a VTMOS is also discussed ad it is foud that chael egieerig is required i scaled VTMOS. These results are expected to be of great help i desigig ultra-low power VTMOS VLSIs, ad the VTMOS will survive i the 50 m geeratio depedig o the scalig sceario ad applicatios. Ackowledgemet The authors would like to thak Prof. T. Sakurai for the fruitful discussios. This work was partly supported by JSPS Research for the Future Program. Fig. 10. Scalability of VTMOS i the sceario with costat V th. Variatio of i each geeratio. Required V bs to obtai (s) of A/µm. The advatage of the costat V th sceario is that is kept almost costat ad the required V bs remais almost the same. However, the disadvatage is that I o becomes too small due to the costat V th. The best scalig sceario for a VTMOS would deped o the applicatio.. The uiform MOS is ot show here because the required V bs is too large. I this sceario, the depletio layer width should decrease rapidly i order to keep V th costat. Therefore, is kept almost costat, ad the required V bs is also almost costat. This is a great advatage for VTMOS. However, a disadvatage of this sceario is that I o is greatly degraded due to costat V th as the device is scaled. These discussios suggest that the scalability of VTMOS depeds o the scalig sceario ad it also depeds o the applicatios. I the 50 m geeratio with very low supply voltage, all the requiremets for scaled devices, such as high speed, low stadby off-curret, low active off-curret, will ot fulfilled by ormal MOSFETs without threshold cotrol. VTMOS will certaily satisfy more requiremets tha ormal MOSFETs ad will survive i the 50 m geeratio deped- 1) T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sao, M. Norishima, M. Murota, M. Kako, M. Kiugasa, M. Kakumu ad T. Sakurai: IEEE J. Solid-State Circuits 31 (1996) ) Y. Oowaki, M. Noguchi, S. Takagi, D. Takashima, M. Oo, Y. Matsuaga, K. Suouchi, H. Kawaguchiya, S. Matsuda, M. Kamoshida, T. Fuse, S. Wataabe, A. Toriumi, S. Maabe ad A. Hojo: ISSCC Dig. Tech. Pap. (1998) p ) H. Mizuo, K. Ishibashi, T. Shimura, T. Hattori, S. Narita, K. Shiozawa, S. Ikeda ad K. Uchiyama: ISSCC Dig. Tech. Pap. (1999) p ) H. P. Wog, D. J. Frak, P. M. Solomo, C. H. J. Wa ad J. J. Welser: Proc. of IEEE 87 (1999) ) T. Hiramoto ad M. Takamiya: IEICE Tras. Electro. E83-C (2000) ) N. H. E. Weste ad K. Eshraghia: Priciples of CMOS VLSI Desig, A Systems Perspective, Addiso-wesley Publishig, (1993) 2d ed. 7) Medici Ver. 4.1, Avat! Corp., July ) K. Noda, T. Tatsumi, T. Uchida, K. Nakajima, H. Miyamoto ad C. Hu: IEEE Tras. Electro Devices 45 (1998) ) Y. Taur, D. A. Buchaa, W. Che, D. J. Frak, K. E. Ismail, S. H. Lo, G. A. Sai-Halasz, R. G. Viswaatha, H. C. Wa, S. J. Wid ad H. S. Wog: Proc. IEEE 85 (1997) ) Iteratioal Techology Roadmap for Semicoductors, 1998 Update, ) Z. Che, C. Diaz, J. D. Plummer, M. Cao ad W. Greee: It. Electro Device Meet. Tech. Dig. (1996) p ) R. Gozalez, B. M. Gordo ad M. A. Horowitz: IEEE J. Solid-State Circuits 32 (1997) ) F. Assaderaghi, D. Siitsky, S. Parke, J. Boker, P. K. Ko ad C. Hu: It. Electro Device Meet. Tech. Dig. (1994) ) C. Wa, K. Noda, T. Taaka, M. Yoshida ad C. Hu: IEEE Tras. Electro Devices 43 (1996) ) A. Keshavarzi, S. Naredra, S. Borker, C. Hawkis, K. Roy ad V. De: It. Symp. Low Power Electroics ad Desig (1999) p. 252.