Temperature-Dependent Kink Effect Model for Partially-Depleted SOI NMOS Devices

Transcription

1 254 IEEE RANSACIONS ON ELECRON DEVICES, VOL. 46, NO. 1, JANUARY 1999 emperature-depedet Kik Effect Model for Partially-Depleted SOI NMOS Devices S. C. Li ad J. B. Kuo Abstract his paper reports a closed-form aalytical temperaturedepedet kik effect model for the partially-depleted SOI NMOS devices. Based o the body-emitter voltage model, a aalytical triggerig V DS formula for temperature-depedet kik effect has bee obtaied. Accordig to the aalytical model, at a higher operatio temperature ad with a lighter thi-film dopig desity, the oset of the kik effect occurs at a larger V DS. I. INRODUCION Partially-depleted SOI NMOS devices have bee itesively studied [1] [3]. Due to the floatig body structure, kik effect is a importat pheomeo for partially-depleted SOI NMOS devices. he kik effect ca be explaied as follows. I partially-depleted SOI NMOS devices, owig to the existece of the eutral regio i the body, the source-body potetial barrier is large. herefore, the geerated holes due to impact ioizatio are easily trapped i the body. Cosequetly, the potetial barrier betwee the source ad the body decreases. he hole curret geerated by impact ioizatio flows from body to source. Due to the icrease i the body potetial, the threshold voltage chages depedig o the drai bias the kik effect [4], [5]. Recetly, CMOS circuits such as dyamic logic gates, frequecy dividers, ad operatioal amplifier realized by SOI CMOS devices operatig at a elevated ambiet temperature have bee reported [6]. Aalysis of the SOI MOS devices operatig at a elevated ambiet temperature has also bee reported [7] [9]. At a elevated ambiet temperature, kik effect is still importat. Aalysis of the kik effect for the partially-depleted SOI NMOS device has bee reported [9]. However, it s ot closed-form. I order to gai isights, a closed-form aalytical temperature-depedet kik effect model is derived i this paper. I the followig sectios, the closed-form aalytical model is derived first, followed by the model verificatio ad discussio. II. MODEL DERIVAION For a partially-depleted SOI NMOS operatig at high temperature, biased i the saturatio regio there are usmooth trasitios i the drai curret due to impact ioizatio. his is the so-called kik effect [4], [5]. At ay operatig temperature, at the kik, the body-emitter voltage of the parasitic bipolar device (V BE ), which is the differece i the quasi-fermi potetial across the body-emitter juctio [10] (V BE = p0, where p ad are the hole ad the electro quasi- Fermi potetial at the body-emitter juctio, respectively), has a abrupt chage. he sudde icrease i the body-emitter voltage at the kik i the saturatio regio is due to the accumulated holes caused by the ijectio of the hole curret geerated by impact ioizatio. At a elevated operatig temperature, the kik effect is reduced. I Mauscript received April 6, his work was supported uder R.O.C. Natioal Sciece Cotracts NSC E ad NSC E he review of this brief was arraged by Editor J. M. Vasi. he authors are with the Departmet of Electrical Egieerig, Natioal aiwa Uiversity, aipei , aiwa, R.O.C. ( jbkuo@cc.ee.tu.edu.tw). Publisher Item Idetifier S (99) this sectio, the temperature-depedet kik effect model is derived. I the followig derivatio, the temperature-depedet models for itrisic cocetratio, electro mobility, geeratio/recombiatio lifetimes, ad impact ioizatio are described subsequetly, followed by the temperature-depedet curret coductio mechaism. A. emperature-depedet Parameters For a partially-depleted SOI NMOS device, due to the eutral regio i the thi film, it ca be regarded as a combiatio of the MOS i top portio ad the parasitic BJ i the bottom portio of the thi-film. Whe derivig the temperature-depedet model, both the top MOS ad bottom parasitic bipolar effects should be icluded. here are four key temperature-depedet parameters used i the partially-depleted SOI NMOS device: itrisic cocetratio, electro mobility, geeratio/recombiatio lifetimes, ad impact ioizatio coefficiets. 1) Itrisic Cocetratio: Whe the operatig temperature rises, the badgap of the silico arrows. As a result, the itrisic cocetratio icreases. he temperature-depedet itrisic cocetratio ca be expressed as [11] E g =1:17 0 4: i =4: m m p m 2 o 0:75 1:5 exp 0Eg 2k where k is the Boltzma s costat, is the operatig temperature i Kelvis, m ad m p are the effective mass of the electro ad the hole, respectively (m = m o(1: : : );m p = m o (0:552+1: : )) [12]. Whe the itrisic cocetratio varies as the operatig temperature rises, the related Fermi-potetial ad the depletio width i the device may chage. 2) Electro Mobility: Electro mobility is depedet o the dopig desity ad the operatig temperature. Cosiderig the surface reductio factor (g s ) due to the surface scatterig effect, the temperature-depedet electro mobility ca be expressed as a fuctio of the lattice mobility ( l ) ad the impurity mobility ( i) as [13] e = g s 1 l + 1 i 01 l = l0 1:5 A i = 02:2 l 1+ B 2 0 B B 2 where A = 3: cm 01 V 01 s 01 k ad B = 1: cm 03 k 02 are depedet o the dopig desity. From simulatio results, the surface reductio factor due to the surface scatterig effect is g s =0:5. At a elevated operatig temperature, the lattice mobility ( l ), which is the domiat factor, decreases. 3) Geeratio/Recombiatio Lifetimes: For a bipolar device, the geeratio/recombiatio lifetimes are importat. I the bipolar device, the electro lifetime i the eutral regio ( ), the geeratio lifetime ( g ) ad the recombiatio lifetime ( r ) i the depletio regio affect the leakage curret of the device. he temperature- (1) (2) (3) /99$ IEEE

2 IEEE RANSACIONS ON ELECRON DEVICES, VOL. 46, NO. 1, JANUARY depedet electro lifetime, geeratio lifetime, ad recombiatio lifetime ca be expressed as [14] = 0 r =2 0 2:2 g = a 2:55 cosh where 0 is the electro lifetime at K ad a =3: ad b =20are process-depedet parameters. Whe the operatig temperature rises, the lifetimes icrease. Cosequetly, the diffusio legth L eb = k q e is affected. 4) Impact Ioizatio Coefficiet: For a partially-depleted SOI NMOS device biased i the saturatio regio, impact ioizatio i the frot chael ad the back chael with a high electric field is importat. Cosiderig the temperature-depedet impact ioizatio effect, the multiplicatio factors of the frot chael ad the back chael are M =1+ (V DS 0 V D SA )exp M B =1+ b b (V DS + bi ) exp 2:5 b 0l (V DS 0 V D SA) 0 b l b V DS + bi where l = t x 2 2 ;x = c = qn ;l 2 V b = F c ; qn si is the permittivity of the silico, ox is the permittivity of the oxide, t ox1 is the thickess of the frot gate oxide, F c is a fittig parameter [4], [5], ad bi = k q l N N is the built-i voltage. = = 2: : Whe the operatig temperature is elevated from the room temperature, the travellig electro i the chael is subject to a icrease i thermal scatterig. As a result, the capability of producig electro-hole pairs owig to collisio with lattice is reduced. herefore, the multiplicatio factors (M; M B ) are lowered whe the operatig temperature is icreased. Note that i the above equatios, ; ; b ; b are temperature-depedet empirical costats [15]. B. Curret Coductio Mechaism Whe cosiderig the curret coductio i a partially-depleted SOI NMOS device, both the top MOS ad the bottom parasitic BJ i the thi-film are importat. Whe a partially-depleted SOI NMOS device is biased with V GS >V ad V DS > 0, the thi-film regio above the buried oxide ca be eutral the parasitic p bipolar device caot be eglected. Due to the floatig body effect, the parasitic bipolar device may be biased i the forward active regio. For the parasitic p bipolar device with the body-collector juctio reverse biased, i the body-collector juctio regio, it has a reverse biased curret (I R), which is composed of the geeratio curret (I ge ) i the space charge regio ad the electro diffusio curret (I di ) i the udepleted body regio outside the space charge regio [16]: I R = I ge + I di I ge = qiaw bc 2 g I di = q D 2 i A (4) (5) (6) where W bc depletio width of the body-collector juctio (W bc = 2 ( +V ) ); qn D diffusio coefficiet i the eutral regio; A cross sectio of the curret flow i the parasitic bipolar 2 2 device (A = W (t si 0 qn )); W width of the device; t si thickess of the thi-film. Whe the operatig temperature is elevated, due to the ifluece from the itrisic carrier cocetratio, the diffusio curret (I di ) becomes importat i I R. Across the forward biased body-emitter juctio i the parasitic bipolar device, the coductig curret (I F ) is made of the recombiatio curret (I reco) i the space charge regio ad the electro diffusio curret (I ES ) [16]: where W be (W be = I F = I reco exp I reco = qiaw be 2 r I ES = q D V BE 2k=q 2 i A + I ES exp V BE k=q (7) is the depletio width of the body-emitter juctio 2 qn ). Whe V BE is small, the first portio of the above equatio domiates I F. Whe V BE is large, the secod portio becomes domiat. I additio, whe the operatig temperature is raised, the diffusio curret becomes importat. Cosiderig the MOS portio of the partially-depleted SOI NMOS device, the threshold voltage is subject to the floatig body effect. he accumulated holes ear the body-emitter juctio i the thi-film due to the parasitic bipolar device caused by the floatig body icrease the body-emitter voltage (V BE). As a result, the threshold voltage is lowered. Cosiderig this effect, the threshold voltage model (V ) ad the coductig curret through the frot chael (I CH ) uder the frot gate oxide have bee reported i [5]. I this subsectio, the curret coductio mechaisms for the MOS portio ad the parasitic bipolar portio of the partially-depleted SOI NMOS device have bee explaied. I the ext subsectio, the temperature-depedet kik effect model is derived for the device biased i the triode regio (V DS V D SA ) ad the saturatio regio (V DS > V D SA). 1) riode Regio V DS V D SA : Fig. 1(a) shows the curret coductio mechaism of the partially-depleted SOI NMOS device biased i the triode regio. I the frot chael regio ear the drai, there is o impact ioizatio. herefore, o holes are ijected ito the floatig body. As a result, the body-emitter voltage (V BE ) is small. Cosequetly, the parasitic bipolar device does ot tur o. Uder this situatio, the floatig body ca be regarded as two diodes coected back to back. At the body-emitter juctio, which is forward biased, the coductig curret is I F. At the body-collector juctio, which is reverse biased, the coductig curret is I R. Cosiderig the impact ioizatio effect at the body-collector juctio, the coductig curret is magified by a factor of M B the coductig curret becomes M B I R. Cosiderig the curret coductio of the parasitic bipolar device (I F = M BI R), from (5) (7), the body-emitter voltage ca be obtaied: V BE = 2k q l 0I reco + I 2 reco +4I ES M B (I ge + I di ) 2I ES : (8)

3 256 IEEE RANSACIONS ON ELECRON DEVICES, VOL. 46, NO. 1, JANUARY 1999 (a) Fig. 1. (b) he curret coductio mechaism i the partially-depleted SOI NMOS device biased at (a) V DS VD SA ad (b) V DS >VDSA. I the above equatio, the b ad the b used i M B are b = 7: ad b =3: : [15]. 2) Saturatio Regio V DS >V D SA : For the partially-depleted SOI NMOS device biased i the saturatio regio, the curret coductio mechaism is show i Fig. 1(b). I this regio, due to V DS >V D SA, the impact ioizatio i the frot chael regio ear the drai is importat. As a result, a large amout of holes due to the frot chael impact ioizatio are ijected ito the floatig body. Cosequetly, the accumulated holes ear the body-emitter juctio tur o the bottom parasitic bipolar device sice the body-emitter voltage V BE becomes large. From [5], i the saturatio regio, V BE ca be expressed as V BE = V BE1 + V BE2 0 V m BE1 + V m 1=m BE2 (9)

4 IEEE RANSACIONS ON ELECRON DEVICES, VOL. 46, NO. 1, JANUARY ABLE I IMPORAN PARAMEERS OF HE PARIALLY-DEPLEED SOI NMOS DEVICE UNDER SUDY where V BE1 is the V BE whe recombiatio curret domiates the parasitic bipolar device; V BE2 is the V BE whe diffusio curret domiates the parasitic bipolar device. Based o the above aalysis as show i Fig. 1(a) ad (b), the drai curret of the partiallydepleted SOI NMOS device is composed of the frot chael curret i the frot MOS portio ad the collector curret i the bottom parasitic bipolar device (see (10), show at the bottom of the page). he above formulas are the closed-form aalytical temperature-depedet kik effect model for the partially-depleted SOI NMOS device. (a) III. MODEL EVALUAION I order to verify the effectiveess of the aalytical temperaturedepedet kik effect model for the partially-depleted SOI NMOS device, the model results have bee compared with the experimetal data [9] ad two-dimesioal (2-D) simulatio results. As show i the table, the test device uder study has a chael legth of 25 m ad a chael width of 50 m. he gate oxide is 250 Å. A thi-film of 2500 Å is atop a buried oxide of 4500 Å. he dopig desity of the thi-film is cm 03. Fig. 2 shows (a) V BE ad (b) ID versus V DS of the partially-depleted SOI NMOS device biased at V GS = 3:5 V, based o the aalytical model, the experimetal data [9] [Fig. 2(b)] ad the 2-D simulatio results. As show i Fig. 2(a), at all three operatig temperatures, at the kik the bodyemitter voltage of the parasitic bipolar device has a abrupt chage. As described i the previous sectio, the sudde icrease i the body-emitter voltage at the kik i the saturatio regio is due to the accumulated holes caused by the ijectio of the hole curret geerated by impact ioizatio. As show i the figures, at a elevated operatig temperature, the kik effect is reduced. As verified by the experimetal data [Fig. 2(b)] ad the 2-D simulatio results, the aalytical model provides a good predictio of the temperaturedepedet kik effect behavior of the partially-depleted SOI NMOS device. As show i the figure, at a small V DS, the model result o V BE is deviated from the simulatio results due to the omissio of the V BE term from W bc = setece below. 2 ( +V 0V ) qn as idicated i the (b) Fig. 2. (a) VBE (b) ID versus VDS of the partially-depleted SOI NMOS device based o the aalytical model, the experimetal data [9] (b) ad the two-dimesioal (2-D) simulatio results. IV. DISCUSSION he triggerig V DS at the oset of the kik effect is depedet o the operatig temperature. Defie V kik as the triggerig V DS whe the kik effect is about to occur. At the oset of the kik effect, the body-emitter voltage is V BE = V BES +10mV (11) where V BES is V BE at V DS = VD SA. From [5], V kik is foud (see (12), show at the top of the ext page). Based o (12), Fig. 3 shows the triggerig V DS (V kik ) at the oset of the kik effect versus the operatig temperature of the partially-depleted SOI NMOS device for various thi-film dopig desities, based o the aalytical model. At a elevated operatig temperature, V kik is icreased the kik effect is suppressed. With a higher dopig desity i the thi-film, V kik is lowered the kik effect is more easily to occur sice at a ID = ICH + MB(Ige + I di ); forv DS VD SA I CH + k 1 F I ES exp V k=q M + MB I ge + I di +(10 k 1 )F I ES exp V k=q ; forv DS >VD SA: (10)

5 258 IEEE RANSACIONS ON ELECRON DEVICES, VOL. 46, NO. 1, JANUARY 1999 V kik = VD SA + 0D 2 + D D 1 D 3 2D 1 D 1 =l D 2 =l D 3 = l Ireco I CH1 exp I reco I CH1 exp I CH1 = W L ec oxv D SA VBES 2k=q V BES 2k=q e e l 2 0 VG V fb 0 2 f 0 2 f 0 V BES 0 0: p V 00:01 1+(V G 0 V fb 0 2 f 0 2 f 0 V BES 0 0:01) 0 B(V BES +0:01) VD SA : (12) Fig. 3. he triggerig V DS (V kik ) at the oset ofthe kik effect versus the operatig temperature of the partially-depleted SOI NMOS device based o the aalytical model for various thi-film dopig desities. higher dopig desity i the thi-film, the parasitic bipolar device is weaker. As a result, the impact ioizatio geerated holes are less likely to be recombied i the base of the parasitic bipolar device. Istead, they are more likely to be accumulated at the body-emitter juctio. As a result, the kik effect is more easily to occur. V. CONCLUSION I this paper, a closed-form aalytical temperature-depedet kik effect model for the partially-depleted SOI NMOS devices has bee described. Based o the body-emitter voltage model, a aalytical triggerig V DS formula for temperature-depedet kik effect has bee obtaied. Accordig to the aalytical model, at a higher operatio temperature ad with a lighter thi-film dopig desity, the oset of the kik effect occurs at a larger V DS. [3] K. Kato,. Wada, ad K. aiguchi, Aalysis of kik characteristics i silico-o-isulator MOSFE s usig two-carrier modelig, IEEE ras. Electro Devices, vol. ED-32, pp , Feb [4] H.-K. Yu, J.-S. Lyu, S.-W. Kag, ad C.-K. Kim, A physical model of floatig body thi film silico-o-isulator MOSFE with parasitic bipolar trasistor, IEEE ras. Electro Devices, vol. 41, pp , May [5] S. S. Che ad J. B. Kuo, A aalytical CAD kik effect model of partially-depleted SOI NMOS devices operatig i strog iversio, Solid-State Electro., vol. 41, o. 3, pp , Mar [6] P. Fracis, A. erao, B. Getie, D. Fladre, ad J.-P. Colige, SOI techology for high-temperature applicatios, i IEDM ech. Dig., 1992, pp [7] G. Groeseeke, J.-P. Colige, H. E. Maes, J. C. Alderma, ad S. Holt, emperature depedece of threshold voltage i thi-film SOI MOSFE s, IEEE Electro Device Lett., vol. 11, pp , Aug [8] D. Fladre, A. erao, P. Fracis, B. Getie, ad J.-P. Colige, Demostratio of the potetial of accumulatio-mode MOS trasistors o SOI substrates for high-temperature operatio (150 C, IEEE ras. Electro Device Lett., vol. 14, pp , Ja [9] D.-S Jeo ad D. E. Burk, A temperature-depedet SOI MOSFE model for high-temperature applicatio (27 C C), IEEE ras. Electro Devices, vol. 38, pp , Sept [10] J. Y. Choi ad J. G. Fossum, Aalysis ad cotrol of floatig-body bipolar effects i fully-depleted submicrometer SOI MOSFE s, IEEE ras. Electro Devices, vol. 38, pp , Jue [11] S. M. Sze, Physics of Semicoductor Devices. New York: Wiley. [12] H. D. Barber, Effective mass ad itrisic carrier cocetratio i silico, Solid-State Electro., vol. 10, o. 6, pp , [13] J. M. Dorkel ad Ph. Leturcq, Carrier mobilities i silico semiempirically related to temperature, dopig ad ijectio level, Solid- State Electro., vol. 24, o. 9, pp , [14] D. K. Schroder, he cocept of geeratio ad recombiatio lifetimes i semicoductors, IEEE ras. Electro Devices, vol. ED-29, pp , Aug [15] W. N. Grat, Electro ad hole ioizatio rates i epitaxial silico at high electric fields, Solid-State Electro., vol. 16, pp , [16] A. Bar-Lev, Semicoductors ad Electroic Devices. New York: Pretice-Hall, REFERENCES [1] M. Matloubia, C.-E. D. Che, B.-Y Mao, R. Sudaresa, ad G. P. Pollack, Modelig of the subthreshold characteristics of SOI MOS- FE s with floatig body, IEEE ras. Electro Devices, vol. 37, pp , Sept [2] D. Suh ad J. G. Fossum, A physical charge-based model for ofully depleted SOI MOSFE s ad its use i assessig floatig-body effects i SOI CMOS circuits, IEEE ras. Electro Devices, vol. 42, pp , Apr