EE105 - Fall 2006 Microelectronic Devices and Circuits

Transcription

1 EE105 - Fall 006 Microelectroic Devices ad Circuits Prof. Ja M. Rabaey (ja@eecs) Lecture 3: Semicoductor Basics (ctd) Semicoductor Maufacturig Overview Last lecture Carrier velocity ad mobility Drift currets IC resistors This lecture Diffusio currets Overview of IC fabricatio process Review of electrostatics 1

2 Admiistrativia Make-up Lecture tomorrow Fr at 3:30pm (streamed) Aother Make-up Lecture Moday at 4pm (streamed) NO LECTURE ON TUESDAY Labs start ext TU MAKE SURE TO ATTEND 3 Some other readig material Sedra ad Smith, Microelectroic Circuits, Fifth Editio, Oxford Uiversity Press Doald Neame, Microelectroics Circuit Aalysis ad Desig, Third Editio, McGraw Hill R. F. Pierret, Semicoductor Device Fudametals, Addiso Wesley, (130 Text Book) R. S. Muller ad T. I. Kamis with Masu Cha, Device Electroics for Itegrated Circuits, 3rd Editio; Wiley ad Sos, Publisher. 4

3 Resistivity Bulk silico: uiform dopig cocetratio, away from surfaces -type example: i equilibrium, o N d Whe we apply a electric field, N d J qμ E qμ N d E Coductivity σ qμnd, eff qμ( Nd Na ) Resistivity 1 1 ρ Ω cm σ q μnd, eff 5 Ohm s Law V σ tw I JA J ( tw ) σ tw E σ tw V L L L ρ L R with ρ σ t W t W σ q μnd, eff V R 6 3

4 Sheet Resistace (R s ) IC resistors have a specified thickess ot uder the cotrol of the circuit desiger Elimiate t by absorbig it ito a ew parameter: the sheet resistace (R s ) ρl R Wt ρ t L W R sq L W Number of Squares 7 Usig Sheet Resistace (R s ) Io-implated (or diffused ) IC resistor 8 4

5 Idealizatios Why does curret desity J tur? What is the thickess of the resistor? What is the effect of the cotact regios? 9 Diffusio Diffusio occurs whe there exists a cocetratio gradiet I the figure below, imagie that we fill the left chamber with a gas at temperate T If we suddely remove the divider, what happes? The gas will fill the etire volume of the ew chamber. How does this occur? 10 5

6 Diffusio (cot) The et motio of gas molecules to the right chamber was due to the cocetratio gradiet If each particle moves o average left or right the evetually half will be i the right chamber If the molecules were charged (or electros), the there would be a et curret flow The diffusio curret flows from high cocetratio to low cocetratio: 11 Diffusio Equatios Assume that the mea free path is λ Fid flux of carriers crossig x0 plae ( λ) 1 ( λ)v th λ (0) 0 (λ) 1 ( λ)v th λ 1 F vth ( ( λ) ( λ) ) 1 d d F vth (0) λ (0) + λ d F vthλ J qf qv thλ d 1 6

7 Eistei Relatio The thermal velocity is give by kt 1 * m v 1 th λ v τ th c kt τ vthλ vthτ c kt m c * kt q Mea Free Time qτ m c * Mobility D μ d kt d J qv λ q μ q kt V q th th Eistei Relatio qd d Diffusio Coefficiet 13 Total Curret Whe both drift ad diffusio are preset, the total curret is give by the sum: J J + J qμ E drift diff + qd d 14 7

8 IC Fabricatio: Photo-Lithographic Process oxidatio optical mask photoresist removal (ashig) photoresist coatig stepper exposure process step Typical operatios i a sigle photolithographic cycle (from [Fullma]). photoresist developmet acid etch spi, rise, dry 15 IC Fabricatio: Si Substrate Pure Si crystal is startig material (wafer) The Si wafer is extremely pure (~1 part i a billio impurities) Why so pure? Si desity is about 5 10 atoms/cm 3 Desire itetioal dopig from Wat uitetioal dopats to be about 1- orders of magitude less dese ~ 10 1 Si wafers are polished to about 700 μm thick (mirror fiish) The Si forms the substrate for the IC 16 8

9 IC Fabricatio: Oxide Si has a ative oxide: SiO SiO (glass) is extremely stable ad very coveiet for fabricatio It s a isulator SiO widows are etched usig photolithography These opeigs allow io implatatio ito selected regios SiO ca block io implatatio i other areas 17 IC Fabricatio: Patterig of SiO Si-substrate (a) Silico base material Si-substrate (b) After oxidatio ad depositio of egative photoresist Si-substrate (c) Stepper exposure Photoresist SiO UV-light Pattered optical mask Exposed resist Si-substrate Si-substrate Si-substrate Chemical or plasma etch Hardeed resist SiO (d) After developmet ad etchig of resist, chemical or plasma etch of SiO (e) After etchig Hardeed resist SiO SiO (f) Fial result after removal of resist 18 9

10 Diffusio Resistor N-type Diffusio Regio Oxide P-type Si Substrate Usig io implatatio/diffusio, the thickess ad dopat cocetratio of resistor is set by process E.g. 100Ω/ (usilicided), 10Ω/ (silicided) Shape of the resistor is set by desig (layout) Metal cotacts are coected to eds of the resistor Resistor is capacitively isolatio from substrate Reverse-biased PN Juctio! 19 Usig Sheet Resistace (R s ) Io-implated (or diffused ) IC resistor 0 10

11 Poly Film Resistor Polysilico Film (N+ or P+ type) Oxide P-type Si Substrate To lower the capacitive parasitics, we should build the resistor further away from substrate We ca deposit a thi film of poly Si (heavily doped) material o top of the oxide E.g Ω/ (usilicided), 1Ω/ (silicided) Bad absolute tolerace, very good relative tolerace 1 CMOS Process at a Glace Defie active areas Etch ad fill treches Implat well regios Deposit ad patter polysilico layer Implat source ad drai regios ad substrate cotacts Create cotact ad via widows Deposit ad patter metal layers 11

12 Electrostatics: a Tool for Device Modelig Gauss s Law ( E) ρ Potetial Def. E φ Poisso s Eq. ( ( φ)) φ ρ 3 Oe-Dimesioal Electrostatics Gauss s Law Potetial Def. E de dφ E ρ Poisso s Eq. d φ ( x) ρ( x) 4 1

13 Electrostatics Review (1) Electric field go from positive charge to egative charge (by covetio) ρ E I words, if the electric field chages magitude, there has to be charge ivolved! Result: I a charge-free regio, the electric field must be costat! 5 Electrostatics Review () Gauss Law equivaletly says that if there is a et electric field leavig a regio, there has to be positive charge i that regio: Electric Fields are Leavig This Box! Q E ds 6 13

14 Electrostatics i 1D Everythig simplifies i 1-D E de ρ ρ de ρ( x') E( x) E( x0) + ' Cosider a uiform charge distributio Zero field boudary coditio ρ(x) ρ 0 x 1 x x0 x x x E x ρ ( ') ρ ( ) ' 0 x 0 E(x) ρ x 1 0 x1 7 Electrostatic Potetial The electric field (force) is related to the potetial (eergy): φ d E Negative sig says that field lies go from high potetial poits to lower potetial poits (egative slope) Note: A electro should float to a high potetial poit: F e dφ qe e φ 1 F e dφ e e φ 8 14

15 More Potetial Itegratig this basic relatio, we have that the potetial is the itegral of the field: r φ( x) φ( x0) E dl I 1D, this is a simple itegral: φ( x) φ( x0) x x0 C E( x' ) ' φ( x 0 ) dl r E φ(x) Goig the other way, we have Poisso s equatio i 1D: d φ ( x) ρ( x) 9 Boudary Coditios Potetial must be a cotiuous fuctio. If ot, the fields (forces) would be ifiite Electric fields eed ot be cotiuous. We have already see that the electric fields diverge o charges. I fact, across a iterface we have: Δx E 1 ( 1 ) E ( ) E ds 1 E1S + ES Q S Q iside Δx E1S + ES E E iside 30 15

16 IC MIM Capacitor Bottom Plate Top Plate Bottom Plate Cotacts Thi Oxide Q CV By formig a thi oxide ad metal (or polysilico) plates, a capacitor is formed Cotacts are made to top ad bottom plate Parasitic capacitace exists betwee bottom plate ad substrate 31 + Review of Capacitors V s Vs E dl E0t ox V s E 0 tox Q Vs Q E ds E0A A t Q E ds For a ideal metal, all charge must be at surface Gauss law: Surface itegral of electric field over closed surface equals charge iside volume ox Q E ds Q CV s A C t ox 3 16

17 Capacitor Q-V Relatio Q V s y Q(y) y Q CV s Total charge is liearly related to voltage Charge desity is a delta fuctio at surface (for perfect metals) 33 A No-Liear Capacitor Q y V s Q(y) y Q f ( V s ) We ll soo meet capacitors that have a o-liear Q-V relatioship If plates are ot ideal metal, the charge desity ca peetrate ito surface 34 17

18 What s the Capacitace? For a o-liear capacitor, we have Q f ( V s ) CV s We ca t idetify a capacitace Imagie we apply a small sigal o top of a bias voltage: Q f ( V + v ) s s df ( V ) f ( Vs ) + dv V Vs v Costat charge s The icremetal charge is therefore: Q Q + q 0 df ( V ) f ( Vs ) + dv V Vs v s 35 Small Sigal Capacitace Break the equatio for total charge ito two terms: Q Q + q 0 Costat Charge Icremetal Charge df ( V ) f ( Vs ) + dv V Vs v s df ( V ) q dv V Vs v s C v s df ( V ) C dv V V s 36 18

19 Example of No-Liear Capacitor Next lecture we ll see that for a PN juctio, the charge is a fuctio of the reverse bias: V Q j ( V ) qnax p 1 φ b Voltage Across NP Juctio Charge At N Side of Juctio Costats Small sigal capacitace: dq j C j ( V ) dv qnax φ b p 1 V 1 φ b C j0 V 1 φ b 37 19