# EE141- Spring 2003 Lecture 3. Last Lecture

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1 - Spring 003 Lecture 3 IC Manufacturing 1 Last Lecture Design Metrics (part 1) Today Design metrics (wrap-up) IC manufacturing 1

2 Administrivia Discussion sessions start this week. Only one this week (Dejan is still stuck) We -3pm in 03 McLaughlin Homework 1 due on Th» If you have problems running SPICE, check with Huifang Labs start next week!» Make sure to get your card key coded for 353 Cory» Temporary logins have been provided for the PCs in 353 Cory. Login: ee141-temp Passward: tempaccount 3 The Week at a Glance M Lab DISC* OH TA mtng (Dejan) (Huifang) (Huifang) BWRC 353 Cory TBD 89Cory Tu Lec (Jan) 03 McLaughlin OH(Jan) 511Cory W Lab (Huifang) 353 Cory DISC* (Dejan) 03 McLaughlin OH (Dejan) 89Cory Th Lec (Jan) 03 McLaughlin Lab (both) 353 Cory <- Problem Sets Due F * Discussion sections will cover identical material 4

3 Design Metrics (wrap-up) How to quantify the quality of a gate? So far : cost & reliability Today: speed & power 5 Delay Definitions V in 50% t V out t phl t plh 90% 50% 10% t t f t r 6 3

4 Ring Oscillator v 0 v 1 v v 3 v 4 v 5 v 0 v 1 v 5 T= t p N 7 AFirst-OrderRCNetwork R v out v in C t p =ln()τ =0.69RC Important model matches delay of inverter 8 4

5 Power Dissipation Instantaneous power: p(t) =v(t)i(t) =V supply i(t) Peak power: P peak = V supply i peak Average power: 1 P ave = T ) V t+ T supply t+ T p( t dt = t t T i supply () t dt 9 Energy and Energy-Delay Power-Delay Product (PDP) = E = Energy per operation = P av t p Energy-Delay Product (EDP) = quality metric of gate = E t p 10 5

6 AFirst-OrderRCNetwork R v out v in C L E 0 1 T T Vdd = Pt ()dt = V dd i supply ()dt t = V dd C L dv out = C L V dd T T Vdd 1 E cap = P cap ()dt t = V out i cap ()dt t = C L V out dv out = --C V L dd CMOS Manufacturing Process 1 6

7 CMOS Process 13 AModernCMOSProcess gate-oxide TiSi AlCu Tungsten SiO n+ p-well p-epi poly n-well p+ SiO p+ Dual-Well Trench-Isolated CMOS Process 14 7

8 Circuit Under Design V DD V DD M M4 V in V out V out M1 M3 This two-inverter circuit (of Figure 3.5 in the text) will be manufactured in a twin-well process. 15 Circuit Layout 16 8

9 The Manufacturing Process For a great tour through the process and its different steps, check For a complete walk-through of the process (64 steps), check the Book web-page 17 Photo-Lithographic Process oxidation optical mask photoresist removal (ashing) photoresist coating stepper exposure process step Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch spin, rinse, dry 18 9

10 Patterning of SiO Si-substrate (a) Silicon base material Si-substrate (b) After oxidation and deposition of negative photoresist Si-substrate Photoresist SiO UV-light Patterned optical mask Exposed resist Si-substrate Si-substrate Si-substrate Chemical or plasma etch Hardened resist SiO (d) After development and etching of resist, chemical or plasma etch of SiO (e) After etching Hardened resist SiO SiO (c) Stepper exposure (f) Final result after removal of resist 19 CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers 0 10

11 CMOS Process Walk-Through p-epi p+ (a) Base material: p+ substrate with p-epi layer p-epi p+ SiN 3 4 SiO (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer) p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask 1 CMOS Process Walk-Through SiO (d) After trench filling, CMP planarization, and removal of sacrificial nitride n (e) After n-well and V Tp adjust implants p (f) After p-well and V Tn adjust implants 11

12 CMOS Process Walk-Through poly(silicon) (g) After polysilicon deposition and etch n+ p+ (h) After n+ source/drain and p+source/drain implants. These steps also dope the polysilicon. SiO (i) After deposition of SiO insulator and contact hole etch. 3 CMOS Process Walk-Through Al (j) After deposition and patterning of first Al layer. Al SiO (k) After deposition of SiO insulator, etching of via s, deposition and patterning of second layer of Al. 4 1

14 Design Rules Jan M. Rabaey 7 3D Perspective Polysilicon Aluminum 8 14

15 Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width» scalable design rules: lambda parameter» absolute dimensions (micron rules) 9 CMOS Process Layers Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation 30 15

16 Layers in 0.5 µmcmosprocess 31 Intra-Layer Design Rules Same Potential Different Potential Well Active Select or Contact or Via Hole Polysilicon Metal1 Metal

17 Transistor Layout Transistor Vias and Contacts 1 Via Metal to Active Contact 1 Metal to Poly Contact

18 Select Layer 3 Select Substrate Well 35 CMOS Inverter Layout GND In V DD A A Out (a) Layout A A n p-substrate Field n + p + Oxide (b) Cross-Section along A-A 36 18

19 Layout Editor 37 Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um

20 Sticks Diagram V DD 3 In 1 Out Dimensionless layout entities Only topology is important Final layout generated by compaction program GND Stick diagram of inverter 39 Next Lecture The inverter at a glance The MOS transistor 40 0

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