EE143 LAB. Professor N Cheung, U.C. Berkeley

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1 EE143 LAB 1 1

2 EE143 Equipment in Cory 218 2

3 Guidelines for Process Integration * A sequence of Additive and Subtractive steps with lateral patterning Processing Steps Si wafer Watch out for materials compatibility issues (e.g. temperature limit) Planarity is desirable for lithography, etching, and thin-film deposition Whenever possible, use self-aligned structures 3

4 Process Tem perature in C Processing Temperature and Material Failure Temperature Resist Exposure Resist Reflow Resist Spin-on Resist Bake Evaporation Deposition Sputtering Deposition Si Melting Point (1412C) CVD Ion Implantation Thermal Oxidation Post Implantation Anneal Al-Si Eutectic (560C) Dopant Diffusion Epi 4

5 Self-Aligned Silicide Process (SALICIDE) using Ion Implantation and Metal-Si reaction poly-gate TiSi 2 (metal) n + n + *Process Flow: Show Process Description and Cross-sections 5

6 A Generic CMOS Process P-well CMOS 6

7 Layout Design Rules Understand the meaning of the boundaries Use EE143 design rule values Actual layout may look different from conceptual layout when rule values are applied conceptual layout Change of design rules values will need understanding of device structures/technology (qualitative) 7

8 Summary : Parameters Affecting V T 6 OX & Q f 1 M 2 x ox n + Q n n + V C N a V B Dopant implant near Si/SiO 2 interface V G -V B = F MS + V ox +V Si 8

9 Voltage drop = area under E-field curve Accumulation V ox = Q a /C ox V Si ~ 0 V ox =qn a x d /C ox Depletion V Si = qn a x d2 /(2 s ) V ox = [qn a x dmax +Q n ]/C ox Inversion V Si = qn a x dmax2 /(2 s ) = 2 F F * For simplicity, dielectric constants assumed to be same for oxide and Si in E-field sketches 9

10 V CB increases F M increases B threshold implant X ox increases X ox increases As or P threshold implant + Q f or Q ox V CB increases F M decreases 10

11 MOSFET I-V Characteristics For V D < V Dsat I D nw L C OX V G V T V 2 DS V DS For V D > V Dsat I D I Dsat nw 2L C OX V V 2 G T Note: V Dsat = V G - V T 11

12 Small Signal Capacitance C ( Q/V G ) C ox *p-type substrate 12

13 Typical Thin Film stress : 10 8 to 5x10 10 dynes/cm 2 (10 7 dyn/cm 2 = 1 MPa) Radius of Curvature of warpage r = E s t s 2 ( 1- ) s 6 f t f Stoney Equation 13

14 MEMS Process Flow Example: to form a hollow cantilever beam 14

15 MEMS- IC Integration Example of MEMS-first approach 15

16 Thermal Oxidation Model C G stagnant layer C s SiO 2 Si Note C s C o C o C i X 0x F 1 F 2 F 3 gas transport flux diffusion flux through SiO 2 reaction flux at interface 16

17 CVD Deposition Rate [Grove Model] film F 1 F 3 Si D k s h k G o e E kt = thickness of stagnant layer F 1 D [ C G - C S ] / F F 1 3 F 3 k S C S 17

18 C(x) C p Ion Implantation Implantation Damage 0.61 C p R p x=0 C R x p R Rp x xj 2 projected range p Cp e xr 2 R p longitudin al straggle p 2 C B Ion Channeling Si Crystal deeper penetration random scattering path 18

19 Examples: Well drive-in and S/D annealing steps T(t) Thermal ( Dt) effective Budget i ( Dt) i well drive-in step S/D Anneal step time For a complete process flow, only those steps with high Dt values are important 19

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21 Depth of Focus (DOF) off point best 21

22 Normalized remianing thickness after development Photon energy dose (mj/cm2) Mormalized resist thickness Past Exam Question Positive Resist Resist cross-section after development Exposure energy dose (mj/cm2) Lateral position x ( in um) Answer Any dose < 20mJ/cm2 will work Any dose < 20mJ/cm2 will work Lateral position x ( in um) 22

23 Worst-Case Design Considerations for Etching step step height variation variation of film thickness across wafer Mask etching mask can be eroded during film etching film Substrate 23

24 Effect of RIE process variables on etching characteristics Control variable effect 24

25 Multilevel Metallization Via Interconnect

26 Electromigration Issues 26