EE-612: Lecture 22: CMOS Process Steps
|
|
- Christian O’Connor’
- 6 years ago
- Views:
Transcription
1 EE-612: Lecture 22: CMOS Process Steps Mark Lundstrom Electrical and Computer Engineering Purdue University West Lafayette, IN USA Fall 2006 NCN Lundstrom EE-612 F06 1
2 outline 1) Unit Process Operations 2) Process Variations Lundstrom EE-612 F06 2
3 unit process operations 1) Oxidation 2) Diffusion 3) Ion Implantation 4) RTA/RTP 5) Chemical Vapor Deposition 6) Lithography 7) Etching 8) Metalization 9) Well Structures 10) Isolation 11) Source / Drain structures Lundstrom EE-612 F06 3
4 useful references 1) J.D. Plummer, M.D. Deal, P.B. Griffin, Silicon VLSI Technology, Fundamentals, Practice, and Modeling, Prentice Hall, Upper Saddle River, NJ, ) S.A. Campbell, The Science and Engineering of Microelectronic Fabrication, 2nd Ed., Oxford Univ. Press, New York, Lundstrom EE-612 F06 4
5 oxidation Si + O 2 SiO 2 Si+ H 2 O SiO 2 (dry) (wet) wafers heater O 2 or H 2 O +carrier gas T = o C fused quartz furnace tube Lundstrom EE-612 F06 5
6 oxidation and doping C phophorous m > 1 boron m < 1 x m = C Si C SiO2 Lundstrom EE-612 F06 6
7 local oxidation Si 3 N 4 SiO 2 Si Lundstrom EE-612 F06 7
8 local oxidation (LOCOS) Si 3 N 4 SiO 2 field oxide Si 'bird's beak' Lundstrom EE-612 F06 8
9 constant source diffusion dopant-containing gas (e.g. POCl 3 ) C C S C(x) = C S erfc( x /2 Dt) Q = C x,t dx = 2C S Dt π 0 time ( ) x Lundstrom EE-612 F06 9
10 Limited source diffusion C C( x,t)= ( Q / π Dt )exp x /2 Dt ( ) 2 C S t = 0 predep time x Lundstrom EE-612 F06 10
11 diffusion Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si substitutional interstitialcy interstitial D(T ) = D 0 e E A /k B T oxidation enhanced diffusion Lundstrom EE-612 F06 11
12 ion implantation energetic ions bombard silicon wafer B magnet F = Q r υ r B acceleration deflection wafer I ion source Lundstrom EE-612 F06 12
13 ion implantation Si R P (E) N x ΔR P (E) ()= N p exp x R p ( ) 2 2ΔR p 2 implant damage (anneal) Q = 2π N p ΔR p Lundstrom EE-612 F06 13
14 ion implantation (ii) 1.0 B Projected range (μm) 0.1 As Acceleration energy (kev) Lundstrom EE-612 F06 14
15 channeling C() x ΔR P tilted 3 deg R P x Lundstrom EE-612 F06 15
16 rapid thermal annealing reflector lamps quartz window thermal budget Dt wafer gas inlet Lundstrom EE-612 F06 16
17 chemical vapor deposition reaction chamber Dt gas inlet wafer susceptor gas exhaust 2SiH 4 + 4NH 3 Si 3 N H 2 SiH 4 Si+2H 2 SiH 4 +O 2 SiO 2 +2H 2 silicon nitride poly silicon silicon dioxide Lundstrom EE-612 F06 17
18 plasma CVD / etching RF power in gas inlet heater wafer lower temperature reduces thermal budget Dt gas exhaust Lundstrom EE-612 F06 18
19 lithography optical source wavelength, λ lens shutter mask resist contact or proximity wafer expose, develop, etch Lundstrom EE-612 F06 19
20 projection printing α UV source lens 1 mask lens 2 wafer Lundstrom EE-612 F06 20
21 registration errors EE E E E EE EE misalignment run out Lundstrom EE-612 F06 21
22 phase shift lithography conventional mask phase shift mask electric field at mask electric field at mask intensity at wafer intensity at wafer Lundstrom EE-612 F06 22
23 pattern transfer negative resist (less soluble after exposure) wafer wafer positive resist (more soluble after exposure) resist: optically sensitive polymer which, when exposed to UV changes its solubility in specific chemicals wafer Lundstrom EE-612 F06 23
24 etching wet chemical etching (isotropic) dry etching (plasma or reactive ion etching - RIE) (anisotropic) wafer wafer undercut chemicals react with underlying material, but not resist ionized gases react with underlying material, but not resist Lundstrom EE-612 F06 24
25 pattern transfer (ii) mask chrome L Drawn lithography bias resist etch bias L Gate (physical) Lundstrom EE-612 F06 25
26 metalization Tungsten (W) plugs for first layer metal dep CMP Edition Lundstrom EE-612 F06 26
27 outline 1) Unit Process Operations 2) Process Variations Lundstrom EE-612 F06 27
28 discrete doping effects V = W L x j N + N + example: L = 50 nm W = 100 nm x j = 25 nm N A = cm -3 N TOT = 125 P (N A cm-3) Number of dopants in the critical volume is a statistical quantity Lundstrom EE-612 F06 28
29 discrete doping effects (ii) source drain Effects: 1) σ VT (10 s of mv) 2) lower avg. V T (10 s of mv) 3) asymmetry in I D 3D transport leads to inhomogeneous conduction (see Wong and Taur, IEDM, 1993, p. 705) Lundstrom EE-612 F06 29
30 discrete doping effects (iii) 35 nm MOSFET AFM measurements, Fujitsu (simulations from A. Asenov group, Univ. of Glasgow) Lundstrom EE-612 F06 30
31 statistical variability Line edge roughness discrete dopants From A. Asenov, Univ. of Glasgow Lundstrom EE-612 F06 31
32 variability is becoming a major issue G. Declerck, Keynote talk, VLSI Technol. Symp Lundstrom EE-612 F06 32
33 outline 1) Unit Process Operations 2) Process Variations For a basic, CMOS process flow for an STI (shallow trench isolation process), see: Lundstrom EE-612 F06 33
34 CMOS process flow For a basic, CMOS process flow for an STI (shallow trench isolation process), see: The author is indebted to Dr. Lynn Fuller of Rochester Institute of Technology for making these materials available. What follows is a condensed version of a more complete presentation by Dr. Fuller. I regret any errors that I may have introduced by shortening these materials. -Mark Lundstrom 10/19/06 Lundstrom EE-612 F06 34
Lecture 150 Basic IC Processes (10/10/01) Page ECE Analog Integrated Circuits and Systems P.E. Allen
Lecture 150 Basic IC Processes (10/10/01) Page 1501 LECTURE 150 BASIC IC PROCESSES (READING: TextSec. 2.2) INTRODUCTION Objective The objective of this presentation is: 1.) Introduce the fabrication of
More informationUNIT 3. By: Ajay Kumar Gautam Asst. Prof. Dev Bhoomi Institute of Technology & Engineering, Dehradun
UNIT 3 By: Ajay Kumar Gautam Asst. Prof. Dev Bhoomi Institute of Technology & Engineering, Dehradun 1 Syllabus Lithography: photolithography and pattern transfer, Optical and non optical lithography, electron,
More information4FNJDPOEVDUPS 'BCSJDBUJPO &UDI
2010.5.4 1 Major Fabrication Steps in CMOS Process Flow UV light oxygen Silicon dioxide Silicon substrate Oxidation (Field oxide) photoresist Photoresist Coating Mask exposed photoresist Mask-Wafer Exposed
More informationLECTURE 5 SUMMARY OF KEY IDEAS
LECTURE 5 SUMMARY OF KEY IDEAS Etching is a processing step following lithography: it transfers a circuit image from the photoresist to materials form which devices are made or to hard masking or sacrificial
More informationSelf-study problems and questions Processing and Device Technology, FFF110/FYSD13
Self-study problems and questions Processing and Device Technology, FFF110/FYSD13 Version 2016_01 In addition to the problems discussed at the seminars and at the lectures, you can use this set of problems
More informationFabrication Technology, Part I
EEL5225: Principles of MEMS Transducers (Fall 2004) Fabrication Technology, Part I Agenda: Microfabrication Overview Basic semiconductor devices Materials Key processes Oxidation Thin-film Deposition Reading:
More informationIon Implantation. alternative to diffusion for the introduction of dopants essentially a physical process, rather than chemical advantages:
Ion Implantation alternative to diffusion for the introduction of dopants essentially a physical process, rather than chemical advantages: mass separation allows wide varies of dopants dose control: diffusion
More informationMake sure the exam paper has 9 pages (including cover page) + 3 pages of data for reference
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Spring 2006 EE143 Midterm Exam #1 Family Name First name SID Signature Make sure the exam paper
More informationIntroduction to Photolithography
http://www.ichaus.de/news/72 Introduction to Photolithography Photolithography The following slides present an outline of the process by which integrated circuits are made, of which photolithography is
More informationCVD: General considerations.
CVD: General considerations. PVD: Move material from bulk to thin film form. Limited primarily to metals or simple materials. Limited by thermal stability/vapor pressure considerations. Typically requires
More informationSeptember 21, 2005, Wednesday
, Wednesday Doping and diffusion I Faster MOSFET requires shorter channel P + Poly Al Al Motivation Requires shallower source, drain Al P + Poly Al source drain Shorter channel length; yes, but same source
More information3.155J/6.152J Microelectronic Processing Technology Fall Term, 2004
3.155J/6.152J Microelectronic Processing Technology Fall Term, 2004 Bob O'Handley Martin Schmidt Quiz Nov. 17, 2004 Ion implantation, diffusion [15] 1. a) Two identical p-type Si wafers (N a = 10 17 cm
More informationAjay Kumar Gautam Asst. Prof. Electronics & Communication Engineering Dev Bhoomi Institute of Technology & Engineering Dehradun UNIT II
Ajay Kumar Gautam Asst. Prof. Electronics & Communication Engineering Dev Bhoomi Institute of Technology & Engineering Dehradun UNIT II Syllabus EPITAXIAL PROCESS: Epitaxy and its concept, Growth kinetics
More informationUNIVERSITY OF CALIFORNIA. College of Engineering. Department of Electrical Engineering and Computer Sciences. Professor Ali Javey.
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EE 143 Professor Ali Javey Spring 2009 Exam 2 Name: SID: Closed book. One sheet of notes is allowed.
More informationETCHING Chapter 10. Mask. Photoresist
ETCHING Chapter 10 Mask Light Deposited Substrate Photoresist Etch mask deposition Photoresist application Exposure Development Etching Resist removal Etching of thin films and sometimes the silicon substrate
More informationnmos IC Design Report Module: EEE 112
nmos IC Design Report Author: 1302509 Zhao Ruimin Module: EEE 112 Lecturer: Date: Dr.Zhao Ce Zhou June/5/2015 Abstract This lab intended to train the experimental skills of the layout designing of the
More informationEE 143 MICROFABRICATION TECHNOLOGY FALL 2014 C. Nguyen PROBLEM SET #7. Due: Friday, Oct. 24, 2014, 8:00 a.m. in the EE 143 homework box near 140 Cory
Issued: Tuesday, Oct. 14, 2014 PROBLEM SET #7 Due: Friday, Oct. 24, 2014, 8:00 a.m. in the EE 143 homework box near 140 Cory Electroplating 1. Suppose you want to fabricate MEMS clamped-clamped beam structures
More informationMake sure the exam paper has 7 pages (including cover page) + 3 pages of data for reference
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Fall 2005 EE143 Midterm Exam #1 Family Name First name SID Signature Make sure the exam paper
More informationSection 3: Etching. Jaeger Chapter 2 Reader
Section 3: Etching Jaeger Chapter 2 Reader Etch rate Etch Process - Figures of Merit Etch rate uniformity Selectivity Anisotropy d m Bias and anisotropy etching mask h f substrate d f d m substrate d f
More informationChanging the Dopant Concentration. Diffusion Doping Ion Implantation
Changing the Dopant Concentration Diffusion Doping Ion Implantation Step 11 The photoresist is removed with solvent leaving a ridge of polysilicon (the transistor's gate), which rises above the silicon
More informationIC Fabrication Technology
IC Fabrication Technology * History: 1958-59: J. Kilby, Texas Instruments and R. Noyce, Fairchild * Key Idea: batch fabrication of electronic circuits n entire circuit, say 10 7 transistors and 5 levels
More informationEE 527 MICROFABRICATION. Lecture 25 Tai-Chang Chen University of Washington
EE 527 MICROFABRICATION Lecture 25 Tai-Chang Chen University of Washington ION MILLING SYSTEM Kaufmann source Use e-beam to strike plasma A magnetic field applied to increase ion density Drawback Low etch
More informationReactive Ion Etching (RIE)
Reactive Ion Etching (RIE) RF 13.56 ~ MHz plasma Parallel-Plate Reactor wafers Sputtering Plasma generates (1) Ions (2) Activated neutrals Enhance chemical reaction 1 2 Remote Plasma Reactors Plasma Sources
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing
EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104-113) S R on D CMOS Manufacturing Process (pp. 36-46) S S C GS G G C GD
More informationChapter 8 Ion Implantation
Chapter 8 Ion Implantation 2006/5/23 1 Wafer Process Flow Materials IC Fab Metalization CMP Dielectric deposition Test Wafers Masks Thermal Processes Implant PR strip Etch PR strip Packaging Photolithography
More informationLecture 15 Etching. Chapters 15 & 16 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/76
Lecture 15 Etching Chapters 15 & 16 Wolf and Tauber 1/76 Announcements Term Paper: You are expected to produce a 4-5 page term paper on a selected topic (from a list). Term paper contributes 25% of course
More informationLecture 6 Plasmas. Chapters 10 &16 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/68
Lecture 6 Plasmas Chapters 10 &16 Wolf and Tauber 1/68 Announcements Homework: Homework will be returned to you on Thursday (12 th October). Solutions will be also posted online on Thursday (12 th October)
More informationChapter 3 Engineering Science for Microsystems Design and Fabrication
Lectures on MEMS and MICROSYSTEMS DESIGN and MANUFACTURE Chapter 3 Engineering Science for Microsystems Design and Fabrication In this Chapter, we will present overviews of the principles of physical and
More informationSection 7: Diffusion. Jaeger Chapter 4. EE143 Ali Javey
Section 7: Diffusion Jaeger Chapter 4 Surface Diffusion: Dopant Sources (a) Gas Source: AsH 3, PH 3, B 2 H 6 (b) Solid Source BN Si BN Si (c) Spin-on-glass SiO 2 +dopant oxide (d) Liquid Source. Fick s
More informationE SC 412 Nanotechnology: Materials, Infrastructure, and Safety Wook Jun Nam
E SC 412 Nanotechnology: Materials, Infrastructure, and Safety Wook Jun Nam Lecture 10 Outline 1. Wet Etching/Vapor Phase Etching 2. Dry Etching DC/RF Plasma Plasma Reactors Materials/Gases Etching Parameters
More informationIon Implant Part 1. Saroj Kumar Patra, TFE4180 Semiconductor Manufacturing Technology. Norwegian University of Science and Technology ( NTNU )
1 Ion Implant Part 1 Chapter 17: Semiconductor Manufacturing Technology by M. Quirk & J. Serda Spring Semester 2014 Saroj Kumar Patra,, Norwegian University of Science and Technology ( NTNU ) 2 Objectives
More informationLecture 0: Introduction
Lecture 0: Introduction Introduction q Integrated circuits: many transistors on one chip q Very Large Scale Integration (VLSI): bucketloads! q Complementary Metal Oxide Semiconductor Fast, cheap, low power
More informationEE C245 ME C218 Introduction to MEMS Design Fall 2010
Lecture Outline EE C245 ME C28 Introduction to MEMS Design Fall 200 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720
More informationEE 434 Lecture 7. Process Technology
EE 434 Lecture 7 Process Technology Quiz 4 How many wafers can be obtained from a 2m pull? Neglect the material wasted in the kerf used to separate the wafers. 2m And the number is. 1 8 3 5 6 4 9 7 2 1
More informationEtching: Basic Terminology
Lecture 7 Etching Etching: Basic Terminology Introduction : Etching of thin films and sometimes the silicon substrate are very common process steps. Usually selectivity, and directionality are the first
More informationEE143 LAB. Professor N Cheung, U.C. Berkeley
EE143 LAB 1 1 EE143 Equipment in Cory 218 2 Guidelines for Process Integration * A sequence of Additive and Subtractive steps with lateral patterning Processing Steps Si wafer Watch out for materials compatibility
More informationModelling for Formation of Source/Drain Region by Ion Implantation and Diffusion Process for MOSFET Device
Modelling for Formation of Source/Drain Region by Ion Implantation and Diffusion Process for MOSFET Device 1 Supratim Subhra Das 2 Ria Das 1,2 Assistant Professor, Mallabhum Institute of Technology, Bankura,
More informationDIFFUSION - Chapter 7
DIFFUSION - Chapter 7 Doping profiles determine many short-channel characteristics in MOS devices. Resistance impacts drive current. Scaling implies all lateral and vertical dimensions scale by the same
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Chenming Hu.
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Spring 2009 Professor Chenming Hu Midterm I Name: Closed book. One sheet of notes is
More informationProperties of Error Function erf(z) And Complementary Error Function erfc(z)
Properties of Error Function erf(z) And Complementary Error Function erfc(z) z erf (z) π e -y dy erfc (z) 1 - erf (z) erf () erf( ) 1 erf(- ) - 1 erf (z) d erf(z) dz π z for z
More informationDiffusion and Ion implantation Reference: Chapter 4 Jaeger or Chapter 3 Ruska N & P Dopants determine the resistivity of material Note N lower
Diffusion and Ion implantation Reference: Chapter 4 Jaeger or Chapter 3 Ruska N & P Dopants determine the resistivity of material Note N lower resistavity than p: due to higher carrier mobility Near linear
More informationEE 527 MICROFABRICATION. Lecture 24 Tai-Chang Chen University of Washington
EE 527 MICROFABRICATION Lecture 24 Tai-Chang Chen University of Washington EDP ETCHING OF SILICON - 1 Ethylene Diamine Pyrocatechol Anisotropy: (100):(111) ~ 35:1 EDP is very corrosive, very carcinogenic,
More informationEtching Issues - Anisotropy. Dry Etching. Dry Etching Overview. Etching Issues - Selectivity
Etching Issues - Anisotropy Dry Etching Dr. Bruce K. Gale Fundamentals of Micromachining BIOEN 6421 EL EN 5221 and 6221 ME EN 5960 and 6960 Isotropic etchants etch at the same rate in every direction mask
More informationEE C245 ME C218 Introduction to MEMS Design
EE C245 ME C218 Introduction to MEMS Design Fall 2008 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 6: Process
More informationDopant Diffusion. (1) Predeposition dopant gas. (2) Drive-in Turn off dopant gas. dose control. Doped Si region
Dopant Diffusion (1) Predeposition dopant gas dose control SiO Si SiO Doped Si region () Drive-in Turn off dopant gas or seal surface with oxide profile control (junction depth; concentration) SiO SiO
More informationLithography and Etching
Lithography and Etching Victor Ovchinnikov Chapters 8.1, 8.4, 9, 11 Previous lecture Microdevices Main processes: Thin film deposition Patterning (lithography) Doping Materials: Single crystal (monocrystal)
More informationIon Implantation ECE723
Ion Implantation Topic covered: Process and Advantages of Ion Implantation Ion Distribution and Removal of Lattice Damage Simulation of Ion Implantation Range of Implanted Ions Ion Implantation is the
More informationCHAPTER 6: Etching. Chapter 6 1
Chapter 6 1 CHAPTER 6: Etching Different etching processes are selected depending upon the particular material to be removed. As shown in Figure 6.1, wet chemical processes result in isotropic etching
More informationSemiconductors Reference: Chapter 4 Jaeger or Chapter 3 Ruska Recall what determines conductor, insulator and semiconductor Plot the electron energy
Semiconductors Reference: Chapter 4 Jaeger or Chapter 3 Ruska Recall what determines conductor, insulator and semiconductor Plot the electron energy states of a material In some materials get the creation
More informationGold Nanoparticles Floating Gate MISFET for Non-Volatile Memory Applications
Gold Nanoparticles Floating Gate MISFET for Non-Volatile Memory Applications D. Tsoukalas, S. Kolliopoulou, P. Dimitrakis, P. Normand Institute of Microelectronics, NCSR Demokritos, Athens, Greece S. Paul,
More informationChapter 3 Basics Semiconductor Devices and Processing
Chapter 3 Basics Semiconductor Devices and Processing Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 1 Objectives Identify at least two
More informationEE141- Spring 2003 Lecture 3. Last Lecture
- Spring 003 Lecture 3 IC Manufacturing 1 Last Lecture Design Metrics (part 1) Today Design metrics (wrap-up) IC manufacturing 1 Administrivia Discussion sessions start this week. Only one this week (Dejan
More informationFLCC Seminar. Spacer Lithography for Reduced Variability in MOSFET Performance
1 Seminar Spacer Lithography for Reduced Variability in MOSFET Performance Prof. Tsu-Jae King Liu Electrical Engineering & Computer Sciences Dept. University of California at Berkeley Graduate Student:
More informationEE C245 ME C218 Introduction to MEMS Design Fall 2007
EE C245 ME C218 Introduction to MEMS Design Fall 2007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 5: ALD,
More informationClean-Room microfabrication techniques. Francesco Rizzi Italian Institute of Technology
Clean-Room microfabrication techniques Francesco Rizzi Italian Institute of Technology Miniaturization The first transistor Miniaturization The first transistor Miniaturization The first transistor Miniaturization
More informationMATHEMATICS OF DOPING PROFILES. C(x,t) t. = D 2 C(x,t) x 2. 4Dt dx '
EE43 MATHEMATICS OF DOPING PROFILES N. Cheung The diffusion equation with constant D : has the general solution: C(x,t) = C(x,t) = D 2 C(x,t) 4πDt F(x ' ) e -(x-x' ) 2 4Dt dx ' - where F(x') is the C(x,t)
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationTechnology for Micro- and Nanostructures Micro- and Nanotechnology
Lecture 10: Deposition Technology for Micro- and Nanostructures Micro- and Nanotechnology Peter Unger mailto: peter.unger @ uni-ulm.de Institute of Optoelectronics University of Ulm http://www.uni-ulm.de/opto
More informationSemiconductor Technology
Semiconductor Technology from A to Z Deposition www.halbleiter.org Contents Contents List of Figures II 1 Deposition 1 1.1 Plasma, the fourth aggregation state of a material............. 1 1.1.1 Plasma
More informationEE143 Fall 2016 Microfabrication Technologies. Lecture 6: Thin Film Deposition Reading: Jaeger Chapter 6
EE143 Fall 2016 Microfabrication Technologies Lecture 6: Thin Film Deposition Reading: Jaeger Chapter 6 Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 Vacuum Basics Units 1 atmosphere
More informationChapter 7 Plasma Basic
Chapter 7 Plasma Basic Hong Xiao, Ph. D. hxiao89@hotmail.com www2.austin.cc.tx.us/hongxiao/book.htm Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 1 Objectives List at least three IC processes
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon
More informationWet and Dry Etching. Theory
Wet and Dry Etching Theory 1. Introduction Etching techniques are commonly used in the fabrication processes of semiconductor devices to remove selected layers for the purposes of pattern transfer, wafer
More informationPlasma Deposition (Overview) Lecture 1
Plasma Deposition (Overview) Lecture 1 Material Processes Plasma Processing Plasma-assisted Deposition Implantation Surface Modification Development of Plasma-based processing Microelectronics needs (fabrication
More informationEE C245 ME C218 Introduction to MEMS Design Fall 2007
EE C245 ME C218 Introduction to MEMS Design Fall 2007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 4: Film
More informationChapter 3 : ULSI Manufacturing Technology - (c) Photolithography
Chapter 3 : ULSI Manufacturing Technology - (c) Photolithography 1 Reference 1. Semiconductor Manufacturing Technology : Michael Quirk and Julian Serda (2001) 2. - (2004) 3. Semiconductor Physics and Devices-
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Fall Exam 1
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 143 Fall 2008 Exam 1 Professor Ali Javey Answer Key Name: SID: 1337 Closed book. One sheet
More informationNanostructures Fabrication Methods
Nanostructures Fabrication Methods bottom-up methods ( atom by atom ) In the bottom-up approach, atoms, molecules and even nanoparticles themselves can be used as the building blocks for the creation of
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationEE C245 ME C218 Introduction to MEMS Design Fall 2007
EE C245 ME C218 Introduction to MEMS Design Fall 2007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 11: Bulk
More informationMetal Deposition. Filament Evaporation E-beam Evaporation Sputter Deposition
Metal Deposition Filament Evaporation E-beam Evaporation Sputter Deposition 1 Filament evaporation metals are raised to their melting point by resistive heating under vacuum metal pellets are placed on
More informationLecture 7 Oxidation. Chapter 7 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/82
Lecture 7 Oxidation Chapter 7 Wolf and Tauber 1/82 Announcements Homework: Homework will be returned to you today (please collect from me at front of class). Solutions will be also posted online on today
More informationXing Sheng, 微纳光电子材料与器件工艺原理. Doping 掺杂. Xing Sheng 盛兴. Department of Electronic Engineering Tsinghua University
微纳光电子材料与器件工艺原理 Doping 掺杂 Xing Sheng 盛兴 Department of Electronic Engineering Tsinghua University xingsheng@tsinghua.edu.cn 1 Semiconductor PN Junctions Xing Sheng, EE@Tsinghua LEDs lasers detectors solar
More informationLecture 6. Rapid Thermal Processing. Reading: Chapter 6
Lecture 6 Rapid Thermal Processing Reading: Chapter 6 (Chapter 6) Categories: Rapid Thermal Anneal (RTA) Rapid Thermal Oxidation (RTO) Rapid Thermal Nitridation (RTN) (and oxynitrides) Rapid Thermal Diffusion
More informationEECS240 Spring Lecture 21: Matching. Elad Alon Dept. of EECS. V i+ V i-
EECS40 Spring 010 Lecture 1: Matching Elad Alon Dept. of EECS Offset V i+ V i- To achieve zero offset, comparator devices must be perfectly matched to each other How well-matched can the devices be made?
More informationChapter 8 Ion Implantation
Chapter 8 Ion Implantation Hong Xiao, Ph. D. hxiao89@hotmail.com www2.austin.cc.tx.us/hongxiao/book.htm Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 1 Objectives List at least three commonly
More informationSection 6: Ion Implantation. Jaeger Chapter 5
Section 6: Ion Imlantation Jaeger Chater 5 Ion Imlantation - Overview Wafer is Target in High Energy Accelerator Imurities Shot into Wafer Preferred Method of Adding Imurities to Wafers Wide Range of Imurity
More informationComparative studies of Ge and Si p-channel metal oxide semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate
Comparative studies of Ge and Si p-channel metal oxide semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate Hu Ai-Bin( 胡爱斌 ) and Xu Qiu-Xia( 徐秋霞 ) Institute of Microelectronics,
More informationFeature-level Compensation & Control. Process Integration September 15, A UC Discovery Project
Feature-level Compensation & Control Process Integration September 15, 2005 A UC Discovery Project Current Milestones Si/Ge-on-insulator and Strained Si-on-insulator Substrate Engineering (M28 YII.13)
More informationThere's Plenty of Room at the Bottom
There's Plenty of Room at the Bottom 12/29/1959 Feynman asked why not put the entire Encyclopedia Britannica (24 volumes) on a pin head (requires atomic scale recording). He proposed to use electron microscope
More informationChapter 7. Plasma Basics
Chapter 7 Plasma Basics 2006/4/12 1 Objectives List at least three IC processes using plasma Name three important collisions in plasma Describe mean free path Explain how plasma enhance etch and CVD processes
More informationExtensive reading materials on reserve, including
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationDEPOSITION OF THIN TiO 2 FILMS BY DC MAGNETRON SPUTTERING METHOD
Chapter 4 DEPOSITION OF THIN TiO 2 FILMS BY DC MAGNETRON SPUTTERING METHOD 4.1 INTRODUCTION Sputter deposition process is another old technique being used in modern semiconductor industries. Sputtering
More informationAtomic layer deposition of titanium nitride
Atomic layer deposition of titanium nitride Jue Yue,version4, 04/26/2015 Introduction Titanium nitride is a hard and metallic material which has found many applications, e.g.as a wear resistant coating[1],
More informationPlasma Processing in the Microelectronics Industry. Bert Ellingboe Plasma Research Laboratory
Plasma Processing in the Microelectronics Industry Bert Ellingboe Plasma Research Laboratory Outline What has changed in the last 12 years? What is the relavant plasma physics? Sheath formation Sheath
More informationIon implantation Campbell, Chapter 5
Ion implantation Campbell, Chapter 5 background why ion implant? elastic collisions nuclear and electronic stopping ion ranges: projected and lateral channeling ion-induced damage and amorphization basic
More informationEE C247B / ME C218 INTRODUCTION TO MEMS DESIGN SPRING 2016 C. NGUYEN PROBLEM SET #4
Issued: Wednesday, March 4, 2016 PROBLEM SET #4 Due: Monday, March 14, 2016, 8:00 a.m. in the EE C247B homework box near 125 Cory. 1. This problem considers bending of a simple cantilever and several methods
More informationAgenda. 1. Atomic Layer Deposition Technology
Agenda 1. Atomic Layer Deposition Technology 2. What is ALD? Atomic Layer Deposition is invented in 1977 by T. Suntola et al. - New Deposition Method for Electro-Luminescent Display (ZnS:Mn Thin Films)
More informationDefense Technical Information Center Compilation Part Notice
UNCLASSIFIED Defense Technical Information Center Compilation Part Notice ADP013351 TITLE: The Effects of Plasma Induced Damage on the Channel Layers of Ion Implanted GaAs MESFETs during Reactive Ion Etching
More informationAccelerated Neutral Atom Beam (ANAB)
Accelerated Neutral Atom Beam (ANAB) Development and Commercialization July 2015 1 Technological Progression Sometimes it is necessary to develop a completely new tool or enabling technology to meet future
More informationCMOS. Technology Doping Profiles. Simulation of 0.35 Ixm/0.25 INTRODUCTION
VLSI DESIGN 2001, Vol. 13, Nos. 4, pp. 459-- 463 Reprints available directly from the publisher Photocopying permitted by license only (C) 2001 OPA (Overseas Publishers Association) N.V. Published by license
More informationEE143 Fall 2016 Microfabrication Technologies. Lecture 7: Ion Implantation Reading: Jaeger Chapter 5
EE143 Fall 016 Microfabrication Technologies Lecture 7: Ion Imlantation Reading: Jaeger Chater 5 Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 Ion Imlantation - Overview Wafer is
More informationDevice Fabrication: Etch
Device Fabrication: Etch 1 Objectives Upon finishing this course, you should able to: Familiar with etch terminology Compare wet and dry etch processes processing and list the main dry etch etchants Become
More informationPatterning Challenges and Opportunities: Etch and Film
Patterning Challenges and Opportunities: Etch and Film Ying Zhang, Shahid Rauf, Ajay Ahatnagar, David Chu, Amulya Athayde, and Terry Y. Lee Applied Materials, Inc. SEMICON, Taiwan 2016 Sept. 07-09, 2016,
More informationReview of Semiconductor Fundamentals
ECE 541/ME 541 Microelectronic Fabrication Techniques Review of Semiconductor Fundamentals Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Page 1 Semiconductor A semiconductor is an almost insulating material,
More informationDO NOT WRITE YOUR NAME OR KAUST ID NUMBER ON THIS PAGE OR ANY OTHER PAGE PUT YOUR EXAM ID NUMBER ON THIS PAGE AND EVERY OTHER PAGE YOU SUBMIT
DO NOT WRITE YOUR NAME OR KAUST ID NUMBER ON THIS PAGE OR ANY OTHER PAGE PUT YOUR EXAM ID NUMBER ON THIS PAGE AND EVERY OTHER PAGE YOU SUBMIT WRITE YOUR SOLUTIONS ON ONLY ONE SIDE OF EMPTY SOLUTION SHEETS
More informationEE 5211 Analog Integrated Circuit Design. Hua Tang Fall 2012
EE 5211 Analog Integrated Circuit Design Hua Tang Fall 2012 Today s topic: 1. Introduction to Analog IC 2. IC Manufacturing (Chapter 2) Introduction What is Integrated Circuit (IC) vs discrete circuits?
More informationEquipment Innovation Team, Memory Fab. Center, Samsung Electronics Co. Ltd. San#16, Banwol, Taean, Hwansung, Kyungki, , Republic of Korea
Solid State Phenomena Vols. 103-104 (2005) pp 63-66 Online available since 2005/Apr/01 at www.scientific.net (2005) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/ssp.103-104.63 Development
More informationFoundations of MEMS. Chang Liu. McCormick School of Engineering and Applied Science Northwestern University. International Edition Contributions by
Foundations of MEMS Second Edition Chang Liu McCormick School of Engineering and Applied Science Northwestern University International Edition Contributions by Vaishali B. Mungurwadi B. V. Bhoomaraddi
More informationA. Optimizing the growth conditions of large-scale graphene films
1 A. Optimizing the growth conditions of large-scale graphene films Figure S1. Optical microscope images of graphene films transferred on 300 nm SiO 2 /Si substrates. a, Images of the graphene films grown
More information