EECS240 Spring Lecture 21: Matching. Elad Alon Dept. of EECS. V i+ V i-
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1 EECS40 Spring 010 Lecture 1: Matching Elad Alon Dept. of EECS Offset V i+ V i- To achieve zero offset, comparator devices must be perfectly matched to each other How well-matched can the devices be made? Not arbitrary direct function of design choices EECS40 Lecture 1
2 Device Mismatch Categories Die-to-die All devices on same chip (or wafer) have same characteristics Within die (long-range) All devices within certain region have same characteristics Local (short-range) Every device different, random Usually most important source of mismatch EECS40 Lecture 1 3 Sources of Local Variation Deterministic sources: Local poly density Sub-90nm: stress, litho interactions, Random sources: Dopant fluctuations Line-edge roughness Oxide traps Focus our modeling on random variations Deterministic handled with good layout practices EECS40 Lecture 1 4
3 References M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE JSSC, vol. 4, pp , Oct Mismatch model Statistical data for.5µm CMOS J. A. Croon, M. Rosmeulen, S. Decoutere, W. Sansen, and H. E. Maes, An easy-to-use mismatch model for the MOS transistor, IEEE JSSC, vol. 37, pp , Aug µm CMOS data EECS40 Lecture 1 5 Mismatch Statistics Total mismatch set by composite of many single, independent events Correlation distance << device dimensions E.g., number of dopant atoms implanted into the channel Individual effects are small: linear superposition holds Mismatch is zero mean, Gaussian distribution EECS40 Lecture 1 6
4 Parameter Mismatch Model σ ( P) σ A WL P ( P ) = + S D : variance of P WL : active gate area P : 0 for "good" layout P Dx : distance between device centers AP : measured area proportionality constant S : measured distance proportionality constant, x EECS40 Lecture 1 7 V T Mismatch Mismatch in V T between two identical devices: A σ = + WL VT ( VT) SV Dx.5µm CMOS process : AV, 30 mv m T NMOS µ A 35 mv µ m VT, PMOS Often largest source of offset T EECS40 Lecture 1 8
5 Drain Bias, V DS V T largely independent of V DS EECS40 Lecture 1 9 Back-Gate Bias, V SB Mismatch can depend on V SB Why? EECS40 Lecture 1 10
6 Current Matching, I D /I D Strong bias dependence (we knew that already) EECS40 Lecture 1 11 Current Factor W β = µc ox L EECS40 Lecture 1 1
7 Sources of β Mismatch Mobility variations E.g., due to dopant variations, random defects Oxide thickness variation Usually very well-controlled Edge roughness EECS40 Lecture 1 13 Edge Model σ β ( β ) σ ( W ) σ ( L) σ ( C ) σ ( µ ) = W + L + C ox ox + µ n n For: σ ( W ) 1 and σ ( L) 1 L W Simplifies to: σ β ( β ) A A AC Aµ L W ox = S D β WL W L WL WL EECS40 Lecture 1 14
8 Orientation Effects Si and transistors are not (perfectly) isotropic keep direction of current flow same! EECS40 Lecture 1 15 Distance Effect EECS40 Lecture 1 16
9 Process Dependence A Vt tends to scale with technology Proportional to t ox Also depends on doping level EECS40 Lecture µm CMOS EECS40 Lecture 1 18
10 Current Matching EECS40 Lecture 1 19 Voltage Matching EECS40 Lecture 1 0
11 Golden Rule of Layout for Matching Everything you can think of might matter Even whether or not there is metal above the devices How to avoid systematic errors? Ref: A. Hastings, The art of analog layout, Prentice Hall, 001 EECS40 Lecture 1 1 Common Centroid Layout Cancels linear gradients Required for moderate matching EECS40 Lecture 1
12 Simulating Mismatch Brute force: Monte Carlo HSPICE throws the dice EECS40 Lecture 1 3 Simulating Mismatch EECS40 Lecture 1 4
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