Chapter 8 Ion Implantation

Transcription

1 Chapter 8 Ion Implantation 2006/5/23 1 Wafer Process Flow Materials IC Fab Metalization CMP Dielectric deposition Test Wafers Masks Thermal Processes Implant PR strip Etch PR strip Packaging Photolithography Final Test Design 2006/5/23 2 1

2 Introduction Semiconductor doping in wells and S/D Two major ways to dope Diffusion Ion implantation Other application of ion implantation 2006/5/23 3 Semiconductor Doping: Diffusion An isotropic process Can t independently control dopant profile and dopant concentration Replaced by ion implantation after its introduction in mid-1970s. 2006/5/23 4 2

3 Performed in high temperature furnace Using silicon dioxide as hard mask Still used for dopant drive-in, low-end product applications Current R&D on ultra shallow junction formation. 2006/5/23 5 Dopant Oxide Deposition (or Pre-deposition) Deposited Dopant Oxide SiO 2 Si Substrate 2006/5/23 6 3

4 Oxidation SiO 2 Si Substrate 2006/5/23 7 Drive-in SiO 2 Doped junction Si Substrate 2006/5/23 8 4

5 Strip and Clean SiO 2 Si Substrate Doped junction 2006/5/23 9 Semiconductor Doping : Ion Implantation First used for atomic and nuclear research Early idea introduced in 1950 s Introduced to semiconductor manufacturing in mid-1970s. Independently control dopant profile (ion energy) and dopant concentration (ion current times implantation time) 2006/5/

6 Anisotropic dopant profile Easy to achieve high concentration dope of heavy dopant atom such as phosphorus and arsenic. 2006/5/23 11 Misalignment of the Gate Metal Gate Gate Oxide Metal Gate n-si p + S/D n-si p + S/D Aligned Misaligned 2006/5/

7 Ion Implantation, Phosphorus SiO 2 Poly Si P + n + n + P-type Silicon 2006/5/23 13 Comparison of Implantation and Diffusion Doped region SiO 2 PR Si Si Diffusion Junction depth Ion implantation 2006/5/

8 Comparison of Implantation and Diffusion Diffusion Unable to achieve high dopant concentrations High temperature, hard mask Isotropic dopant profile Cannot independently control of the dopant concentration and junction depth Batch process Ion Implantation Wide range of dopant dose (10 11 ~10 17 atoms/cm 2 ) Low temperature, photoresist mask Anisotropic dopant profile Can independently control of the dopant concentration and junction depth Both Batch and single wafer process 2006/5/23 15 Ion Implantation Control Beam current and implantation time control dopant concentration Ion energy controls junction depth Dopant profile is anisotropic 2006/5/

9 Other Applications Oxygen implantation for silicon-oninsulator (SOI) device Pre-amorphous silicon implantation on titanium film for better annealing Pre-amorphous germanium implantation on silicon substrate for profile control Polysilicon doping poly barrier formation. Silicide on top of polysilicon shorts p-n junction of the silicon and forms local interconnection 2006/5/23 17 Stopping Mechanism Ions penetrate into substrate Collide with lattice atoms Gradually lose their energy and stop Ion Random Collisions (S=S n +S e ) Channeling (S S e ) Back Scattering (S S n ) 2006/5/

10 Two Stopping Mechanism Nuclear stopping Collision with nuclei of the lattice atoms Scattered significantly Causes crystal structure damage. electronic stopping Collision with electrons of the lattice atoms Incident ion path is almost unchanged Energy transfer is very small Crystal structure damage is negligible 2006/5/23 19 Stopping Mechanism The total stopping power S total = S n + S e S n : nuclear stopping, S e : electronic stopping Low E, high A ion implantation: mainly nuclear stopping High E, low A ion implantation, electronic stopping mechanism is more important 2006/5/

11 Stopping Power and Ion Velocity I II III Stopping Power Nuclear Stopping Electronic Stopping Ion Velocity 2006/5/23 21 Ion Trajectory and Projected Range Vacuum Ion Beam Substrate Ion Trajectory Collision Projected Range Distance to the Surface 2006/5/

12 Ion Projection Range ln (Concentration) Projected Range Substrate Surface Depth from the Surface 2006/5/ Projected Range in Silicon Projected Range ( m) B As P Sb Implantation Energy (kev) 2006/5/

13 Barrier Thickness to Block 200 kev Ion Beam 1.20 Mask Thickness (micron) B P As Sb Si SiO 2 Si 3 N 4 Al PR 2006/5/23 25 Implantation Processes: Channeling If the incident angle is right, ion can travel long distance without collision with lattice atoms It causes uncontrollable dopant profile, a tail Lots of collisions Very few collisions 2006/5/

14 Channeling Effect Lattice Atoms Channeling Ion Collisional Ion Wafer Surface 2006/5/23 27 Post-collision Channeling Collisional Channeling Collisional Wafer Surface 2006/5/

15 Post-collision Channeling Collisional Channeling Collisional Dopant Concentration Distance from surface 2006/5/23 29 Implantation Processes: Channeling Ways to avoid channeling effect Tilt wafer, 7 is most commonly used Screen oxide Pre-amorphous implantation Shadowing effect Ion blocked by structures Rotate wafer and post-implantation diffusion 2006/5/

16 Shadowing Effect Ion Beam Polysilicon Substrate Doped Region Shadowed Region 2006/5/23 31 Shadowing Effect After Annealing and Diffusion Polysilicon Substrate Doped Region 2006/5/

17 Damage Process Implanted ions transfer energy to lattice atoms Atoms to break free Freed atoms collide with other lattice atoms Free more lattice atoms Damage continues until all freed atoms stop One energetic ion can cause thousands of displacements of lattice atoms 2006/5/23 33 Lattice Damage With One Ion Light Ion Damaged Region Heavy Ion Single Crystal Silicon 2006/5/

18 Implantation Processes: Damage Ion collides with lattice atoms and knock them out of lattice grid Implant area on substrate becomes amorphous structure Before Implantation After Implantation 2006/5/23 35 Implantation Processes: Anneal Dopant atom must in single crystal structure and bond with four silicon atoms to be activated as donor (N-type) or acceptor (P-type) Thermal energy from high temperature helps amorphous atoms to recover single crystal structure. 2006/5/

19 Thermal Annealing Lattice Atoms Dopant Atom 2006/5/23 37 Thermal Annealing Lattice Atoms Dopant Atom 2006/5/

20 Thermal Annealing Lattice Atoms Dopant Atom 2006/5/23 39 Thermal Annealing Lattice Atoms Dopant Atom 2006/5/

21 Thermal Annealing Lattice Atoms Dopant Atom 2006/5/23 41 Thermal Annealing Lattice Atoms Dopant Atom 2006/5/

22 Thermal Annealing Lattice Atoms Dopant Atom 2006/5/23 43 Thermal Annealing Lattice Atoms Dopant Atoms 2006/5/

23 Implantation Processes: Annealing Before Annealing After Annealing 2006/5/23 45 Rapid Thermal Annealing (RTA) At high temperature, annealing out pace diffusion Rapid thermal process (RTP) is widely used for post-implantation anneal RTA is fast (less than a minute), better WTW uniformity, better thermal budget control, and minimized the dopant diffusion 2006/5/

24 RTP and Furnace Annealing Poly Si Gate Gate SiO 2 Poly Si Si Source/Drain Si RTP Annealing Furnace Annealing 2006/5/23 47 Ion Implantation: Hardware Gas system Electrical system Vacuum system Ion beamline 2006/5/

25 Ion Implanter Gas Cabin Electrical System Analyzer Magnet Ion Source Vacuum Pump Beam Line Electrical System Plasma Flooding System Vacuum Pump Wafers End Analyzer 2006/5/23 49 Ion Implantation: Beamline Ion source Extraction electrode Analyzer magnet Post acceleration Plasma flooding system End analyzer 2006/5/

26 Ion Beam Line Suppression Electrode Analyzer Magnet Ion Source Vacuum Pump Beam Line Extraction Electrode Post Acceleration Electrode Plasma Flooding System Vacuum Pump Wafers End Analyzer 2006/5/23 51 Ion implanter: Ion Source Hot tungsten filament emits thermal electron Electrons collide with source gas molecules to dissociate and ionize Ions are extracted out of source chamber and accelerated to the beamline RF and microwave power can also be used to ionize source gas 2006/5/

27 Ion Source Filament Power, 0-5V, up to 200A Arc Power ~ 120 V - + Source Gas or Vapor Tungsten Filament Plasma Magnetic Field Line Anti-cathode Source Magnet 2006/5/23 53 RF Ion Source Dopant Gas + - RF Plasma RF Coils Ion Beam Extraction Electrode 2006/5/

28 Microwave Ion Source Microwave Magnetic Coils ECR Plasma Magnetic Field Line Extraction Electrode 2006/5/23 55 Ion Implantation: Extraction Extraction electrode accelerates ions up to 50 kev High energy is required for analyzer magnet to select right ion species. 2006/5/

29 Extraction Assembly Suppression Electrode Ion Source Plasma Extraction Electrode Top View Ion Beam + Extraction Power, up to 60 kv Suppression Power, up to 10 kv + Terminal Chassis Slit Extracting Ion Beam 2006/5/23 57 Ion Implantation: Analyzer Magnet Gyro radius of charge particle in magnetic field relate with B-field and mass/charge ratio Used for isotope separation to get enriched U 235 Only ions with right mass/charge ratio can go through the slit Purified the implanting ion beam 2006/5/

30 Analyzer Magnetic Field (Point Outward) Ion Beam Larger m/q Ratio Flight Tube Smaller m/q Ratio Right m/q Ratio 2006/5/23 59 Ions in BF 3 Plasma Ions Atomic or molecule weight 10 B B BF BF 30 F BF BF /5/

31 Ion Implantation: Post Acceleration Increasing (sometimes decreasing) ion energy for ion to reach the required junction depth determined by the device Electrodes with high DC voltage Adjustable vertical vanes control beam current 2006/5/23 61 Ion Implantation: Plasma Flooding System Ions cause wafer charging Wafer charging can cause non-uniform doping and arcing defects Elections are flooding into ion beam and neutralized the charge on the wafer Argon plasma generated by thermal electrons emit from hot tungsten filament 2006/5/

32 Post Acceleration Suppression Electrode Acceleration Electrode Ion Beam Terminal Chassis Suppression Power, up to 10 kv + Post Accel. Power, up to 60 kv /5/23 63 Ion Beam Current Control Fixed Defining Aperture Ion Beam Adjustable Vertical Vanes 2006/5/

33 Bending Ion Trajectory Neutral Atom Trajectory Bias Electrode Ion Trajectory Wafer 2006/5/23 65 Charge Neutralization System Implanted ions charge wafer positively Cause wafer charging effect Expel positive ion, cause beam blowup and result non-uniform dopant distribution Discharge arcing create defects on wafer Breakdown gate oxide, low yield Need eliminate or minimize charging effect 2006/5/

34 Charging Effect Ions trajectory Wafer /5/23 67 Charge Neutralization System Need to provide electrons to neutralize ions Plasma flooding system Electron gun Electron shower are used to 2006/5/

35 Plasma Flooding System Filament Current DC Power + Tungsten Filament Plasma Ar Ion Beam Electrons Wafer 2006/5/23 69 Electron Gun Secondary Electron Target Electrons Secondary Electrons Ion Beam Electron Gun Thermal Filament Wafer 2006/5/

36 Beam Stop Graphite Top View Ion Beam Magnets Water Cooled Base Plate Faraday Current Detectors 2006/5/23 71 Ion Implantation: The Process CMOS applications CMOS ion implantation requirements Implantation process evaluations 2006/5/

37 CMOS Implantation Requirements Implant Step 0.35 m, 64 Mb 0.25 m, 256 Mb 0.18 m, 1 Gb N-well Well P/600/ P/400/ P/300/ Anti-punch through P/100/ As/100/ As/50/ Threshold B/10/ B/5/ B/2/ Poly dope P/30/ B/20/ B/20/ Poly diffusion block - - N 2 /20/ Lightly doped drain (LDD) B/7/ B/5/ B/2/ Halo (45 implant) - - As/30/ Source/drain contact B/10/ B/7/ B/6/ P-well Well B/225/ B/200/ B/175/ Anti-punch through B/30/ B/50/ B/45/ Threshold B/10/ B/5/ B/2/ Poly dope P/30/ P/20/ As/40/ Poly diffusion block - - N 2 /20/ Lightly doped drain (LDD) P/20/ P/12/ P/5/ Halo (45 implant) B/30/ B/20/ B/7/ Source/drain contact As/30/ As/20/ As/15/ /5/23 73 Implantation Process: Well Implantation High energy (to MeV), low current (10 13 /cm 2 ) P + Photoresist N-Well P-Epi P-Wafer 2006/5/

38 Implantation Process: V T Adjust Implantation Low Energy, Low Current STI Photoresist USG P-Well P-Epi P-Wafer B + N-Well 2006/5/23 75 Lightly Doped Drain (LDD) Implantation Low energy (10 kev), low current (10 13 /cm 2 ) P + STI Photoresist USG P-Well N-Well P-Epi P-Wafer 2006/5/

39 Implantation Process: S/D Implantation Low energy (20 kev), high current (>10 15 /cm 2 ) P + Photoresist STI n + n + P-Well USG P-Epi P-Wafer N-Well 2006/5/23 77 Ion Implantation Processes Ion Implantation Energy Current Well High energy low current Source/Drain Low energy high current V T Adjust Low energy low current LDD Low energy low current 2006/5/

40 Process Issues Wafer charging Particle contamination Elemental contamination Process evaluation 2006/5/23 79 Wafer Charging Break down gate oxide Dielectric strength of SiO 2 : ~10 MV/cm 100 Å oxide breakdown voltage is 10 V Gate oxide: 30 to 35 Å for 0.18 m device Require better charge neutralization 2006/5/

41 Wafer Charging Monitoring Antenna capacitor changing test structure The ratio of polysilicon pad area and thin oxide area is called antenna ratio Can be as high as 100,000:1 The larger antenna ratio, the easier to breakdown the thin gate oxide 2006/5/23 81 Antenna Ratio Top View Side View Polysilicon Field Oxide Silicon Substrate Gate Oxide 2006/5/

42 Particle Contamination Large particles can block the ion beam especially for the low energy processes, V T adjust, LDD and S/D implantations, Cause incomplete dopant junction. Harmful to yield 2006/5/23 83 Effect of Particle Contamination Ion Beam Dopant in PR Particle Photoresist Screen Oxide Partially Implanted Junctions 2006/5/

43 Elemental Contamination Co-implantation other elements with intended dopant 94 Mo ++ and 11 BF 2 +, same mass/charge ratio (A/e = 49) Mass analyzer can t separate these two 94 Mo ++ causes heavy metal contamination Ion source can t use standard stainless steel Other materials such as graphite and tantalum are normally used 2006/5/23 85 Process Evaluation Four-point probe Thermal wave Optical measurement system (OMS) 2006/5/

44 Thermal Wave System Argon pump laser generates thermal pulses on wafer surface He-Ne probe laser measures DC reflectivity (R) and reflectivity modulation induced by the pump laser ( R) at the same spot Ratio R/R is called thermal wave (TW) signal, TW signal R/R related to the crystal damage crystal damage is a function of the implant dose 2006/5/23 87 Thermal Wave System I R R Thermal Waver Signal Detector Pump Laser t I Probe Laser t R/R: Thermal Wave Signal Wafer 2006/5/

45 Thermal Wave System Performed immediately after the implant process Four-point probe needs anneal first Non-destructive, can measure production wafers Four-point probe is only good for test wafers Low sensitivity at low dosage Drift of the TW signal over time needs to be taken as soon as the implantation finished Don t have very high measurement accuracy Laser heating relax crystal damage 2006/5/23 89 Ion Implantation: Safety One of most hazardous process tools in semiconductor industry Chemical Electro-magnetic Mechanical 2006/5/

46 Ion Implantation: Chemical Safety Most dopant materials are highly toxic, flammable and explosive. Poisonous and explosive: AsH 3, PH 3, B 2 H 6 Corrosive: BF 3 Toxic: P, B, As, Sb Common sense: get out first, let the trained people to do the investigation. 2006/5/23 91 Ion Implantation: Electro-magnetic Safety High voltage: from facility 208 V to acceleration electrode up to 50 kv. Ground strip, Work with buddy! Lock & tag Magnetic field: pacemaker, etc. 2006/5/

47 Ion Implantation: Radiation Safety High energy ions cause strong X-ray radiation Normally well shield 2006/5/23 93 Ion Implantation: Corrosive by-products BF 3 as dopant gas Fluorine will react with hydrogen to from HF Anything in the beamline could have HF Double glove needed while wet clean those parts 2006/5/

48 Ion Implantation: Mechanical Safety Moving parts, doors, valves and robots Spin wheel Hot surface 2006/5/23 95 Technology Trends Ultra shallow junction (USJ) Silicon on insulator (SOI) Plasma immersion ion implantation (PIII) 2006/5/

49 Ultra Shallow Junction (USJ) USJ (x j 0.05 m) for sub-0.1 m devices p-type junction, boron ion beam at extremely low energy, as low as 0.2 kev The requirements for the USJ Shallow Low sheet resistance Low contact resistance Minimal impact on channel profile Compatible with polysilicon gate 2006/5/23 97 CMOS on SOI Substrate n + source/drain Gate oxide Polysilicon p + source/drain p-si STI Buried oxide Balk Si n-si USG 2006/5/

50 SOI Formation Implanted wafers Heavy oxygen ion implantation High temperature annealing Bonded wafers Two wafers Grow oxide on one wafer High temperature bond wafer bonding Polish one wafer until thousand Å away from SiO /5/23 99 Oxygen Ion Implantation Silicon with lattice damage Oxygen rich silicon Balk Si 2006/5/

51 High Temperature Annealing Single crystal silicon Silicon dioxide Balk Si 2006/5/ Plasma Immersion Ion Implantation Deep trench capacitor for DRAM Deeper and narrower Very difficult to heavily dope both sidewall and bottom by ion implantation Plasma immersion ion implantation (PIII) An ion implantation process without precise ion species and ion energy selection 2006/5/

52 Deep Trench Capacitor Polysilicon Heavily doped Si Dielectric Layer Silicon Substrate 2006/5/ ECR Plasma Immersion System Microwave Magnet Coils Magnetic field line E-chuck Helium Bias RF ECR plasma Wafer 2006/5/

53 Summary of Ion Implantation Dope semiconductor Better doping method than diffusion Easy to control junction depth (by ion energy) and dopant concentration ( by ion current and implantation time). Anisotropic dopant profile. 2006/5/ Summary of Ion Implantation Ion source Extraction Analyzer magnets Post acceleration Charge neutralization system Beam stop 2006/5/

54 Summary of Ion Implantation Well Source/Drain Vt Adjust LDD High energy, low current Low energy, high current Low energy, low current Low energy, low current 2006/5/