UNIVERSITY OF CALIFORNIA. College of Engineering. Department of Electrical Engineering and Computer Sciences. Professor Ali Javey.
|
|
- Karen Hamilton
- 5 years ago
- Views:
Transcription
1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EE 143 Professor Ali Javey Spring 2009 Exam 2 Name: SID: Closed book. One sheet of notes is allowed. There are a total of 15 pages on this exam, including the cover page. Problem 1 41 Problem 2 32 Problem 3 19 Problem 4 8 Total 100 1
2 Physical Constants Electronic charge q C Permittivity of vacuum ε F cm 1 Relative permittivity of silicon ε Si /ε Boltzmann s constant k x 10 5 ev/ K or J K 1 Thermal voltage at T = 300K kt/q V Effective density of states N c 2.8 x cm 3 Effective density of states N v 1.04 x cm 3 Silicon Band Gap E G 1.12 ev 2
3 Solid Solubility Limits Information which may be useful: 3
4 Diffusion Information which may be useful: 4
5 Ion Implantation Information which may be useful: 5
6 Problem 1: Doping (41 pts) 1. An ion implantation step (dose= =10 14 cm 2, R p p=0.0226um, ΔR p =0.0102um) implants Arsenic (As) into a p type semiconductor material with uniformly doped boron (B) background concentration of cm 3. The total thickness of this Si wafer is 300 µm. A. Find the peak As concentration, N p ( 5 pts) N P = Δ R P 1 Q 10 = 2π = π points for equation 2.5 points for the result B. Qualitatively draw the As and B concentration profiles. Clearly indicate and label the projected range and the peak concentration. Assume an ideal Gaussian profile. (5 pts) 6
7 C. Find the junction depth(s) right after the implantation (5 pts) N B x = 10 j 16 = = 64nm N p 2.5 points for equation 2.5 points for the result ( x j R p ) 2 exp 2 2ΔR p D. The sample is now thermally annealed at 950 C for a fraction of a second. Qualitatively draw the Arsenic and boron profiles of this sample after high temperature annealing with and without transient enhanced diffusion (TED). Indicate clearly which curve has TED effect. Here, you do not have to consider electric field enhanced diffusion. (5 pts) E. If we increase the implantation energy and dose, will the TED effect be more prominent? Briefly explain (1 sentence). (3pts) Yes. More defects will be induced by using higher energy and/ /or dose. 7
8 F. Redraw the As and B profiles of the sample after thermal annealing, this time ignoring TED but including the electric field enhanced diffusion. Label the direction of the e field as well. (5pts) G. We do high temperature annealing at 1000 C for a long time, say two week. Redraw the As and B profiles. Assume the result in section F to be your starting point. (5 pts) 8
9 H. Besides the various effects covered in the previous parts of this question, channeling could also affect the dopant profile after the ion implantation step. Briefly explain the channeling effect and list/describe two approaches for reducing the channeling effect (4 sentences max). (4 pts) If the ions are implanted through the Si lattice in the <110> direction, then they may miss the Si atoms and channel much more deeply into the material than otherwise predicted Tilt the substrate and amorphization of the surface 2 points for the explanation 2 points for the prevention ways I. Achieving ultrashallow junctions as the source/drain extensions of nanoscale MOSFETs is a challenging field of active research. Speculate whether enabling ultrashallow junctions is more difficult for p+ or n+ doping. Briefly justify your answer (3 sentences max). (4 pts) p+ is harder because B is lighter than As, and hence go deeper upon implanting. Also, B diffuses faster than As (i.e. B has a higher diffusion coefficient) during high temperature post implant steps such as annealing. 9
10 Problem 2: Etching (32 pts) A. List the three main mechanistic steps involved in a wet etching process. (3 pts) 1. transport_(absorption) of reactants_ 2. reaction 3. desorption of by product B. Increasing the temperature typically results in an increased etch rate. Briefly explain why that is the case. Specifically answer this question in reference to the mechanistic steps listed in A. (5 pts) [1] Reaction rate increases with increasing temperature. [2] Transport (absorption) rate increases with increasing temperature. [3] Desorption rate increases with increasing temperature. +0 for none +5 for [1] only +2.5 for [2] only +2.5 for [3] only +5 for both [1] and [2] +5 for both [1] and [3] +2.5 for both [2] and [3] +5 for all three of them, [1] and [2] and [3] C. Increasing the concentration of the reactant typically results in an increased etch rate. Briefly explain why that is the case. Specifically answer this question in reference to the mechanistic steps listed in A. (5 pts) [1] Reaction rate increases with increasing concentration. [2] Transport (absorption) rate increases with increasing concentration. [3] Desorption rate is not affected. +0 for none +2.5 for [1] only +5 for [2] only +0 for [3] only +5 for both [1] and [2] +1.5 for both [1] and [3] +4 for both [2] and [3] +4 for all three of them, [1] and [2] and [3] 10
11 D. Stirring the etching solution typically results in an increased etch rate. Briefly explain why that is the case. Specifically answer this question in reference to the mechanistic steps listed in A. (5 pts) [1] Reaction rate is not affected. [2] Transport (absorption) rate increases with increasing agitation. [3] Desorption rate increases with increasing agitation. +0 for none +0 for [1] only +2.5 for [2] only +2.5 for [3] only +1.5 for both [1] and [2] +1.5 for both [1] and [3] +5 for both [2] and [3] +4 for all three of them, [1] and [2] and [3] E. List the three main disadvantages of wet etching over dry etching. (3 pts) Isotropic, Contamination, Lack of control, Lack of uniformity, Inadequate for defining very fine features, Potential of chemical handling hazards +1 for each disadvantage stated, max 3pts F. Consider a 1um thick photoresist pattern shown below. A dry etch is performed on the sample with the etch rate of oxide being 100 nm/min. 1 um PR PR 0.5 um Oxide Si Substrate If the selectivity of PR versus oxide is 1:10 (i.e., Oxide etch rate is 10X faster than PR), redraw the figure after 1min and 5mins etching. (6 pts) 1.02 um 1.1 um PR 45? 45? PR PR 45? 0.5 um Oxide 0.4 um 0.5 um Oxide Si Substrate Si Substrate 45? PR 11
12 +3 for the correct profile after 1min; +1 for the lateral dimension of the trench, 1.02 μm +1 for the vertical dimension of the trench, 0.1 μm +1 for the sidewall angle, ~ for the right etch profile after 5mins; +1 for the lateral dimension of the trench, 1.1 μm +1 for the vertical dimension of the trench, 0.5 μm +1 for the sidewall angle, ~84.29 G. Starting with sidewall angle of PR, θ P R (sidewall angle is the angle between sidewall and the substrate. For example, θ PR =45 shown above), derive the sidewall angle of the etched oxide, θ OX, as a function of selectivity (i.e. oxide etching rate is s times faster than PR etching rate). (5 pts) 12
13 Problem 3: Deposition (19 pts) a) Assume a starting substrate profile shown below. A conformal deposition of Al2O3 is then performed with a deposition rate of 0.1 micron/min. Sketch the cross sections of the deposited film for a completely conformal deposition after 1 min, 2 min, and 4min of deposition. (6 pts) Total 6 points. (2 pt for each curve and 1pt for conformal coverage each curve) 13
14 b) For chemical vapor deposition of poly Si using SiCl 4 as a gaseous source, the vapor phase masstransfer coefficient hg = 1 cm/sec, the surface reaction rate constant k s = 2x10 6 exp( 1.9eV/kT) cm/sec, and the concentration of Si atoms in the gas stream Cg = 3x10 16 atoms/cm 3. (The atomic concentration of solid Si is 5x10 22 atoms/cm 3.) (6 pts) i) What is the growth rate at 500 C? The growth rate of a silicon layer can be calculated using v J kh s g Cg N k + h N s = = s g 1.5pt Use h = 1 cm/sec, g ks 5 k ev / K v 6 = 2 10 exp( 1.9 / kt), Cg =, T=773K, we can get the growth rate is 13 = cm/ s 1.5pt ii) At what temperature does k s = h g? 16 3 = 3 10 atoms/ cm, N 22 3 = 5 10 cm, If ks = h, then we have g exp( 1.9 / kt ) 1 =. 1.5pt We can get T=1519.7K by solving the equation. 1.5pt c) List the major advantages of using chemical vapor deposition versus physical vapor deposition for thin films. (4 pts) Adv. of CVD over PVD: - Better coverage of the surface. 2pt - Better Uniformity. 2pt d) List the major advantages of using sputtering deposition versus evaporation deposition for thin films. (3 pts) Advantages of sputtering over evaporation: - For multi component films, sputtering gives better composition control using compound targets. Evaporation depends on vapor pressure of various vapor components and is difficult to control. - Better lateral thickness uniformity(lager target for sputtering and superposition of multiple point sources). - Better coverage. Total 3 points. For each advantage, you get 1.5 point. 14
15 Problem 4: Oxidation (8 pts) We have a structure shown below. This structure is placed in a furnace and oxidized at 900ºC in the presence of dry oxygen in order to grow a thin layer of SiO2. Draw the schematic of this structure after the dry oxidation process. In particular, make sure that your drawing emphasizes the relative thickness and the surface profile/ /morphology of SiO2 obtained in different regions. (8 pts) (Newly formed) oxide thickness: region (ii) > (iii) > (i) > (iv) (no oxide) Bird s beak: 2 pts 15
Make sure the exam paper has 9 pages (including cover page) + 3 pages of data for reference
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Spring 2006 EE143 Midterm Exam #1 Family Name First name SID Signature Make sure the exam paper
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 130 Professor Ali Javey Fall 2006
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Professor Ali Javey Fall 2006 Midterm 2 Name: SID: Closed book. Two sheets of notes are
More informationMake sure the exam paper has 7 pages (including cover page) + 3 pages of data for reference
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Fall 2005 EE143 Midterm Exam #1 Family Name First name SID Signature Make sure the exam paper
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Fall Exam 1
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 143 Fall 2008 Exam 1 Professor Ali Javey Answer Key Name: SID: 1337 Closed book. One sheet
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Chenming Hu.
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Spring 2009 Professor Chenming Hu Midterm I Name: Closed book. One sheet of notes is
More informationMidterm I - Solutions
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Spring 2008 Professor Chenming Hu Midterm I - Solutions Name: SID: Grad/Undergrad: Closed
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Ali Javey. Spring 2009.
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EE143 Professor Ali Javey Spring 2009 Exam 1 Name: SID: Closed book. One sheet of notes is allowed.
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 130 Professor Ali Javey Fall 2006
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Professor Ali Javey Fall 2006 Midterm I Name: Closed book. One sheet of notes is allowed.
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Ali Javey. Fall 2009.
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EE143 Professor Ali Javey Fall 2009 Exam 1 Name: SID: Closed book. One sheet of notes is allowed.
More information3.155J/6.152J Microelectronic Processing Technology Fall Term, 2004
3.155J/6.152J Microelectronic Processing Technology Fall Term, 2004 Bob O'Handley Martin Schmidt Quiz Nov. 17, 2004 Ion implantation, diffusion [15] 1. a) Two identical p-type Si wafers (N a = 10 17 cm
More informationQuiz #1 Practice Problem Set
Name: Student Number: ELEC 3908 Physical Electronics Quiz #1 Practice Problem Set? Minutes January 22, 2016 - No aids except a non-programmable calculator - All questions must be answered - All questions
More informationSelf-study problems and questions Processing and Device Technology, FFF110/FYSD13
Self-study problems and questions Processing and Device Technology, FFF110/FYSD13 Version 2016_01 In addition to the problems discussed at the seminars and at the lectures, you can use this set of problems
More informationFabrication Technology, Part I
EEL5225: Principles of MEMS Transducers (Fall 2004) Fabrication Technology, Part I Agenda: Microfabrication Overview Basic semiconductor devices Materials Key processes Oxidation Thin-film Deposition Reading:
More informationIon Implantation. alternative to diffusion for the introduction of dopants essentially a physical process, rather than chemical advantages:
Ion Implantation alternative to diffusion for the introduction of dopants essentially a physical process, rather than chemical advantages: mass separation allows wide varies of dopants dose control: diffusion
More informationIon Implantation ECE723
Ion Implantation Topic covered: Process and Advantages of Ion Implantation Ion Distribution and Removal of Lattice Damage Simulation of Ion Implantation Range of Implanted Ions Ion Implantation is the
More informationIon Implant Part 1. Saroj Kumar Patra, TFE4180 Semiconductor Manufacturing Technology. Norwegian University of Science and Technology ( NTNU )
1 Ion Implant Part 1 Chapter 17: Semiconductor Manufacturing Technology by M. Quirk & J. Serda Spring Semester 2014 Saroj Kumar Patra,, Norwegian University of Science and Technology ( NTNU ) 2 Objectives
More informationLecture 150 Basic IC Processes (10/10/01) Page ECE Analog Integrated Circuits and Systems P.E. Allen
Lecture 150 Basic IC Processes (10/10/01) Page 1501 LECTURE 150 BASIC IC PROCESSES (READING: TextSec. 2.2) INTRODUCTION Objective The objective of this presentation is: 1.) Introduce the fabrication of
More informationEE143 LAB. Professor N Cheung, U.C. Berkeley
EE143 LAB 1 1 EE143 Equipment in Cory 218 2 Guidelines for Process Integration * A sequence of Additive and Subtractive steps with lateral patterning Processing Steps Si wafer Watch out for materials compatibility
More informationPlasma Deposition (Overview) Lecture 1
Plasma Deposition (Overview) Lecture 1 Material Processes Plasma Processing Plasma-assisted Deposition Implantation Surface Modification Development of Plasma-based processing Microelectronics needs (fabrication
More informationChemical Vapor Deposition (CVD)
Chemical Vapor Deposition (CVD) source chemical reaction film substrate More conformal deposition vs. PVD t Shown here is 100% conformal deposition ( higher temp has higher surface diffusion) t step 1
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE 105: Microelectronic Devices and Circuits Spring 2008 MIDTERM EXAMINATION #1 Time
More informationReactive Ion Etching (RIE)
Reactive Ion Etching (RIE) RF 13.56 ~ MHz plasma Parallel-Plate Reactor wafers Sputtering Plasma generates (1) Ions (2) Activated neutrals Enhance chemical reaction 1 2 Remote Plasma Reactors Plasma Sources
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EECS 40 Spring 2000 Introduction to Microelectronic Devices Prof. King MIDTERM EXAMINATION
More informationEE-612: Lecture 22: CMOS Process Steps
EE-612: Lecture 22: CMOS Process Steps Mark Lundstrom Electrical and Computer Engineering Purdue University West Lafayette, IN USA Fall 2006 NCN www.nanohub.org Lundstrom EE-612 F06 1 outline 1) Unit Process
More informationSection 7: Diffusion. Jaeger Chapter 4. EE143 Ali Javey
Section 7: Diffusion Jaeger Chapter 4 Surface Diffusion: Dopant Sources (a) Gas Source: AsH 3, PH 3, B 2 H 6 (b) Solid Source BN Si BN Si (c) Spin-on-glass SiO 2 +dopant oxide (d) Liquid Source. Fick s
More informationEE 143 Microfabrication Technology Fall 2014
EE 143 Microfabrication Technology Fall 2014 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 EE 143: Microfabrication
More informationChapter 8 Ion Implantation
Chapter 8 Ion Implantation 2006/5/23 1 Wafer Process Flow Materials IC Fab Metalization CMP Dielectric deposition Test Wafers Masks Thermal Processes Implant PR strip Etch PR strip Packaging Photolithography
More informationDIFFUSION - Chapter 7
DIFFUSION - Chapter 7 Doping profiles determine many short-channel characteristics in MOS devices. Resistance impacts drive current. Scaling implies all lateral and vertical dimensions scale by the same
More informationEE143 Fall 2016 Microfabrication Technologies. Lecture 6: Thin Film Deposition Reading: Jaeger Chapter 6
EE143 Fall 2016 Microfabrication Technologies Lecture 6: Thin Film Deposition Reading: Jaeger Chapter 6 Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 Vacuum Basics Units 1 atmosphere
More informationIC Fabrication Technology
IC Fabrication Technology * History: 1958-59: J. Kilby, Texas Instruments and R. Noyce, Fairchild * Key Idea: batch fabrication of electronic circuits n entire circuit, say 10 7 transistors and 5 levels
More informationnmos IC Design Report Module: EEE 112
nmos IC Design Report Author: 1302509 Zhao Ruimin Module: EEE 112 Lecturer: Date: Dr.Zhao Ce Zhou June/5/2015 Abstract This lab intended to train the experimental skills of the layout designing of the
More informationCVD: General considerations.
CVD: General considerations. PVD: Move material from bulk to thin film form. Limited primarily to metals or simple materials. Limited by thermal stability/vapor pressure considerations. Typically requires
More informationDO NOT WRITE YOUR NAME OR KAUST ID NUMBER ON THIS PAGE OR ANY OTHER PAGE PUT YOUR EXAM ID NUMBER ON THIS PAGE AND EVERY OTHER PAGE YOU SUBMIT
DO NOT WRITE YOUR NAME OR KAUST ID NUMBER ON THIS PAGE OR ANY OTHER PAGE PUT YOUR EXAM ID NUMBER ON THIS PAGE AND EVERY OTHER PAGE YOU SUBMIT WRITE YOUR SOLUTIONS ON ONLY ONE SIDE OF EMPTY SOLUTION SHEETS
More informationReview of Semiconductor Fundamentals
ECE 541/ME 541 Microelectronic Fabrication Techniques Review of Semiconductor Fundamentals Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Page 1 Semiconductor A semiconductor is an almost insulating material,
More informationFilm Deposition Part 1
1 Film Deposition Part 1 Chapter 11 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Spring Semester 2013 Saroj Kumar Patra Semidonductor Manufacturing Technology, Norwegian University of
More information4FNJDPOEVDUPS 'BCSJDBUJPO &UDI
2010.5.4 1 Major Fabrication Steps in CMOS Process Flow UV light oxygen Silicon dioxide Silicon substrate Oxidation (Field oxide) photoresist Photoresist Coating Mask exposed photoresist Mask-Wafer Exposed
More informationMake sure the exam paper has 8 pages plus an appendix page at the end.
UNIVERSITY OF CALIFORNIA College of Engineering Deartment of Electrical Engineering and Comuter Sciences Fall 2000 EE143 Midterm Exam #1 Family Name First name Signature Make sure the exam aer has 8 ages
More informationOxide growth model. Known as the Deal-Grove or linear-parabolic model
Oxide growth model Known as the Deal-Grove or linear-parabolic model Important elements of the model: Gas molecules (oxygen or water) are incident on the surface of the wafer. Molecules diffuse through
More informationXing Sheng, 微纳光电子材料与器件工艺原理. Doping 掺杂. Xing Sheng 盛兴. Department of Electronic Engineering Tsinghua University
微纳光电子材料与器件工艺原理 Doping 掺杂 Xing Sheng 盛兴 Department of Electronic Engineering Tsinghua University xingsheng@tsinghua.edu.cn 1 Semiconductor PN Junctions Xing Sheng, EE@Tsinghua LEDs lasers detectors solar
More informationElectrical Characteristics of MOS Devices
Electrical Characteristics of MOS Devices The MOS Capacitor Voltage components Accumulation, Depletion, Inversion Modes Effect of channel bias and substrate bias Effect of gate oide charges Threshold-voltage
More informationChapter 3 Basics Semiconductor Devices and Processing
Chapter 3 Basics Semiconductor Devices and Processing Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 1 Objectives Identify at least two
More information6.012 Electronic Devices and Circuits
Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless
More informationModelling for Formation of Source/Drain Region by Ion Implantation and Diffusion Process for MOSFET Device
Modelling for Formation of Source/Drain Region by Ion Implantation and Diffusion Process for MOSFET Device 1 Supratim Subhra Das 2 Ria Das 1,2 Assistant Professor, Mallabhum Institute of Technology, Bankura,
More informationEECS143 Microfabrication Technology
EECS143 Microfabrication Technology Professor Ali Javey Introduction to Materials Lecture 1 Evolution of Devices Yesterday s Transistor (1947) Today s Transistor (2006) Why Semiconductors? Conductors e.g
More informationWet and Dry Etching. Theory
Wet and Dry Etching Theory 1. Introduction Etching techniques are commonly used in the fabrication processes of semiconductor devices to remove selected layers for the purposes of pattern transfer, wafer
More informationSection 6: Ion Implantation. Jaeger Chapter 5
Section 6: Ion Imlantation Jaeger Chater 5 Ion Imlantation - Overview Wafer is Target in High Energy Accelerator Imurities Shot into Wafer Preferred Method of Adding Imurities to Wafers Wide Range of Imurity
More informationSection 3: Etching. Jaeger Chapter 2 Reader
Section 3: Etching Jaeger Chapter 2 Reader Etch rate Etch Process - Figures of Merit Etch rate uniformity Selectivity Anisotropy d m Bias and anisotropy etching mask h f substrate d f d m substrate d f
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationEECS C245 ME C218 Midterm Exam
University of California at Berkeley College of Engineering EECS C245 ME C218 Midterm Eam Fall 2003 Prof. Roger T. Howe October 15, 2003 Dr. Thara Srinivasan Guidelines Your name: SOLUTIONS Circle your
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 8/30/2007 Semiconductor Fundamentals Lecture 2 Read: Chapters 1 and 2 Last Lecture: Energy Band Diagram Conduction band E c E g Band gap E v Valence
More informationLecture 0: Introduction
Lecture 0: Introduction Introduction q Integrated circuits: many transistors on one chip q Very Large Scale Integration (VLSI): bucketloads! q Complementary Metal Oxide Semiconductor Fast, cheap, low power
More informationIntroduction to Photolithography
http://www.ichaus.de/news/72 Introduction to Photolithography Photolithography The following slides present an outline of the process by which integrated circuits are made, of which photolithography is
More informationEE 212 FALL ION IMPLANTATION - Chapter 8 Basic Concepts
EE 212 FALL 1999-00 ION IMPLANTATION - Chapter 8 Basic Concepts Ion implantation is the dominant method of doping used today. In spite of creating enormous lattice damage it is favored because: Large range
More informationDopant Diffusion. (1) Predeposition dopant gas. (2) Drive-in Turn off dopant gas. dose control. Doped Si region
Dopant Diffusion (1) Predeposition dopant gas dose control SiO Si SiO Doped Si region () Drive-in Turn off dopant gas or seal surface with oxide profile control (junction depth; concentration) SiO SiO
More informationFinal Examination EE 130 December 16, 1997 Time allotted: 180 minutes
Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2
More informationSeptember 21, 2005, Wednesday
, Wednesday Doping and diffusion I Faster MOSFET requires shorter channel P + Poly Al Al Motivation Requires shallower source, drain Al P + Poly Al source drain Shorter channel length; yes, but same source
More informationDiffusion in Extrinsic Silicon
1 Diffusion in Extrinsic Silicon SFR Workshop & Review April 17, 2002 Hughes Silvestri, Ian Sharp, Hartmut Bracht, and Eugene Haller Berkeley, CA 2002 GOAL: Diffusion measurements on P doped Si to complete
More informationChapter 9 Ion Implantation
Chapter 9 Ion Implantation Professor Paul K. Chu Ion Implantation Ion implantation is a low-temperature technique for the introduction of impurities (dopants) into semiconductors and offers more flexibility
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Midterm I
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Fall 2006 Professor Ali Javey Midterm I Name: 1. Closed book. One sheet of notes is allowed.
More informationA semiconductor is an almost insulating material, in which by contamination (doping) positive or negative charge carriers can be introduced.
Semiconductor A semiconductor is an almost insulating material, in which by contamination (doping) positive or negative charge carriers can be introduced. Page 2 Semiconductor materials Page 3 Energy levels
More informationMATHEMATICS OF DOPING PROFILES. C(x,t) t. = D 2 C(x,t) x 2. 4Dt dx '
EE43 MATHEMATICS OF DOPING PROFILES N. Cheung The diffusion equation with constant D : has the general solution: C(x,t) = C(x,t) = D 2 C(x,t) 4πDt F(x ' ) e -(x-x' ) 2 4Dt dx ' - where F(x') is the C(x,t)
More informationEtching Issues - Anisotropy. Dry Etching. Dry Etching Overview. Etching Issues - Selectivity
Etching Issues - Anisotropy Dry Etching Dr. Bruce K. Gale Fundamentals of Micromachining BIOEN 6421 EL EN 5221 and 6221 ME EN 5960 and 6960 Isotropic etchants etch at the same rate in every direction mask
More informationDiffusion in Extrinsic Silicon and Silicon Germanium
1 Diffusion in Extrinsic Silicon and Silicon Germanium SFR Workshop & Review November 14, 2002 Hughes Silvestri, Ian Sharp, Hartmut Bracht, and Eugene Haller Berkeley, CA 2002 GOAL: Diffusion measurements
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon
More informationChanging the Dopant Concentration. Diffusion Doping Ion Implantation
Changing the Dopant Concentration Diffusion Doping Ion Implantation Step 11 The photoresist is removed with solvent leaving a ridge of polysilicon (the transistor's gate), which rises above the silicon
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Oldham Fall 1999
UNIVERSITY OF CLIFORNI College of Engineering Department of Electrical Engineering and Computer Sciences Professor Oldham Fall 1999 EECS 40 FINL EXM 13 December 1999 Name: Last, First Student ID: T: Kusuma
More informationThin Film Deposition. Reading Assignments: Plummer, Chap 9.1~9.4
Thin Film Deposition Reading Assignments: Plummer, Chap 9.1~9.4 Thermally grown Deposition Thin Film Formation Thermally grown SiO 2 Deposition SiO 2 Oxygen is from gas phase Silicon from substrate Oxide
More informationEE C247B / ME C218 INTRODUCTION TO MEMS DESIGN SPRING 2016 C. NGUYEN PROBLEM SET #4
Issued: Wednesday, March 4, 2016 PROBLEM SET #4 Due: Monday, March 14, 2016, 8:00 a.m. in the EE C247B homework box near 125 Cory. 1. This problem considers bending of a simple cantilever and several methods
More informationION IMPLANTATION - Chapter 8 Basic Concepts
ION IMPLANTATION - Chapter 8 Basic Concepts Ion implantation is the dominant method of doping used today. In spite of creating enormous lattice damage it is favored because: Large range of doses - 1 11
More informationLecture 15 Etching. Chapters 15 & 16 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/76
Lecture 15 Etching Chapters 15 & 16 Wolf and Tauber 1/76 Announcements Term Paper: You are expected to produce a 4-5 page term paper on a selected topic (from a list). Term paper contributes 25% of course
More information3.15 Electrical, Optical, and Magnetic Materials and Devices Caroline A. Ross Fall Term, 2005
3.15 Electrical, Optical, and Magnetic Materials and Devices Caroline A. Ross Fall Term, 2005 Exam 2 (5 pages) Closed book exam. Formulae and data are on the last 3.5 pages of the exam. This takes 80 min
More informationLecture 6. Rapid Thermal Processing. Reading: Chapter 6
Lecture 6 Rapid Thermal Processing Reading: Chapter 6 (Chapter 6) Categories: Rapid Thermal Anneal (RTA) Rapid Thermal Oxidation (RTO) Rapid Thermal Nitridation (RTN) (and oxynitrides) Rapid Thermal Diffusion
More informationChapter 2. The Well. Cross Sections Patterning Design Rules Resistance PN Junction Diffusion Capacitance. Baker Ch. 2 The Well. Introduction to VLSI
Chapter 2 The Well Cross Sections Patterning Design Rules Resistance PN Junction Diffusion Capacitance Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor
More informationIntroduction to Semiconductor Physics. Prof.P. Ravindran, Department of Physics, Central University of Tamil Nadu, India
Introduction to Semiconductor Physics 1 Prof.P. Ravindran, Department of Physics, Central University of Tamil Nadu, India http://folk.uio.no/ravi/cmp2013 Review of Semiconductor Physics Semiconductor fundamentals
More informationFeature-level Compensation & Control. Process Integration September 15, A UC Discovery Project
Feature-level Compensation & Control Process Integration September 15, 2005 A UC Discovery Project Current Milestones Si/Ge-on-insulator and Strained Si-on-insulator Substrate Engineering (M28 YII.13)
More informationMICROCHIP MANUFACTURING by S. Wolf
by S. Wolf Chapter 15 ALUMINUM THIN-FILMS and SPUTTER-DEPOSITION 2004 by LATTICE PRESS CHAPTER 15 - CONTENTS Aluminum Thin-Films Sputter-Deposition Process Steps Physics of Sputter-Deposition Magnetron-Sputtering
More informationLecture 6 Plasmas. Chapters 10 &16 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/68
Lecture 6 Plasmas Chapters 10 &16 Wolf and Tauber 1/68 Announcements Homework: Homework will be returned to you on Thursday (12 th October). Solutions will be also posted online on Thursday (12 th October)
More information1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00
1 Name: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND Final Exam Physics 3000 December 11, 2012 Fall 2012 9:00-11:00 INSTRUCTIONS: 1. Answer all seven (7) questions.
More informationMSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University
MSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University Practice Final Exam 1 Read the questions carefully Label all figures
More informationCHAPTER 6: Etching. Chapter 6 1
Chapter 6 1 CHAPTER 6: Etching Different etching processes are selected depending upon the particular material to be removed. As shown in Figure 6.1, wet chemical processes result in isotropic etching
More informationEE143 Microfabrication Technology Spring 2011 Prof. J. Bokor. Final Exam
-- EE143 Microfabrication Technology Spring 2011 Prof. J. Bokor Final Exam Name: ---------------------------- Signature: ------------------------------------- SID: ----------------------- CLOSED BOOK.
More informationExtensive reading materials on reserve, including
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationDiffusion and Ion implantation Reference: Chapter 4 Jaeger or Chapter 3 Ruska N & P Dopants determine the resistivity of material Note N lower
Diffusion and Ion implantation Reference: Chapter 4 Jaeger or Chapter 3 Ruska N & P Dopants determine the resistivity of material Note N lower resistavity than p: due to higher carrier mobility Near linear
More informationThermal Oxidation of Si
Thermal Oxidation of General Properties of O 2 Applications of thermal O 2 Deal-Grove Model of Oxidation Thermal O 2 is amorphous. Weight Density = 2.20 gm/cm 3 Molecular Density = 2.3E22 molecules/cm
More informationSolutions for Assignment-6
Solutions for Assignment-6 Q1. What is the aim of thin film deposition? [1] (a) To maintain surface uniformity (b) To reduce the amount (or mass) of light absorbing materials (c) To decrease the weight
More informationP. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions
P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the
More informationSecondary ion mass spectrometry (SIMS)
Secondary ion mass spectrometry (SIMS) ELEC-L3211 Postgraduate Course in Micro and Nanosciences Department of Micro and Nanosciences Personal motivation and experience on SIMS Offers the possibility to
More informationDopant Diffusion Sources
Dopant Diffusion (1) Predeposition dopant gas dose control SiO Si SiO Doped Si region () Drive-in Turn off dopant gas or seal surface with oide profile control (junction depth; concentration) SiO SiO Si
More informationSemiconductors Reference: Chapter 4 Jaeger or Chapter 3 Ruska Recall what determines conductor, insulator and semiconductor Plot the electron energy
Semiconductors Reference: Chapter 4 Jaeger or Chapter 3 Ruska Recall what determines conductor, insulator and semiconductor Plot the electron energy states of a material In some materials get the creation
More informationSpring Semester 2012 Final Exam
Spring Semester 2012 Final Exam Note: Show your work, underline results, and always show units. Official exam time: 2.0 hours; an extension of at least 1.0 hour will be granted to anyone. Materials parameters
More informationUNIT 3. By: Ajay Kumar Gautam Asst. Prof. Dev Bhoomi Institute of Technology & Engineering, Dehradun
UNIT 3 By: Ajay Kumar Gautam Asst. Prof. Dev Bhoomi Institute of Technology & Engineering, Dehradun 1 Syllabus Lithography: photolithography and pattern transfer, Optical and non optical lithography, electron,
More informationCHAPTER 3: Epitaxy. City University of Hong Kong
1 CHAPTER 3: Epitaxy Epitaxy (epi means "upon" and taxis means "ordered") is a term applied to processes used to grow a thin crystalline layer on a crystalline substrate. The seed crystal in epitaxial
More informationESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec 6: September 18, 2017 MOS Model You are Here: Transistor Edition! Previously: simple models (0 and 1 st order) " Comfortable
More informationECE 305 Exam 3: Spring 2015 March 6, 2015 Mark Lundstrom Purdue University
NAME: PUID: : ECE 305 Exam 3: March 6, 2015 Mark Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula sheet at the end of this exam Following the ECE policy,
More informationSemiconductor Physics Problems 2015
Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible
More informationEE 143 MICROFABRICATION TECHNOLOGY FALL 2014 C. Nguyen PROBLEM SET #7. Due: Friday, Oct. 24, 2014, 8:00 a.m. in the EE 143 homework box near 140 Cory
Issued: Tuesday, Oct. 14, 2014 PROBLEM SET #7 Due: Friday, Oct. 24, 2014, 8:00 a.m. in the EE 143 homework box near 140 Cory Electroplating 1. Suppose you want to fabricate MEMS clamped-clamped beam structures
More informationChapter 3 Engineering Science for Microsystems Design and Fabrication
Lectures on MEMS and MICROSYSTEMS DESIGN and MANUFACTURE Chapter 3 Engineering Science for Microsystems Design and Fabrication In this Chapter, we will present overviews of the principles of physical and
More informationEvaluation of plasma strip induced substrate damage Keping Han 1, S. Luo 1, O. Escorcia 1, Carlo Waldfried 1 and Ivan Berry 1, a
Solid State Phenomena Vols. 14-146 (29) pp 249-22 Online available since 29/Jan/6 at www.scientific.net (29) Trans Tech Publications, Switzerland doi:.428/www.scientific.net/ssp.14-146.249 Evaluation of
More informationThe Intrinsic Silicon
The Intrinsic ilicon Thermally generated electrons and holes Carrier concentration p i =n i ni=1.45x10 10 cm-3 @ room temp Generally: n i = 3.1X10 16 T 3/2 e -1.21/2KT cm -3 T= temperature in K o (egrees
More informationSection 5: Thin Film Deposition part 1 : sputtering and evaporation. Jaeger Chapter 6. EE143 Ali Javey
Section 5: Thin Film Deposition part 1 : sputtering and evaporation Jaeger Chapter 6 Vacuum Basics 1. Units 1 atmosphere = 760 torr = 1.013x10 5 Pa 1 bar = 10 5 Pa = 750 torr 1 torr = 1 mm Hg 1 mtorr =
More information