Patterning Challenges and Opportunities: Etch and Film

Size: px
Start display at page:

Download "Patterning Challenges and Opportunities: Etch and Film"

Transcription

1 Patterning Challenges and Opportunities: Etch and Film Ying Zhang, Shahid Rauf, Ajay Ahatnagar, David Chu, Amulya Athayde, and Terry Y. Lee Applied Materials, Inc. SEMICON, Taiwan 2016 Sept , 2016, Taipei, Taiwan

2 2 Outline Advanced nodes pose challenges for patterning These challenges demand new film and etch/removal capabilities Atomic Level Deposition Atomic Level Etch and Removal Low electron temperature plasma etch Highly selective radical based removal Closing remarks

3 Advanced nodes pose challenges for patterning

4 4 Patterning Technology Trend Lithography Technology Materials Engineering Lithography Technology 248nm 193nm 193i Litho multiple exposure EUV Complementary Litho e.g., 193i + EUV Key challenge: Overlay EPE Materials Engineering Etch Film ALD Gapfill Selective removal ALE Selective deposition/growth Key advantage: Enable self-align schemes Atomic Level Controllability

5 5 SAxP Flows In SAxP pitch splitting flows 1 litho step + many non-litho steps (film, etch, etc.) e.g.: SAQP: Litho Etch ALD Etch ALD Etch

6 6 CD/CDU/LER/LWR dominated by Litho, Etch and ALD In SAQP, there are 8 edges : Direct edge: = f (Litho CD/CDU/LER/LWR) S1 edge: = f (Litho and 1 st spacer CD/CDU/LER/LWR) S2 edge: = f (1 st and 2 nd spacer CD/CDU/LER/LWR) S1/S2 edge: = f (1 st, 1 st spacer and 2 nd spacer CD/CDU/LER/LWR) Source: Schenker, Intel SPIE 2016 To systematically reduce EPE: CD/CDU/LER/LWR of all edges at all steps need to be measured to trace down root causes Litho the key source of LER Etch/ALD the key for pitch walking

7 These challenges demand new film and etch/removal capabilities - ALD

8 8 Conventional ALD vs. Olympia TM Reconfigures ALD What is ALD? Conventional ALD Olympia TM ALD Divides CVD into two half-reactions Precursor Precursor Is self-limiting, producing uniform, conformal deposition A B A B Wafer is stationary A B On Off On Off A B Alternating chemistries Purge separates chemistries Primary technology used today Wafer travels continuously Spatially separated chemistries Chemistry-free zones isolate individual chemistries

9 Modular Design for Atomic-Level Engineering Precursor Precursor Treatment X ALD Mode Process Sequence Conventional ALD Thermal Plasma Enhanced A A B B p 20nm Titanium Nitride 20n m Silicon Nitride 20nm Titanium Oxide 20n m Silicon Oxide 100nm Aluminum Oxide Olympia TM ALD Atomic- Layer Treatment Versatility Broadens Spectrum of Achievable ALD Materials without Compromising Productivity A B X Source: Applied Materials, Inc. 9

10 These challenges demand new film and etch/removal capabilities - Etch

11 11 RIE Plasma etching patterning trend Mainstream plasma technologies Variety of CCP Variety of ICP ECR DSP/RP Add-on s Variety of RF pulsing technologies Mainstream plasma technologies Variety of CCP Variety of ICP ECR DSP/RP Add-on s Variety of RF pulsing technologies Thin Layer Etching (TLE) Atomic Layer Etching (ALE) Complex pulsing technologies Advanced radical etching Low T e plasmas Neutral beam

12 12 Basic Mechanisms of Reactive Ion Etching Ion-neutral reaction synergism One of the most important concepts of plasma-surface chemistry is the synergism of ion and neutral reactions Three key aspects of ion bombardment: Stimulate surface reactions Stimulate desorption or clear the surface of etch-inhibiting, nonvolatile residues Anisotropic or directional etching Ion Bombardment effects in Reactive Ion Etching Coburn and Winters, J. of App. Phys , 1979

13 SICLthick (A) 13 Low electron temperature, T e, plasmas Intuitively, lower T e lower V p lower ion energy lower damage ALE(?) How to control low ion energy, e.g., from <4eV to ~25eV? eV 10eV 25eV 50eV 100eV Radical Cl + Cl + Radical Cl + 25eV Cl + ~4 layers Radical Cl + 5eV Cl + ~1-2 layers Cl+ Fluence (ML) From Oliver Joubert, CNRS-LTM

14 14 Low T e Plasma Etch System A low T e plasma is produced in the processing chamber using energetic beam electrons in the kev energy range. A separate inductively coupled plasma (ICP) based radical source is used in our system to provide accurate control over relative concentrations of radicals and ions Another important element in this plasma processing system is low frequency RF bias capability which allows control of ion energy in the 2 50 ev range Radical source e-beam source x Bias (wafer voltage)

15 15 Cross-section (Å 2 ) f e (au) Ion / Radical Composition: RF and Low T e Plasmas In an RF plasma (with T e = 4.0 ev), significantly more electrons can dissociate than ionize due to lower threshold for dissociation. In a low T e plasma produced using energetic electrons, radical / ion fraction is much lower. 6 Cl f T e = 4.0 ev Ebeam s ion 0.8 f T e = 0.2 ev s diss Energy (ev) 0.0

16 Low T e Plasma can etch Si layer-layer with minimal damage The top surface can be more quantitatively analyzed using electron energy loss spectroscopy (EELS). The thickness of the amorphous layer at the top is similar for the unprocessed sample and the sample which has been etched in the low T e plasma only. When RF bias is applied to increase E i, the amorphous layer thickness increases. The sample that was etched in the inductively coupled plasma without bias shows similar damage to the 0.8 W etch case.

17 These challenges demand new film and etch/removal capabilities Selective Removal

18 18 What is Extreme Selectivity? Multiple Material Layers are Formed in a Structure Extreme Selectivity Enables Removal of Only One Material No Damage or Residues Remaining Selectra TM Removes Target Material without Damage to Others Critical for Patterning and 3D Architectures

19 19 Collapse Percentage (%) New Etch Methods Required to Continue Scaling Traditional Wet Etch Collapse of high aspect ratio structures Inability to penetrate small dimensions Traditional Dry Etch Lacks extreme selectivity Insufficient lateral etch control Overetch at Top Internal Image Incomplete Removal 0 Graph Courtesy of imec Aspect Ratio Pattern Collapse Internal Image Tight Features Internal Image Lateral Control Traditional Etch Technologies Unable to Advance Moore s Law Insufficie nt at Bottom

20 20 How Does Selectra TM Achieve Extreme Selectivity? Plasma creates etchant chemistry Ions are blocked, chemistry passes through Damage-free, extreme selectivity etch without polymers The Selectra TM System Creates Tailored Chemistry for Extreme Selectivity

21 21 Extreme Selectivity Enables 10nm Multi-Patterning Pre- Selectra TM 9.3n m Si Ox SiN Ox Internal Image Post- Selectra TM Ox SiN 9.3n m No change in spacer width Ox Internal Image

22 Etch Amount (Å) Atomic-Level Precision Enables 10nm FinFET Pre-Selectra TM Post-Selectra TM Pre-Selectra TM Post-Selectra TM Ox Ox α-si 10 8 Si Internal Image Si Internal Image TiN Ox Ox TiN 6 0 Applied Materials Internal Structures Silicon etch of two atomic layers Selectra TM Enables Fin Scaling and Penetration of Atomic-Level Structures Si Internal Image Si Internal Image Can access spaces <5 silicon atoms across

23 23 Lateral Etch Uniformity Enables 3D NAND Pre Etch Traditional Etch Selectra TM Etch Selectra TM Etch Creates Consistent Contact Resistance

24 24 Closing Remark Advanced nodes pose challenges for patterning Patterning trend: Litho dominating Litho/Materials engineering dominating Recent EUV emerging will help Litho, e.g., complementary litho, but not likely change this trend These challenges demand new film and etch/removal capabilities CD/CDU/LER/LWR play increasingly critical role in scaling Etch/Removal and Film play increasingly critical role in EPE reduction More opportunities for Film and Etch/Removal but key challenges are to have atomic level precision Atomic Layer Deposition Atomic Layer Etch and Removal Low electron temperature plasma etch Highly selective radical based removal

ETCHING Chapter 10. Mask. Photoresist

ETCHING Chapter 10. Mask. Photoresist ETCHING Chapter 10 Mask Light Deposited Substrate Photoresist Etch mask deposition Photoresist application Exposure Development Etching Resist removal Etching of thin films and sometimes the silicon substrate

More information

4FNJDPOEVDUPS 'BCSJDBUJPO &UDI

4FNJDPOEVDUPS 'BCSJDBUJPO &UDI 2010.5.4 1 Major Fabrication Steps in CMOS Process Flow UV light oxygen Silicon dioxide Silicon substrate Oxidation (Field oxide) photoresist Photoresist Coating Mask exposed photoresist Mask-Wafer Exposed

More information

Plasma Etching: Atomic Scale Surface Fidelity and 2D Materials

Plasma Etching: Atomic Scale Surface Fidelity and 2D Materials 1 Plasma Etching: Atomic Scale Surface Fidelity and 2D Materials Thorsten Lill, Keren J. Kanarik, Samantha Tan, Meihua Shen, Alex Yoon, Eric Hudson, Yang Pan, Jeffrey Marks, Vahid Vahedi, Richard A. Gottscho

More information

Etching: Basic Terminology

Etching: Basic Terminology Lecture 7 Etching Etching: Basic Terminology Introduction : Etching of thin films and sometimes the silicon substrate are very common process steps. Usually selectivity, and directionality are the first

More information

Reactive Ion Etching (RIE)

Reactive Ion Etching (RIE) Reactive Ion Etching (RIE) RF 13.56 ~ MHz plasma Parallel-Plate Reactor wafers Sputtering Plasma generates (1) Ions (2) Activated neutrals Enhance chemical reaction 1 2 Remote Plasma Reactors Plasma Sources

More information

Selective Processes: Challenges and Opportunities in Semiconductor Scaling

Selective Processes: Challenges and Opportunities in Semiconductor Scaling Selective Processes: Challenges and Opportunities in Semiconductor Scaling June 4, 2018 Kandabara Tapily TEL Technology Center, America, LLC IITC 2018 Selective Deposition Workshop K. Tapily/ IITC 2018

More information

Section 3: Etching. Jaeger Chapter 2 Reader

Section 3: Etching. Jaeger Chapter 2 Reader Section 3: Etching Jaeger Chapter 2 Reader Etch rate Etch Process - Figures of Merit Etch rate uniformity Selectivity Anisotropy d m Bias and anisotropy etching mask h f substrate d f d m substrate d f

More information

UNIT 3. By: Ajay Kumar Gautam Asst. Prof. Dev Bhoomi Institute of Technology & Engineering, Dehradun

UNIT 3. By: Ajay Kumar Gautam Asst. Prof. Dev Bhoomi Institute of Technology & Engineering, Dehradun UNIT 3 By: Ajay Kumar Gautam Asst. Prof. Dev Bhoomi Institute of Technology & Engineering, Dehradun 1 Syllabus Lithography: photolithography and pattern transfer, Optical and non optical lithography, electron,

More information

Device Fabrication: Etch

Device Fabrication: Etch Device Fabrication: Etch 1 Objectives Upon finishing this course, you should able to: Familiar with etch terminology Compare wet and dry etch processes processing and list the main dry etch etchants Become

More information

Procédés de dépôt plasma avec injection pulsée de précurseurs (PECVD et PEALD) :

Procédés de dépôt plasma avec injection pulsée de précurseurs (PECVD et PEALD) : Procédés de dépôt plasma avec injection pulsée de précurseurs (PECVD et PEALD) : Impact du réacteur et de la pression et développement de dépôts sélectifs C. Vallée 1,3, R. Gassilloud 2, R. Vallat 1,2,

More information

Wet and Dry Etching. Theory

Wet and Dry Etching. Theory Wet and Dry Etching Theory 1. Introduction Etching techniques are commonly used in the fabrication processes of semiconductor devices to remove selected layers for the purposes of pattern transfer, wafer

More information

Etching Issues - Anisotropy. Dry Etching. Dry Etching Overview. Etching Issues - Selectivity

Etching Issues - Anisotropy. Dry Etching. Dry Etching Overview. Etching Issues - Selectivity Etching Issues - Anisotropy Dry Etching Dr. Bruce K. Gale Fundamentals of Micromachining BIOEN 6421 EL EN 5221 and 6221 ME EN 5960 and 6960 Isotropic etchants etch at the same rate in every direction mask

More information

CHAPTER 6: Etching. Chapter 6 1

CHAPTER 6: Etching. Chapter 6 1 Chapter 6 1 CHAPTER 6: Etching Different etching processes are selected depending upon the particular material to be removed. As shown in Figure 6.1, wet chemical processes result in isotropic etching

More information

CVD: General considerations.

CVD: General considerations. CVD: General considerations. PVD: Move material from bulk to thin film form. Limited primarily to metals or simple materials. Limited by thermal stability/vapor pressure considerations. Typically requires

More information

Lecture 6 Plasmas. Chapters 10 &16 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/68

Lecture 6 Plasmas. Chapters 10 &16 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/68 Lecture 6 Plasmas Chapters 10 &16 Wolf and Tauber 1/68 Announcements Homework: Homework will be returned to you on Thursday (12 th October). Solutions will be also posted online on Thursday (12 th October)

More information

EE-612: Lecture 22: CMOS Process Steps

EE-612: Lecture 22: CMOS Process Steps EE-612: Lecture 22: CMOS Process Steps Mark Lundstrom Electrical and Computer Engineering Purdue University West Lafayette, IN USA Fall 2006 NCN www.nanohub.org Lundstrom EE-612 F06 1 outline 1) Unit Process

More information

3.155J/6.152J Microelectronic Processing Technology Fall Term, 2004

3.155J/6.152J Microelectronic Processing Technology Fall Term, 2004 3.155J/6.152J Microelectronic Processing Technology Fall Term, 2004 Bob O'Handley Martin Schmidt Quiz Nov. 17, 2004 Ion implantation, diffusion [15] 1. a) Two identical p-type Si wafers (N a = 10 17 cm

More information

FLCC Seminar. Spacer Lithography for Reduced Variability in MOSFET Performance

FLCC Seminar. Spacer Lithography for Reduced Variability in MOSFET Performance 1 Seminar Spacer Lithography for Reduced Variability in MOSFET Performance Prof. Tsu-Jae King Liu Electrical Engineering & Computer Sciences Dept. University of California at Berkeley Graduate Student:

More information

E SC 412 Nanotechnology: Materials, Infrastructure, and Safety Wook Jun Nam

E SC 412 Nanotechnology: Materials, Infrastructure, and Safety Wook Jun Nam E SC 412 Nanotechnology: Materials, Infrastructure, and Safety Wook Jun Nam Lecture 10 Outline 1. Wet Etching/Vapor Phase Etching 2. Dry Etching DC/RF Plasma Plasma Reactors Materials/Gases Etching Parameters

More information

LECTURE 5 SUMMARY OF KEY IDEAS

LECTURE 5 SUMMARY OF KEY IDEAS LECTURE 5 SUMMARY OF KEY IDEAS Etching is a processing step following lithography: it transfers a circuit image from the photoresist to materials form which devices are made or to hard masking or sacrificial

More information

Figure 1: Graphene release, transfer and stacking processes. The graphene stacking began with CVD

Figure 1: Graphene release, transfer and stacking processes. The graphene stacking began with CVD Supplementary figure 1 Graphene Growth and Transfer Graphene PMMA FeCl 3 DI water Copper foil CVD growth Back side etch PMMA coating Copper etch in 0.25M FeCl 3 DI water rinse 1 st transfer DI water 1:10

More information

Fabrication Technology, Part I

Fabrication Technology, Part I EEL5225: Principles of MEMS Transducers (Fall 2004) Fabrication Technology, Part I Agenda: Microfabrication Overview Basic semiconductor devices Materials Key processes Oxidation Thin-film Deposition Reading:

More information

Chapter 7 Plasma Basic

Chapter 7 Plasma Basic Chapter 7 Plasma Basic Hong Xiao, Ph. D. hxiao89@hotmail.com www2.austin.cc.tx.us/hongxiao/book.htm Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 1 Objectives List at least three IC processes

More information

Normally-Off GaN Field Effect Power Transistors: Device Design and Process Technology Development

Normally-Off GaN Field Effect Power Transistors: Device Design and Process Technology Development Center for High Performance Power Electronics Normally-Off GaN Field Effect Power Transistors: Device Design and Process Technology Development Dr. Wu Lu (614-292-3462, lu.173@osu.edu) Dr. Siddharth Rajan

More information

DOE WEB SEMINAR,

DOE WEB SEMINAR, DOE WEB SEMINAR, 2013.03.29 Electron energy distribution function of the plasma in the presence of both capacitive field and inductive field : from electron heating to plasma processing control 1 mm PR

More information

Lithography Challenges Moore s Law Rising Costs and Challenges of Advanced Patterning

Lithography Challenges Moore s Law Rising Costs and Challenges of Advanced Patterning Lithography Challenges Moore s Law Rising Costs and Challenges of Advanced Patterning SEMI Texas Spring Forum May 21, 2013 Austin, Texas Author / Company / Division / Rev. / Date A smartphone today has

More information

Technology for Micro- and Nanostructures Micro- and Nanotechnology

Technology for Micro- and Nanostructures Micro- and Nanotechnology Lecture 10: Deposition Technology for Micro- and Nanostructures Micro- and Nanotechnology Peter Unger mailto: peter.unger @ uni-ulm.de Institute of Optoelectronics University of Ulm http://www.uni-ulm.de/opto

More information

Plasma atomic layer etching using conventional plasma equipment

Plasma atomic layer etching using conventional plasma equipment Plasma atomic layer etching using conventional plasma equipment Ankur Agarwal a Department of Chemical and Biomolecular Engineering, University of Illinois, 600 S. Mathews Ave., Urbana, Illinois 61801

More information

Plasma etching. Bibliography

Plasma etching. Bibliography Plasma etching Bibliography 1. B. Chapman, Glow discharge processes, (Wiley, New York, 1980). - Classical plasma processing of etching and sputtering 2. D. M. Manos and D. L. Flamm, Plasma etching; An

More information

PIC-MCC/Fluid Hybrid Model for Low Pressure Capacitively Coupled O 2 Plasma

PIC-MCC/Fluid Hybrid Model for Low Pressure Capacitively Coupled O 2 Plasma PIC-MCC/Fluid Hybrid Model for Low Pressure Capacitively Coupled O 2 Plasma Kallol Bera a, Shahid Rauf a and Ken Collins a a Applied Materials, Inc. 974 E. Arques Ave., M/S 81517, Sunnyvale, CA 9485, USA

More information

EE 527 MICROFABRICATION. Lecture 25 Tai-Chang Chen University of Washington

EE 527 MICROFABRICATION. Lecture 25 Tai-Chang Chen University of Washington EE 527 MICROFABRICATION Lecture 25 Tai-Chang Chen University of Washington ION MILLING SYSTEM Kaufmann source Use e-beam to strike plasma A magnetic field applied to increase ion density Drawback Low etch

More information

Chapter 7. Plasma Basics

Chapter 7. Plasma Basics Chapter 7 Plasma Basics 2006/4/12 1 Objectives List at least three IC processes using plasma Name three important collisions in plasma Describe mean free path Explain how plasma enhance etch and CVD processes

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Fall Exam 1

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Fall Exam 1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 143 Fall 2008 Exam 1 Professor Ali Javey Answer Key Name: SID: 1337 Closed book. One sheet

More information

Plasma Chemistry Study in an Inductively Coupled Dielectric Etcher

Plasma Chemistry Study in an Inductively Coupled Dielectric Etcher Plasma Chemistry Study in an Inductively Coupled Dielectric Etcher Chunshi Cui, John Trow, Ken Collins, Betty Tang, Luke Zhang, Steve Shannon, and Yan Ye Applied Materials, Inc. October 26, 2000 10/28/2008

More information

Plasma etch control by means of physical plasma parameter measurement with HERCULES Sematech AEC/APC Symposium X

Plasma etch control by means of physical plasma parameter measurement with HERCULES Sematech AEC/APC Symposium X Plasma etch control by means of physical plasma parameter measurement with HERCULES A. Steinbach F. Bell D. Knobloch S. Wurm Ch. Koelbl D. Köhler -1- Contents - Introduction - Motivation - Plasma monitoring

More information

Inductively Coupled Plasma Reactive Ion Etching of GeSbTe Thin Films in a HBr/Ar Gas

Inductively Coupled Plasma Reactive Ion Etching of GeSbTe Thin Films in a HBr/Ar Gas Integrated Ferroelectrics, 90: 95 106, 2007 Copyright Taylor & Francis Group, LLC ISSN 1058-4587 print / 1607-8489 online DOI: 10.1080/10584580701249371 Inductively Coupled Plasma Reactive Ion Etching

More information

Lecture 150 Basic IC Processes (10/10/01) Page ECE Analog Integrated Circuits and Systems P.E. Allen

Lecture 150 Basic IC Processes (10/10/01) Page ECE Analog Integrated Circuits and Systems P.E. Allen Lecture 150 Basic IC Processes (10/10/01) Page 1501 LECTURE 150 BASIC IC PROCESSES (READING: TextSec. 2.2) INTRODUCTION Objective The objective of this presentation is: 1.) Introduce the fabrication of

More information

PIC-MCC/Fluid Hybrid Model for Low Pressure Capacitively Coupled O 2 Plasma

PIC-MCC/Fluid Hybrid Model for Low Pressure Capacitively Coupled O 2 Plasma PIC-MCC/Fluid Hybrid Model for Low Pressure Capacitively Coupled O 2 Plasma Kallol Bera a, Shahid Rauf a and Ken Collins a a Applied Materials, Inc. 974 E. Arques Ave., M/S 81517, Sunnyvale, CA 9485, USA

More information

Dry Etching Zheng Yang ERF 3017, MW 5:15-6:00 pm

Dry Etching Zheng Yang ERF 3017,   MW 5:15-6:00 pm Dry Etching Zheng Yang ERF 3017, email: yangzhen@uic.edu, MW 5:15-6:00 pm Page 1 Page 2 Dry Etching Why dry etching? - WE is limited to pattern sizes above 3mm - WE is isotropic causing underetching -

More information

EE 527 MICROFABRICATION. Lecture 24 Tai-Chang Chen University of Washington

EE 527 MICROFABRICATION. Lecture 24 Tai-Chang Chen University of Washington EE 527 MICROFABRICATION Lecture 24 Tai-Chang Chen University of Washington EDP ETCHING OF SILICON - 1 Ethylene Diamine Pyrocatechol Anisotropy: (100):(111) ~ 35:1 EDP is very corrosive, very carcinogenic,

More information

ALD & ALE Tutorial Speakers and Schedule

ALD & ALE Tutorial Speakers and Schedule ALD & ALE Tutorial Speakers and Schedule Sunday, July 29, 2018 1:00-1:05 Tutorial Welcome 1:05-1:50 1:50-2:35 2:35-3:20 Challenges of ALD Applications in Memory Semiconductor Devices, Choon Hwan Kim (SK

More information

New plasma technologies for atomic scale precision etching

New plasma technologies for atomic scale precision etching New plasma technologies for atomic scale precision etching Erwine Pargon Laboratoire des Technologies de la Microélectronique (LTM/CNRS), Grenoble Journées des réseaux plasma froids 17-20 octobre 2016,

More information

VACUUM TECHNOLOGIES NEEDED FOR 3D DEVICE PROCESSING

VACUUM TECHNOLOGIES NEEDED FOR 3D DEVICE PROCESSING VACUUM TECHNOLOGIES NEEDED FOR 3D DEVICE PROCESSING Future ICs will use more 3D device structures such as finfets and gate-all-around (GAA) transistors, and so vacuum deposition processes are needed that

More information

Supplementary Figure 1 Detailed illustration on the fabrication process of templatestripped

Supplementary Figure 1 Detailed illustration on the fabrication process of templatestripped Supplementary Figure 1 Detailed illustration on the fabrication process of templatestripped gold substrate. (a) Spin coating of hydrogen silsesquioxane (HSQ) resist onto the silicon substrate with a thickness

More information

EE143 Fall 2016 Microfabrication Technologies. Lecture 6: Thin Film Deposition Reading: Jaeger Chapter 6

EE143 Fall 2016 Microfabrication Technologies. Lecture 6: Thin Film Deposition Reading: Jaeger Chapter 6 EE143 Fall 2016 Microfabrication Technologies Lecture 6: Thin Film Deposition Reading: Jaeger Chapter 6 Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 Vacuum Basics Units 1 atmosphere

More information

DEPOSITION AND COMPOSITION OF POLYMER FILMS IN FLUOROCARBON PLASMAS*

DEPOSITION AND COMPOSITION OF POLYMER FILMS IN FLUOROCARBON PLASMAS* DEPOSITION AND COMPOSITION OF POLYMER FILMS IN FLUOROCARBON PLASMAS* Kapil Rajaraman and Mark J. Kushner 1406 W. Green St. Urbana, IL 61801 rajaramn@uiuc.edu mjk@uiuc.edu http://uigelz.ece.uiuc.edu November

More information

Modification of thin films and nanoparticles. Johannes Berndt, GREMI,Orléans

Modification of thin films and nanoparticles. Johannes Berndt, GREMI,Orléans Modification of thin films and nanoparticles Johannes Berndt, GREMI,Orléans Low temperature plasmas not fully ionized Ionization degree 10-6 10-4 far away from thermodynamic equlilibrium T electron >>

More information

Accelerated Neutral Atom Beam (ANAB)

Accelerated Neutral Atom Beam (ANAB) Accelerated Neutral Atom Beam (ANAB) Development and Commercialization July 2015 1 Technological Progression Sometimes it is necessary to develop a completely new tool or enabling technology to meet future

More information

Hotwire-assisted Atomic Layer Deposition of Pure Metals and Metal Nitrides

Hotwire-assisted Atomic Layer Deposition of Pure Metals and Metal Nitrides Hotwire-assisted Atomic Layer Deposition of Pure Metals and Metal Nitrides Alexey Kovalgin MESA+ Institute for Nanotechnology Semiconductor Components group a.y.kovalgin@utwente.nl 1 Motivation 1. Materials

More information

Tilted ion implantation as a cost-efficient sublithographic

Tilted ion implantation as a cost-efficient sublithographic Tilted ion implantation as a cost-efficient sublithographic patterning technique Sang Wan Kim 1,a), Peng Zheng 1, Kimihiko Kato 1, Leonard Rubin 2, Tsu-Jae King Liu 1 1 Department of Electrical Engineering

More information

MODELING OF SEASONING OF REACTORS: EFFECTS OF ION ENERGY DISTRIBUTIONS TO CHAMBER WALLS*

MODELING OF SEASONING OF REACTORS: EFFECTS OF ION ENERGY DISTRIBUTIONS TO CHAMBER WALLS* MODELING OF SEASONING OF REACTORS: EFFECTS OF ION ENERGY DISTRIBUTIONS TO CHAMBER WALLS* Ankur Agarwal a) and Mark J. Kushner b) a) Department of Chemical and Biomolecular Engineering University of Illinois,

More information

Lithography and Etching

Lithography and Etching Lithography and Etching Victor Ovchinnikov Chapters 8.1, 8.4, 9, 11 Previous lecture Microdevices Main processes: Thin film deposition Patterning (lithography) Doping Materials: Single crystal (monocrystal)

More information

Chapter 9, Etch. Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm

Chapter 9, Etch. Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm Chapter 9, Etch Hong Xiao, Ph. D. hxiao89@hotmail.com www2.austin.cc.tx.us/hongxiao/book.htm Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 1 Objectives Upon finishing this course, you should

More information

Plasma Deposition (Overview) Lecture 1

Plasma Deposition (Overview) Lecture 1 Plasma Deposition (Overview) Lecture 1 Material Processes Plasma Processing Plasma-assisted Deposition Implantation Surface Modification Development of Plasma-based processing Microelectronics needs (fabrication

More information

Lecture 15 Etching. Chapters 15 & 16 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/76

Lecture 15 Etching. Chapters 15 & 16 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/76 Lecture 15 Etching Chapters 15 & 16 Wolf and Tauber 1/76 Announcements Term Paper: You are expected to produce a 4-5 page term paper on a selected topic (from a list). Term paper contributes 25% of course

More information

Effects of plasma treatment on the precipitation of fluorine-doped silicon oxide

Effects of plasma treatment on the precipitation of fluorine-doped silicon oxide ARTICLE IN PRESS Journal of Physics and Chemistry of Solids 69 (2008) 555 560 www.elsevier.com/locate/jpcs Effects of plasma treatment on the precipitation of fluorine-doped silicon oxide Jun Wu a,, Ying-Lang

More information

Self-study problems and questions Processing and Device Technology, FFF110/FYSD13

Self-study problems and questions Processing and Device Technology, FFF110/FYSD13 Self-study problems and questions Processing and Device Technology, FFF110/FYSD13 Version 2016_01 In addition to the problems discussed at the seminars and at the lectures, you can use this set of problems

More information

Atomic layer deposition of titanium nitride

Atomic layer deposition of titanium nitride Atomic layer deposition of titanium nitride Jue Yue,version4, 04/26/2015 Introduction Titanium nitride is a hard and metallic material which has found many applications, e.g.as a wear resistant coating[1],

More information

DO NOT WRITE YOUR NAME OR KAUST ID NUMBER ON THIS PAGE OR ANY OTHER PAGE PUT YOUR EXAM ID NUMBER ON THIS PAGE AND EVERY OTHER PAGE YOU SUBMIT

DO NOT WRITE YOUR NAME OR KAUST ID NUMBER ON THIS PAGE OR ANY OTHER PAGE PUT YOUR EXAM ID NUMBER ON THIS PAGE AND EVERY OTHER PAGE YOU SUBMIT DO NOT WRITE YOUR NAME OR KAUST ID NUMBER ON THIS PAGE OR ANY OTHER PAGE PUT YOUR EXAM ID NUMBER ON THIS PAGE AND EVERY OTHER PAGE YOU SUBMIT WRITE YOUR SOLUTIONS ON ONLY ONE SIDE OF EMPTY SOLUTION SHEETS

More information

Nanoimprint Lithography

Nanoimprint Lithography Nanoimprint Lithography Wei Wu Quantum Science Research Advanced Studies HP Labs, Hewlett-Packard Email: wei.wu@hp.com Outline Background Nanoimprint lithography Thermal based UV-based Applications based

More information

Lecture 11. Etching Techniques Reading: Chapter 11. ECE Dr. Alan Doolittle

Lecture 11. Etching Techniques Reading: Chapter 11. ECE Dr. Alan Doolittle Lecture 11 Etching Techniques Reading: Chapter 11 Etching Techniques Characterized by: 1.) Etch rate (A/minute) 2.) Selectivity: S=etch rate material 1 / etch rate material 2 is said to have a selectivity

More information

Modeling of Ion Energy Distribution Using Time-Series Neural Network

Modeling of Ion Energy Distribution Using Time-Series Neural Network 12th SEAS International Conference on SYSTEMS, Heralion, Greece, July 22-24, 2008 Modeling of Ion Energy Distribution Using Time-Series Neural Networ Suyeon Kim, Byungwhan Kim* Department of Electronic

More information

Plasma Processing in the Microelectronics Industry. Bert Ellingboe Plasma Research Laboratory

Plasma Processing in the Microelectronics Industry. Bert Ellingboe Plasma Research Laboratory Plasma Processing in the Microelectronics Industry Bert Ellingboe Plasma Research Laboratory Outline What has changed in the last 12 years? What is the relavant plasma physics? Sheath formation Sheath

More information

High-density data storage: principle

High-density data storage: principle High-density data storage: principle Current approach High density 1 bit = many domains Information storage driven by domain wall shifts 1 bit = 1 magnetic nanoobject Single-domain needed Single easy axis

More information

Modern Methods in Heterogeneous Catalysis Research: Preparation of Model Systems by Physical Methods

Modern Methods in Heterogeneous Catalysis Research: Preparation of Model Systems by Physical Methods Modern Methods in Heterogeneous Catalysis Research: Preparation of Model Systems by Physical Methods Methods for catalyst preparation Methods discussed in this lecture Physical vapour deposition - PLD

More information

EE C245 ME C218 Introduction to MEMS Design

EE C245 ME C218 Introduction to MEMS Design EE C245 ME C218 Introduction to MEMS Design Fall 2008 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 6: Process

More information

Etching Capabilities at Harvard CNS. March 2008

Etching Capabilities at Harvard CNS. March 2008 Etching Capabilities at Harvard CNS March 2008 CNS: A shared use facility for the Harvard Community and New England CNS Provides technical support, equipment and staff. Explicitly multi-disciplinary w/

More information

UHF-ECR Plasma Etching System for Dielectric Films of Next-generation Semiconductor Devices

UHF-ECR Plasma Etching System for Dielectric Films of Next-generation Semiconductor Devices UHF-ECR Plasma Etching System for Dielectric Films of Next-generation Semiconductor Devices 1 UHF-ECR Plasma Etching System for Dielectric Films of Next-generation Semiconductor Devices Katsuya Watanabe

More information

Enhanced High Aspect Ratio Etch Performance With ANAB Technology. Keywords: High Aspect Ratio, Etch, Neutral Particles, Neutral Beam I.

Enhanced High Aspect Ratio Etch Performance With ANAB Technology. Keywords: High Aspect Ratio, Etch, Neutral Particles, Neutral Beam I. Enhanced High Aspect Ratio Etch Performance With ANAB Technology. Keywords: High Aspect Ratio, Etch, Neutral Particles, Neutral Beam I. INTRODUCTION As device density increases according to Moore s law,

More information

Introduction to Photolithography

Introduction to Photolithography http://www.ichaus.de/news/72 Introduction to Photolithography Photolithography The following slides present an outline of the process by which integrated circuits are made, of which photolithography is

More information

Thomas Schwarz-Selinger. Max-Planck-Institut for Plasmaphysics, Garching Material Science Division Reactive Plasma Processes

Thomas Schwarz-Selinger. Max-Planck-Institut for Plasmaphysics, Garching Material Science Division Reactive Plasma Processes Max-Planck-Institut für Plasmaphysik Thomas Schwarz-Selinger Max-Planck-Institut for Plasmaphysics, Garching Material Science Division Reactive Plasma Processes personal research interests / latest work

More information

EE 143 MICROFABRICATION TECHNOLOGY FALL 2014 C. Nguyen PROBLEM SET #7. Due: Friday, Oct. 24, 2014, 8:00 a.m. in the EE 143 homework box near 140 Cory

EE 143 MICROFABRICATION TECHNOLOGY FALL 2014 C. Nguyen PROBLEM SET #7. Due: Friday, Oct. 24, 2014, 8:00 a.m. in the EE 143 homework box near 140 Cory Issued: Tuesday, Oct. 14, 2014 PROBLEM SET #7 Due: Friday, Oct. 24, 2014, 8:00 a.m. in the EE 143 homework box near 140 Cory Electroplating 1. Suppose you want to fabricate MEMS clamped-clamped beam structures

More information

Ion Implant Part 1. Saroj Kumar Patra, TFE4180 Semiconductor Manufacturing Technology. Norwegian University of Science and Technology ( NTNU )

Ion Implant Part 1. Saroj Kumar Patra, TFE4180 Semiconductor Manufacturing Technology. Norwegian University of Science and Technology ( NTNU ) 1 Ion Implant Part 1 Chapter 17: Semiconductor Manufacturing Technology by M. Quirk & J. Serda Spring Semester 2014 Saroj Kumar Patra,, Norwegian University of Science and Technology ( NTNU ) 2 Objectives

More information

Understanding electron energy loss mechanisms in EUV resists using EELS and first-principles calculations

Understanding electron energy loss mechanisms in EUV resists using EELS and first-principles calculations Understanding electron energy loss mechanisms in EUV resists using EELS and first-principles calculations Robert Bartynski Sylvie Rangan Department of Physics & Astronomy and Laboratory for Surface Modification

More information

EE143 LAB. Professor N Cheung, U.C. Berkeley

EE143 LAB. Professor N Cheung, U.C. Berkeley EE143 LAB 1 1 EE143 Equipment in Cory 218 2 Guidelines for Process Integration * A sequence of Additive and Subtractive steps with lateral patterning Processing Steps Si wafer Watch out for materials compatibility

More information

Clean-Room microfabrication techniques. Francesco Rizzi Italian Institute of Technology

Clean-Room microfabrication techniques. Francesco Rizzi Italian Institute of Technology Clean-Room microfabrication techniques Francesco Rizzi Italian Institute of Technology Miniaturization The first transistor Miniaturization The first transistor Miniaturization The first transistor Miniaturization

More information

Top down and bottom up fabrication

Top down and bottom up fabrication Lecture 24 Top down and bottom up fabrication Lithography ( lithos stone / graphein to write) City of words lithograph h (Vito Acconci, 1999) 1930 s lithography press Photolithography d 2( NA) NA=numerical

More information

Numerical Simulation: Effects of Gas Flow and Rf Current Direction on Plasma Uniformity in an ICP Dry Etcher

Numerical Simulation: Effects of Gas Flow and Rf Current Direction on Plasma Uniformity in an ICP Dry Etcher Appl. Sci. Converg. Technol. 26(6): 189-194 (2017) http://dx.doi.org/10.5757/asct.2017.26.6.189 Research Paper Numerical Simulation: Effects of Gas Flow and Rf Current Direction on Plasma Uniformity in

More information

ABSTRACT COMPARISON OF ADVANCED RESIST ETCHING IN E-BEAM GENERATED PLASMAS

ABSTRACT COMPARISON OF ADVANCED RESIST ETCHING IN E-BEAM GENERATED PLASMAS ABSTRACT Title: COMPARISON OF ADVANCED RESIST ETCHING IN E-BEAM GENERATED PLASMAS Bryan J. Orf, Masters of Science, 2006 Directed By: Professor Gottlieb S. Oehrlein, Department of Material Science and

More information

EE 292L : Nanomanufacturing. Week 5: Advanced Process Technology. Oct

EE 292L : Nanomanufacturing. Week 5: Advanced Process Technology. Oct EE 292L : Nanomanufacturing Week 5: Advanced Process Technology Oct 22 2012 1 Advanced Process Technology 1 HAR etch 2 3 HAR Gapfill Metal ALD 4 Reflow 5 6 SAC Airgap 7 8 Strain Ge/III-V Engineering 1

More information

Evaluation of plasma strip induced substrate damage Keping Han 1, S. Luo 1, O. Escorcia 1, Carlo Waldfried 1 and Ivan Berry 1, a

Evaluation of plasma strip induced substrate damage Keping Han 1, S. Luo 1, O. Escorcia 1, Carlo Waldfried 1 and Ivan Berry 1, a Solid State Phenomena Vols. 14-146 (29) pp 249-22 Online available since 29/Jan/6 at www.scientific.net (29) Trans Tech Publications, Switzerland doi:.428/www.scientific.net/ssp.14-146.249 Evaluation of

More information

Characterization of Post-etch Residue Clean By Chemical Bonding Transformation Mapping

Characterization of Post-etch Residue Clean By Chemical Bonding Transformation Mapping Characterization of Post-etch Residue Clean By Chemical Bonding Transformation Mapping Muthappan Asokan, Oliver Chyan*, Interfacial Electrochemistry and Materials Research Lab, University of North Texas

More information

Chapter 6. Summary and Conclusions

Chapter 6. Summary and Conclusions Chapter 6 Summary and Conclusions Plasma deposited amorphous hydrogenated carbon films (a-c:h) still attract a lot of interest due to their extraordinary properties. Depending on the deposition conditions

More information

Supporting Information for: Sustained sub-60 mv/decade switching via the negative capacitance effect in MoS 2 transistors

Supporting Information for: Sustained sub-60 mv/decade switching via the negative capacitance effect in MoS 2 transistors Supporting Information for: Sustained sub-60 mv/decade switching via the negative capacitance effect in MoS 2 transistors Felicia A. McGuire 1, Yuh-Chen Lin 1, Katherine Price 1, G. Bruce Rayner 2, Sourabh

More information

Gold Nanoparticles Floating Gate MISFET for Non-Volatile Memory Applications

Gold Nanoparticles Floating Gate MISFET for Non-Volatile Memory Applications Gold Nanoparticles Floating Gate MISFET for Non-Volatile Memory Applications D. Tsoukalas, S. Kolliopoulou, P. Dimitrakis, P. Normand Institute of Microelectronics, NCSR Demokritos, Athens, Greece S. Paul,

More information

The Pennsylvania State University. Kurt J. Lesker Company. North Carolina State University. Taiwan Semiconductor Manufacturing Company 1

The Pennsylvania State University. Kurt J. Lesker Company. North Carolina State University. Taiwan Semiconductor Manufacturing Company 1 Enhancement Mode Strained (1.3%) Germanium Quantum Well FinFET (W fin =20nm) with High Mobility (μ Hole =700 cm 2 /Vs), Low EOT (~0.7nm) on Bulk Silicon Substrate A. Agrawal 1, M. Barth 1, G. B. Rayner

More information

EE C245 ME C218 Introduction to MEMS Design Fall 2010

EE C245 ME C218 Introduction to MEMS Design Fall 2010 Lecture Outline EE C245 ME C28 Introduction to MEMS Design Fall 200 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720

More information

Hong Young Chang Department of Physics, Korea Advanced Institute of Science and Technology (KAIST), Republic of Korea

Hong Young Chang Department of Physics, Korea Advanced Institute of Science and Technology (KAIST), Republic of Korea Hong Young Chang Department of Physics, Korea Advanced Institute of Science and Technology (KAIST), Republic of Korea Index 1. Introduction 2. Some plasma sources 3. Related issues 4. Summary -2 Why is

More information

TMT4320 Nanomaterials November 10 th, Thin films by physical/chemical methods (From chapter 24 and 25)

TMT4320 Nanomaterials November 10 th, Thin films by physical/chemical methods (From chapter 24 and 25) 1 TMT4320 Nanomaterials November 10 th, 2015 Thin films by physical/chemical methods (From chapter 24 and 25) 2 Thin films by physical/chemical methods Vapor-phase growth (compared to liquid-phase growth)

More information

Sensors and Metrology. Outline

Sensors and Metrology. Outline Sensors and Metrology A Survey 1 Outline General Issues & the SIA Roadmap Post-Process Sensing (SEM/AFM, placement) In-Process (or potential in-process) Sensors temperature (pyrometry, thermocouples, acoustic

More information

Simulating mechanism at the atomic-scale for atomically precise deposition and etching

Simulating mechanism at the atomic-scale for atomically precise deposition and etching SEMICON TechArena session on Advanced Materials 14 November 2017 Simulating mechanism at the atomic-scale for atomically precise deposition and etching Simon D. Elliott & Ekaterina Filatova simon.elliott@tyndall.ie

More information

INVESTIGATION of Si and SiO 2 ETCH MECHANISMS USING an INTEGRATED SURFACE KINETICS MODEL

INVESTIGATION of Si and SiO 2 ETCH MECHANISMS USING an INTEGRATED SURFACE KINETICS MODEL 46 th AVS International Symposium Oct. 25-29, 1999 Seattle, WA INVESTIGATION of Si and SiO 2 ETCH MECHANISMS USING an INTEGRATED SURFACE KINETICS MODEL Da Zhang* and Mark J. Kushner** *Department of Materials

More information

X-Ray Photoelectron Spectroscopy (XPS) Prof. Paul K. Chu

X-Ray Photoelectron Spectroscopy (XPS) Prof. Paul K. Chu X-Ray Photoelectron Spectroscopy (XPS) Prof. Paul K. Chu X-ray Photoelectron Spectroscopy Introduction Qualitative analysis Quantitative analysis Charging compensation Small area analysis and XPS imaging

More information

MSN551 LITHOGRAPHY II

MSN551 LITHOGRAPHY II MSN551 Introduction to Micro and Nano Fabrication LITHOGRAPHY II E-Beam, Focused Ion Beam and Soft Lithography Why need electron beam lithography? Smaller features are required By electronics industry:

More information

Ion beam lithography

Ion beam lithography Ion beam lithography Progress in ion technology spot size

More information

The Impact of EUV on the Semiconductor Supply Chain. Scotten W. Jones President IC Knowledge LLC

The Impact of EUV on the Semiconductor Supply Chain. Scotten W. Jones President IC Knowledge LLC The Impact of EUV on the Semiconductor Supply Chain Scotten W. Jones President IC Knowledge LLC sjones@icknowledge.com Outline Why EUV Who needs EUV EUV adoption roadmaps EUV wafer volume projections Impact

More information

Evaluating the Performance of c-c 4 F 8, c-c 5 F 8, and C 4 F 6 for Critical Dimension Dielectric Etching

Evaluating the Performance of c-c 4 F 8, c-c 5 F 8, and C 4 F 6 for Critical Dimension Dielectric Etching Evaluating the Performance of c- 4 8, c- 5 8, and 4 6 for ritical Dimension Dielectric Etching B. Ji, P. R. Badowski, S. A, Motika, and E. J. Karwacki, Jr. Introduction: One of the many challenges I manufacturing

More information

A comparison of the defects introduced during plasma exposure in. high- and low-k dielectrics

A comparison of the defects introduced during plasma exposure in. high- and low-k dielectrics A comparison of the defects introduced during plasma exposure in high- and low-k dielectrics H. Ren, 1 G. Jiang, 2 G. A. Antonelli, 2 Y. Nishi, 3 and J.L. Shohet 1 1 Plasma Processing & Technology Laboratory

More information

JOHN G. EKERDT RESEARCH FOCUS

JOHN G. EKERDT RESEARCH FOCUS JOHN G. EKERDT RESEARCH FOCUS We study the surface, growth and materials chemistry of metal, dielectric, ferroelectric, and polymer thin films. We seek to understand and describe nucleation and growth

More information

Robert A. Meger Richard F. Fernster Martin Lampe W. M. Manheimer NOTICE

Robert A. Meger Richard F. Fernster Martin Lampe W. M. Manheimer NOTICE Serial Number Filing Date Inventor 917.963 27 August 1997 Robert A. Meger Richard F. Fernster Martin Lampe W. M. Manheimer NOTICE The above identified patent application is available for licensing. Requests

More information