Feature-level Compensation & Control. Process Integration September 15, A UC Discovery Project

Transcription

1 Feature-level Compensation & Control Process Integration September 15, 2005 A UC Discovery Project

2 Current Milestones Si/Ge-on-insulator and Strained Si-on-insulator Substrate Engineering (M28 YII.13) Increase thermal robustness of GeOI by using nitrogen and ammonia plasma for bonding. Use of pseudo-mosfet structure to evaluate transferred layer electronic properties. Develop a thermal-mechanical model to predict transferred layer thickness and structural stability. Work with industrial sponsors to initiate SOI research. Diffusion of oxygen in germanium (M29 YII.14) Determine the diffusion coefficient for the diffusion of oxygen in germanium, including the temperature dependence and the activation energy of the diffusion. Investigate the effect of an SiO 2 cap on the diffusion of Si in Ge. Initial experiments on interaction of fine patterns with diffusion. Transient enhanced diffusion of B in Ge (Milestone added) Investigate the effect of ion implantation damage on the diffusion of B in Ge. 2 Intermixing of germanium in SOI films (YII.15) Develop a process for selectively forming strained Si 1-x Ge x -in-soi by intermixing Ge & Si 09/15/ Process Integration

3 3 Year 3 Milestones Si/Ge-on-insulator and Strained Si-on-insulator Substrate Engineering (PI Y3.1) Prototype GeOI MOSFET performance evaluation. Demonstrate GeSiOI layer transfer using GeSi epi wafers. Investigate interfacial quality with high-k dielectric as buried insulator. Effect of surface on diffusion in germanium (PI Y3.2) Utilize the test mask for the growth of thermal oxide and thermal nitride on Ge to systematically study the effects of the surface layers on diffusion in Ge. Effect of implantation damage on the diffusion of dopants in Ge (PI Y3.3) Study the effect of ion implantation, in particular, end of range damage on the diffusion of common dopants in Ge. Determine if ion implantation damages have any transient effect on diffusion in Ge. Characterization of Si 1-x Ge x formed with Ge/Si intermixing process (PI Y3.4) Characterize the resistance of boron-doped Si 1-x Ge x -on-insulator formed by the Ge/Si intermixing process. Characterize metal-to-si 1-x Ge x -on-insulator contact resistance and explore ways of lowering this to below 10-8 Ω-cm 2. 09/15/ Process Integration

4 4 Advanced S/D Technology for Thin-Body FETs Pankaj Kalra, Prof. Tsu-Jae King University of California, Berkeley XTEM of UTB MOSFET w/ raised Ge S/D Si 1-x Ge x Source Gate SOI Si 1-x Ge x Drain Gate Ge Source Ge Drain SiO 2 Si T Si = 3 nm 09/15/ Process Integration SiO 2 Silicon Substrate

5 5 Year 2 Milestones Develop a process for selectively forming strained Si 1-x Ge x -in-soi by intermixing Ge & Si Future Milestones Characterization of series and contact resistances of boron-doped Si 1-x Ge x -on-insulator layers 09/15/ Process Integration

6 6 UTB MOSFET with SiGe Source/Drain 2-D Stress Distribution Stress Profile vs. L g K. Shin et al., to be published Stress in the channel varies with position increases with decreasing L g & T Si, and with increasing Ge in S/D 09/15/ Process Integration

7 7 Results to Date Intermixed Ge/Si samples have been fabricated Various surface/interface treatments Boron-implanted vs. unimplanted 800 o C vs. 850 o C anneal SiO 2 Ge SiO 2 Ge SiO 2 Ge Silicon Substrate Characterization of Ge profile is underway XTEM with EDX nanoprobe XTEM with EELS 09/15/ Process Integration Collaboration with Prof. Haller s group

8 8 Transient Effects on Boron Diffusion in Germanium Chris Liao, Hughes Silvestri, and Eugene E. Haller University of California at Berkeley and Lawrence Berkeley National Laboratory, Berkeley, CA 09/15/ Process Integration

9 09/15/ Process Integration 9 Motivation New generation electronic devices utilize heterogeneous materials incorporation (e.g., Si/SiGe and Ge) to enhance device performance Due to aggressive scaling, precise dopant and selfdiffusion controls in SiGe and Ge are becoming ever more crucial Advanced modeling and control of diffusion requires an improved basic understanding of diffusion processes in SiGe and Ge High quality diffusion data on SiGe and Ge are not available

10 10 Current Milestones Year 2 Milestone (2005): Determine diffusion coefficient of O in Ge and the effect of SiO 2 cap on diffusion of Si in Ge (in progress) Year 2 Milestone: Investigate transient enhanced diffusion (TED) in Ge (added) the effect of implantation damage on B diffusion in Ge 09/15/ Process Integration

11 11 Diffusion Mechanisms in Ge Diffusion in Ge is believed to be mostly vacancy-mediated Interstitial Ge has not been observed B diffusion in Ge has high 2 activation energy: D = 6 10 cm Vacancy mechanism 4.5eV s exp kbt 8 * *W. C. Dunlap, Jr., Phys. Rev. 94, 1531 (1954) 09/15/ Process Integration

12 12 Experimental Setup B + implantation (111) Ge wafer B + implantation + Ge + implantation Ge wafer Ge wafer Boron is chosen because it shows very limited equilibrium diffusion; transient enhancement is expected to be detectable Subsequent Ge implantation is used to create excess native defects without introducing electrically active dopants 09/15/ Process Integration

13 13 Preliminary SIMS Results B in Ge B in Ge as-imp; 32keV, cm C 30 min anneal - simulation 550 C 30 min anneal - SIMS data B implantation - simulation Concentration (atoms/cm 3 ) Depth (nm) 09/15/ Process Integration

14 14 Preliminary SIMS Results A broader tail relative to implant simulation is observed in as-implanted profile due to channeling effect Diffusion simulation shows no observable diffusion for 550 C 30 minutes anneal SIMS result shows a significant increase in diffusivity Further experiments are required to pinpoint the source(s) of the diffusion enhancement (TED, random channeling, other effects) 09/15/ Process Integration

15 15 Future Milestones Year 3 Milestone: Effect of implantation damage on dopant diffusion in Ge (Added) Extend the current experiment to other dopants such as P and As More relevant for feature level control because P and As have to be thermally activated to be electrically active whereas B is activated upon implantation Effect of surface on diffusion in Ge (M44) Utilize the test mask to systematically study the effects of selective area oxidation and nitridation on diffusion in Ge 09/15/ Process Integration

16 16 Fabrication and Processing of GeOI Eric Z. Liu, Vorrada Loryuenyong, Prof. Nathan W. Cheung University of California, Berkeley Ge Transferred Germanium 1 cm 850nm Ox/Si 09/15/ Process Integration

17 17 Key Results: Year 2 to date Delamination defect density greatly reduced using Nitrogen plasma treatment prior to bonding CMP process reduces GeOI surface RMS < 1nm ; (5x5µm AFM image) Establish fast turn-around method to evaluate electrical property of bonded interface with Pseudo MOSFET measurement (4-probe configuration). Thermal-Mechanical model predicting transfer layer thickness improved by incorporating : (1) Implantation induced stress effect (2) Thermal mismatch between Ge and Si substrate 09/15/ Process Integration

18 18 Layer Transfer Process Improvement 09/15/ Process Integration

19 19 GeOI surface smoothing by CMP 200nm (a) as-cut GeOI Z[nm] RMS:11.8 nm; Ra:9.5 nm Z-range: 87.8 nm X[µm] 200nm 09/15/ Process Integration Z[nm] (b) after CMP and HF dip RMS: 0.3 nm; Ra: 0.23 nm Z-range: 3 nm X[µm]

20 20 GeOI surface smoothing by CMP and H 2 annealing As-cut,Ra=14.6nm CMP: Ra=0.86nm H 2 anneal+hf dip: Ra=0.7nm (Pad_2: Polishing cloth Rayon- Fine 8 Diameter PSA P/N PRF08A-10, SBT Inc. ) H2 annealing process being optimized for Ra(target) =0.2nm 09/15/ Process Integration

21 21 V 2,3 V Pseudo MOSFET Measurement (4-probe configuration) A I 1,4 Fast turn-around technique to evaluate quality of bonded interface 1 2 Ge 3 4 BOX P + -Si substrate _ V G + BOX interface charge and interface carrier mobility can be extracted 09/15/ Process Integration

22 22 Pseudo MOSFET result 130 I 1,4 for keeping V 2,3 =0.5V I 1,4 /2 for keeping V 2,3 =1.0V I 1,4 /3 for keeping V 2,3 =1.5V 120 I, (µa) I 1,4 = f g C ox (V G -V FB )V 2,3 µ p V G, (V) Accumulated Mode: hole mobility µ p0 =88cm 2 /V-sec 09/15/ Process Integration

23 Implanted layer 09/15/ Process Integration 23 Thermal-Mechanical Model to predict transfer layer thickness Silicon h d Germanium M M= M applied +M thermal + M implant P = P applied +P thermal + P implant K K I II = f 1 = f d E (, h E 2 Si Ge d E (, h E Si Ge )Ph )Ph 1/ 2 1/ 2 + g 1 + g d E (, h E 2 Si Ge d E (, h E Si Ge )Mh )Mh P 3/ 2 3/ 2 Based on Hutchinson and Wu, Adv. Appl. Mechanics (1992) Normalized Y d Y( h 1.0 Interface Delamination E, E Si Ge Under condition K II = Relative Crack Depth, d/h ) = Ph / M = f 2 ( d h E, E Si Ge ) / g 2 ( d h E, E Si Ge )

24 24 Future Milestones H 2 annealing effects on the smoothing of GeOI surface Evaluate bonded interface electrical quality with various processing conditions by Pseudo MOSFET measurements Fabricate and evaluate prototype GeOI MOSFET Demonstrate GeSiOI layer transfer using GeSi epi wafers (with Per-Ove Hansson, AMAT) Investigate interfacial quality with high-k dielectric as buried insulator (with Ilkka Suni, VTT, Finland). 09/15/ Process Integration