There's Plenty of Room at the Bottom

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1 There's Plenty of Room at the Bottom 12/29/1959 Feynman asked why not put the entire Encyclopedia Britannica (24 volumes) on a pin head (requires atomic scale recording). He proposed to use electron microscope to write the words, and to read the words. He also thought that biological systems were already writing and reading information at the molecular (or nano) scale. 1

2 The Nanometer Sizescale Nanotube 2

3 Fabrication Techniques for Nano-Scale Structures Top-down Approaches Lithography (E-beam,EUV) Nano Imprint Dip-Pen Nanolithography Bottom-up' Approaches Selective growth Self-assembly Scanning Tip Manipulation 3

4 e-beam lithography resolution factors beam quality ( ~1 nm) secondary electrons ( lateral range: few nm) performance records organic resist PMMA ~ 7 nm inorganic resist, b.v. AlF 3 ~ 1-2 nm 4

5 The benchmark of Top-down Approach 5nm-Gate Nanowire FinFET 2004 Symposium on VLSI Technology, p.196 5

6 Technology Gap for Top-Down Approach 6

7 How to make a single-crystal Si Nanowire 7

8 Si Nanowire by thermal oxidation Y.Ono et al., Si complementary single-electron inverter, IEDM, pp , 1999 Oxidation rate slows down with mechanical stress induced by surrounding oxide 8

9 30-nm wire fabrication by directional thin-film deposition Triangular cross-section Rectangular cross-section Prober et al, APL, 94 (1980) 9

10 Sidewall Spacer to define nm wires dummy step SiO2 Substrate Si Conformal CVD film ~10nm dummy step SiO2 (1) Substrate (2) Si 10-20nm spacer Spacer as etching mask nm Si SiO2 Substrate Si SiO2 (3) Substrate (4) 10

11 Twin nanowires With anisotropic etching of SOI 11

12 Nanochannel fabrication Sacrificial layer method, deposition method, etc. Cheaper and mass-productable methods Soft mat l vs. hard mat l Tas et al., Nano Letters, 2, 1031 (2002) 12

13 13

14 Dip-Pen Nanolithography * as small as 15 nm linewidths and ~5 nm spatial resolution D. Piner, J. Zhu, F. Xu, and S. Hong, C. A. Mirkin, "Dip-Pen Nanolithography", Science, 1999, 283,

15 Cutting window through a thin layer of Si oxide Local E-beam Line dose: 3.3, 2.5, and 1.7 x 10-3 C/cm, for the three lines from top to bottom; Etching an 8-nm Ag thin film on Si(100) using the LEEB/STM 15

16 By E-Beam 16

17 Nanowire Growth by Vapor-Liquid-Solid Method Growth Modes * Au nanoparticles as catalyst 17

18 1D Functional Heterojunctions LOHNs Nanotape COHNs NanoElectronics Thermoelectrics Selective sensors Prof. P. Yang, Chemistry NanoOptics NanoFludics Si/SiGe TiO2/SnO2 GaN/AlGaN AlGaN/GaN 18

19 19

20 Step Coverage (Al2O3) 20

21 Chemical Modification of Single Walled Nanotubes 21

22 Silicon probe with a conductive single walled carbon nanotube (<2 nm diameter). The tip is at the end of a flexible cantilever designed for the atomic force microscope. A nanotube-bundle tip was used as the negative electrode to locally oxidize silicon and write the oxide pattern C- Tube. OH - ions (from condensed H 2 O on tip) are driven by the strong field into the solid and induce the oxidation by reacting with Si holes in bulk Si. 22

23 Title : Carbon Monoxide Man Media : Carbon Monoxide on Platinum (111) Title: Atom Media: Iron on Copper (111) 23

24 Probe Manipulation Technique 24

25 The smallest transistor 100 I (pa) V g = 6.4 V V g = 6.9 V V g = 7.4 V V g = 7.7 V Operation only at low temp V sd (mv) 25

26 Potassium Doping of CNT (n-type) Javey et al, Nano Lett

27 Field Assisted Assembly Long-range forces attract nanowires to substrate Theresa Mayer EE Dept. dielectric medium + -V metallic particle +V particle moves in gradient of field towards region of highest field strength 27

28 Field Assisted Assembly SiO 2 +V -V V = 0V Nanowires attracted and aligned to top electrodes Alignment process is self limiting SiO 2 +V -V Silicon substrate 28

29 Crossed Nanowire Architecture Nanowires serve dual purpose: both active devices and interconnects. All key nanoscale metrics are defined during synthesis and subsequent assembly. Crossed nanowire architecture provides natural scaling and potential for integration at highest densities. No additional complexity (with added material). 29

30 E-field Enhanced Fluidic Alignment 30

31 Surface Programmed Assembly M. Lee et al Seoul National Univ

32 Logic Gates and Computation from Assembled Nanowire Building Blocks *p-si and n-gan NWs The OR and AND gates has no signal gain Assembly Y. Huang,, Science 291, 630 (2001). Huang et al, SCIENCE VOL NOVEMBER

33 Carbon Nanotube Interconnects Applied Physics Letters, (2003) 33

34 Empirical : Resolution (in Å) ~ 23 Areal Throughput (in µm 2 /hr)

35 Principle and Practice of Top-Down Integration * A sequence of Additive and Subtractive steps with lateral patterning Si wafer Processing Steps Planarization is used to control critical dimensions (lithography, etching, and thin-film deposition) Self-aligned structure used whenever possible Alignment is done for ALL lithography steps (registration marks always available on substrate) 35

36 Grand Challenges of The Bottom Up Approach What is the optimum functional building block using self-assembly? How do we align the different functional blocks for integration? - Alignment marks - 2D or 3D alignment Bocheva et al, PNAS April 16, 2002 vol. 99 no

37 100 A) current (na) time (min) Light Emitting Sensing Magnetic Assembly 20 nm Wavelength Conversion Thermoelectronics Bimorph Mechanics Finite size effect.. Chemical/thermal stability issue for devices Interface/complexity/functionality The integration issue: nano-micro-macro continuum. Catalysis 37

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