Nanostrukturphysik (Nanostructure Physics)
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1 Nanostrukturphysik (Nanostructure Physics) Prof. Yong Lei & Dr. Yang Xu Fachgebiet 3D-Nanostrukturierung, Institut für Physik Contact: Office: Unterpoerlitzer Straße 38 (Heisenbergbau) (tel: 3748) Vorlesung: Wedsnesday 9:00 10:30, C 108 Übung: Friday (G), 9:00 10:30, C 110 (a) (b 1 ) (b 2 ) UTAM-prepared free-standing one-dimensional surface nanostructures on Si substrates: Ni nanowire arrays (a) and carbon nanotube arrays (b).
2 Class 1: a general introduction of fundamentals of nanostructured materials, and definition Class 2: research at 3D-Nanostructuring (01) Class 3: research at 3D-Nanostructuring (02) Class 4: optical properties of 1D nanostructures Class 5: carbon nanotubes Class 6: graphene Class 7: 2D atomically thin nanosheets Class 8: lithium-ion batteries: Si nanostructures Class 9: solar water splitting I: fundamentals Class 10: solar water splitting II: nanostructures for water splitting Class 11: solar cells
3 Single-crystal nanoparticles with identical crystal orientation In nanoparticles a 1 b d b In f SiO 2 Surface normal of Si Si b 1 SiO 2 c b 1 c e a g (b), (b1), (c): Fourier transformation patterns of the same large squared areas b, b1 and c in (a), in In particle and Si respectively. (d), (e) Fourier filtered lattice images of the areas b and c in (a). To study relative orientation relationship between In and Si, we performed the simulation of electron diffraction patterns along the [111] direction of In (f) and the [110] direction of Si (g), both of them have been rotated to fit the patterns in b and c exactly. The surface normal of the Si (001) substrate is defined by the arrow in g. We moved the arrow to f and found that the In (101) plane has almost the same direction as the surface normal direction of Si, which indicates that the In (101) plane is parallel to the Si (002) plane. Therefore, the relative orientation relationship between In and Si was identified as In(101)[111]//Si(002)[110]. The white and black parallel lines at the bottom right corner in d and e are the In (101) and Si (002) planes, respectively.
4 In 2 O 3 nanoparticles b d a In 2 O 3 b SiO 2 Si c c e f g To study the relative orientation relationship between In2O3 and Si, we performed the simulation of electron diffraction patterns along the [110] directions of In2O3 (Sys: Cubic, S. G.: Ia3(206)) (f) and Si (g), both of them have been rotated so that they fit the patterns in b and c exactly. The surface normal of the Si (001) substrate is defined by the arrow in g. We moved the arrow to f and found that the In2O3 (222) plane has almost the same direction as the surface normal direction of Si, which indicates that the In2O3 (222) plane is parallel to the Si (002) plane. Therefore, the relative orientation relationship between In2O3 and Si was identified as In2O3(222)[110]//Si(002)[110]. The white parallels lines at the bottom right corner in d and e are the In2O3 (222) and Si (002) planes, respectively. Y Lei, WK Chim, J Weissmuller, G Wilde, Nanotechnology, 16, 1892, 2005
5 A challenging technical point for UTAM technique to realize quantum-sized surface structures (below nm) Minimum pore diameter of UTAMs is about 10 nm impossible to synthesize surface structures smaller than 10 nm; the arrangement regularity and monodispersity of the pores are poor when the pore diameter is smaller than 20 nm; Prevents the fabrication of surface structures within or close to the quantumsized range (below nm) using the UTAM patterning technique largely limits the investigation of the quantum confinement effect using the UTAM surface nano-patterning process.
6 Well-controlled pore-opening process to the barrier layer of UTAMs realizing pore-opening and surface nanostructures within the quantum-sized range An alumina barrier layer between the pore bottom and the aluminum foil of as-prepared PAMs. It has a hemispherical and scalloped geometry. Using acidic etching solutions, the barrier layer can be thinned and finally removed.
7 UTAMs used in the pore-opening process were prepared using 0.3 M modulated H 2 SO 4 solutions (glycol/water: 3:2) under 25 V at 4 o C, cell-size 60 nm, pore-diameter 20 nm, barrier layer thickness 20 nm Pore-opening process was carried out using a 5 wt% H 3 PO 4 solution at 30 o C Before the etching, UTAMs were covered by a protecting PMMA layer on the top so that the H 3 PO 4 solution only etch on the bottom surface. (a) (b) [nm] [nm] nm x nm o min 1: Before etching in 5 wt% H 3 PO 4 solution (30 o C) nm x nm 10 mins surface 0.00 After 8 min etching in 5 wt% H 3 PO 4 solution (30 o C)
8 (c) (d) [nm] [nm] nm x nm 10min 1: After 15 min etching in 5wt% H 3 PO 4 solution (30 o C) The pore diameter is about 5 nm (e) nm x nm 2-18mins edge 0.00 After 18 min etching in 5 wt% H 3 PO 4 solution (30 o C) The pore diameter is about 10 nm (f) [nm] [nm] nm x nm 2-24mins nm x nm h20 30mins 0.00 After 24 min etching in 5 wt% H 3 PO 4 solution (30 o C) The pore diameter is about 17 nm After 30 min etching in 5 wt% H 3 PO 4 solution (30 o C) The pore diameter is about 22 nm
9 Mechanism of the pore-opening process (a) Before etching (b) After 8 min etching (c) After 13 min etching (d) After 15 min etching (e) After 18 min etching (f) After 24 min etching (a) Acid ions consumed at barrier layer surface ionic compensation easier at the top of the barrier layer than that at the bottom ionic concentration at the top is higher than the bottom a faster etching rate at the top. (c) ~ 13 min etching center of barrier layer opens while the other parts keep closed. (d-h) With further etching, the poreopening becomes larger and their size increases with the etching time. Meanwhile, acid solution goes into the pores via the openings and etches pore walls, i.e. a pore-widening process accompanying a pore-opening process. The double-sided etching on barrier layer (d-f) flattens hemispherical barrier layer an almost flat bottom surface (h). (g) After 30 min etching (h) After 40 min etching
10 UTAM surface nano-patterning Barrier layer Quantum dot array 5 nm 10 nm 17 nm L.Y. Wen, Y. Lei, et al., Small 2010, 6 (5), 695. Fabian Grote
11 Device applications of UTAM-prepared surface patterns 1. Metal insulator semiconductor (MIS) memory device based on ordered Ge nanodot arrays. (Z Chen, Y Lei, et al., J. Cry. Grow., 268, 560, 2004). 2. Fe/Pt multi-layer nanodot arrays with interesting magnetic properties (J Ellrich, Y Lei, H Hahn, patent application, 2008). 3. Other possible device applications (Lei Y, et al., Adv. Eng. Mater., 9, 343, 2007).
12 Metal insulator semiconductor (MIS) memory device based on Ge nanodots The MIS structure is composed of four sub-layers on the Si substrate: a 5 nmthick oxide layer (RTO) beneath 3 nm-thick Ge nanoparticles, a 50 nm-thick oxide capping layer, and an Al gate electrode on the top. The RTO and capping oxide layers act as the insulating layer.
13 The Ge nanodots have a diameter of 80 nm and a density of ~ cm -2 CV characteristics show a charge storage capacity of Coulomb/cm -2 The most important advantage of these devices is a controllable CV properties and a much longer device lifetime comparing to the devices using the semiconductor films. Z Chen, Y Lei, et al., J. Cry. Grow., 268, 560, 2004 C-V characteristics of MIS structures after RTA at 1000 o C for 200 s (device A) and at 700 o C for 200 s (device B).
14 Intensity (a. u.) (a) Si 10nm 20nm CdS 3. Photoluminescence properties of CdS nanodots SiO 2 CdS CdS (a) (b) 10nm (c) Additional deposition SiO 2 Si CdS SiO 2 (b) 100nm Si 10nm Flat discs sub-band I sub-band II sub-band I sub-band II Wavelength (nm) Sample A Two Gaussian fit sub-bands (I, II) Gaussian fit (I + II) Sample B Two Gaussian fit sub-bands (I, II) Gaussian fit (I + II) Y Lei, WK Chim, HP Sun, G Wilde, Appl. Phys. Lett., 86, ,
15 4. Large-scale ordered carbon nanotube (CNT) arrays initiated from highly ordered catalyst arrays on silicon substrates 1. Use the highly ordered metal nanoparticle arrays (Au, Fe, Ni, and Co) as the catalysts to fabricate one-dimensional nanomaterials. 2. Two methods to fabricate ordered aligned arrays of individual CNTs: EBL method: graphitized CNTs; adjustable diameters and spacing of the CNTs. (limited pattern area; high capital cost) Template method: large pattern areas; low equipment capital costs. (difficult to obtain CNT arrays on the substrate; poor crystallinity) Combine the advantages of the template and the EBL methods.
16 Fabrication Process of highly ordered CNT arrays on Si substrate Catalyst array Carbon nanotube array Si wafer Ultra-thin Catalyst array alumina mask
17 Ni film area (d 2 ) Ordered CNT array on Ni particle area (c 4 ) (c 2 ) (c 3 ) (c 5 ) 200nm (d 3 ) (d) (c) Ordered CNT array grown from the Ni nanoparticle array. (d) CNTs grown from Ni film for the comparison with CNTs. (c)
18 a b 1. Ordered arrays of CNTs with monodisperse diameters have been successfully fabricated on Si substrates with quite large areas. 2. Due to the high uniformity of such aligned arrays of graphitized CNTs, their properties, especially the field-emission properties, are worthy of further study. Y Lei, Chem. Mater., 16, 2757, 2004
19 UTAM surface nano-patterning Attractive features of the UTAM surface nano-patterning Large pattern area (> 1cm 2 ) and high throughput; high density of the surface nanostructures ( cm -2 ); a general process to prepare different patterns (semiconductors, metals); well-defined nanostructures; low equipment costs. Y. Lei, et.al., J. Am. Chem. Soc., 127, 1487, 2005; Chem. Mater., 17, 580, 2005; Chem. Mater., 16, 2757, 2004; Appl. Phys. Lett., 86, , 2005; Nanotechnology, 16, 1892, Y. Lei, et al., Progress in Materials Science, 52, 465, Fabian Grote
20 Sub-100-nm Nanoparticle Arrays with Perfect Ordering, Tunable and Uniform Dimensions Fabricated by Combining Nanoimprinting with UTAM Technique Zhan Z.B., Lei Y., et al., ACS Nano, 8 (4), , 2014.
21 Wafer-scale (4 in. ) UTAM transferring Perfect mounting without any twisting, folding, cracking and contamination A free-standing 4-in. wafer-scale UTAM with the residual Al frame Al-Haddad, Lei, et al., ACS Nano, 9(8): , 2015
22 Three-Dimensional Surface Nano-Patterning (from 2006) Multifunctional surface nano-structures One A much of the larger most surface attractive area advantages of nanomaterials (extremely large surface area) is missing in the existing 2-D surface nano-patterns Possible to increase the device density in the nanodots nanowires Dual-core CPU lateral direction feature-size 45 nm Only way to increase the device density is to decrease the pattern size nanorings nanotubes From Intel Homepage, Public Relations Much lower contacting influence from the substrate Large contacting influence from the substrate very large signal noises degrades device performance An efficient evolution from 2-D to 3-D surface nano-patterning: Change from nanodots or nanorings to nanowires or nanotubes
23 From 2D to 3D surface patterns using templates Large-scale free-standing metallic nanowires for 3D surface patterns: (Left): top view of nanowire array of an area of about 775 μm 2. (Right): high regularity of nanowire arrays.
24 3D Surface Nano-Patterning: Addressing Schematic of addressing system (only shows an array of 3 3) Addressing System for 3-D surface nanostructures with nano-scale resolution nanowire 1A 2009 obtained the ERC Grant from the European Research Council (ERC). 1.4 million Euros is granted from ERC. It is the second round of the ERC starting grant (with only about 9% successful rate).
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