Multiple Gate CMOS and Beyond

Transcription

1 Multiple CMOS and Beyond Dept. of EECS, KAIST Yang-Kyu Choi

2 Outline 1. Ultimate Scaling of MOSFETs - 3nm Nanowire FET - 8nm Non-Volatile Memory Device 2. Multiple Functions of MOSFETs 3. Summary 2

3 CMOS Evolution Scenario S G D S G D Fin Fin Fin Buried Oxide Bulk-single gate SOI single gate Double gate Ω-gate All-around No report for Sub-50nm L G =4nm NEC IEDM 2003 L G =8nm IBM IEDM 2003 L G =10nm AMD/Berkeley IEDM 2003 L G =10nm LETI VLSI 2005 This Work 3

4 ITRS Roadmap L G (nm) EOT Bulk SG (nm) DG I sd,leak (µa/µm) I d,sat (ma/mm) Bulk SG DG Bulk SG DG Solution exist Solution being pursued No known solution Source: ITRS 2005 roadmap

5 All-Around (AAG) FinFET Source AAG-FinFET L G =3nm W Fin =3nm EOT(HfO 2 )=1.2nm Drain To fabricate sub-5nm silicon transistor, All-Around (AAG) FinFET was proposed. 5

6 Process Flow of AAG-FinFET (100) SOI wafer Silicon body thinning Fin patterning (dual-resist) Sacrificial oxidation dielectric (HfO 2 ) Poly-silicon deposition patterning (dual-resist) Spacer formation Source/Drain implantation Spike annealing (1000 o C) Forming gas annealing (450 o C) 6

7 3nm AAG FinFET: Silicon-Fin Silicon fin 20nm HfO 2 Source S Poly-si 3nm Drain Buried oxide 5nm 3nm 5nm 7 Y.-K. Choi et al., VLSI, 2006

8 3nm AAG FinFET: 5nm Poly-si Source 5nm Poly-si HfO 2 IFO 5nm Si Poly-si 3nm Drain HfO 2 IFO Silicon fin 5nm Si 8

9 I-V of 3nm AAG FinFET Drain Current [A/µm] 10-3 Simulated Measured V D =1.0V V D =0.2V DIBL=230mV/V SS=208 mv/dec 60 HfO 2 =1.4nm 40 L G =3nm 20 W Fin =3nm Voltage [V] Transconductance [µs/µm] Drain Current [µa/µm] HfO 2 =1.4nm L G =3nm W Fin =3nm 0.6V 0.4V V G =0.2V Drain Voltage [V] Large DIBL and SS due to thick EOT ITRS requirement: 0.5nm EOT for DG 9

10 Fundamental Limit of Scaling Device scaling limit (Operating at 300K) Heisenberg s uncertainty principle Shannon - von Neumann - Landauer (SNL) expression SCALING LIMIT x min h = = p = 1.5nm h 2m E c bit = ( T = 300K) 2m k c h B T ln Fabricated 3nm all-around gate FinFET is approaching to this fundamental limit. 10

11 Nanowire Structure Silicon nanowire non-volatile memory structure for ultimate scaling Poly-silicon Blocking oxide Nitride trap layer Tunneling oxide Si Buried Oxide 8nm Non-Volatile Memory Omega-shape gate ONO-structure 11

12 8nm Si Nanowire NVM Poly-silicon N O O S e - S Silicon Nanowire (7/10nm) trap sites BOX Tunneling oxide Nitride trap layer Blocking oxide 10nm Poly-silicon 12 Y.-K. Choi et al., VLSI, 2007

13 8nm Si Nanowire NVM 7/10nm 3.8nm 6.4nm 5.1nm Oxide Nitride Silicon T ONO =15nm > L G =8nm 8nm 5.1nm 6.4nm 3.8nm 13

14 Drain Current [A/µm] 8nm Silicon Nanowire NVM with ONO 1x10-4 1x ONO=3.8/6.4/5.1nm t Program =80µsec Initial 8V 10V V PG =12V L G =8nm W NW =7nm H NW =10.5nm Voltage [V] Drain Current [A/µm] 1x10-4 1x V ER =-12V 8nm L G with 7nm W NW using ONO-structure ONO=3.8/6.4/5.1nm t Erase =80µsec - Acceptable electrical performance by omega-gate -10-8V Initial L G =8nm W NW =7nm H NW =10.5nm Voltage [V] - Wide hysteresis shows the probability of multi-level NVM 14

15 8nm Si Nanowire Memory V T [V] ONO=3.8/6.4/5.1nm L G =8nm W NW =7nm V PG =12V V PG =10V V PG =8V Program Time [sec] V T [V] L G =8nm W NW =7nm H NW =10nm -10V V ER =-8V 0.5 V 0.0 ER =-12V Erase Time [sec] 8nm NVM: V T window = 2V +12V/1msec, 15

16 Scaling Limit in NVM Ultimately scaled NVM Nanowire + SONOS T O/N/O =15nm > L g =8nm Y.-K. Choi et. al., VLSI 2007 Scaling Limit! Close to end-point of semiconductor memory 16

17 Where to Go? Multi- Functioning This Work! Down Scaling Multi-Bit We are here 17

18 Example of Fusion Memory (System in Package) DRAM NVM SRAM. Increased volume Complexity in assembly Chip-to-chip interference 18 Wafer level fusion!!

19 Principal of SONOS Flash Memory S control oxide nitride tunnel oxide D S Substrate Substrate < program > < erase > D Drain current 1 0 S D Substrate Substrate < read 0 > < read 1 > S D voltage Features of flash High density Non-volatile Speed 19

20 Principal of Capacitorless DRAM S Buried oxide Substrate < program > D S D Buried oxide Substrate < erase > S Buried oxide Substrate < read 1 > Drain current D S 1 0 Time Buried oxide Substrate < read 0 > D Source : IEEE spectrum Dec Features of 1T-DRAM High speed 2x denser than 1T/1C DRAM 5x denser than SRAM Volatile 20

21 Basis of URAM Operation (1) voltage capacitorless 1T-DRAM erase flash program capacitorless 1T-DRAM program Drain voltage flash erase Flash Memory Mode - Program : FN tunneling/hei - Erase : FN tunneling/hhi (High gate & drain voltage) Capacitorless 1T-DRAM Mode - Program : Impact ionization - Erase : Forward junction current (Low gate & drain voltage) Disturbance Issue - Periodical refresh 21

22 Multi-Function (URAM) Operation Flash Memory electron DRAM hole Oxide Nitride Oxide Source Drain 드레인 Quantum Barrier 22

23 Family of URAM S. Okonin et.al., SOI conf., 2001 R. Ranica et.al., VLSI symp.,

24 Process Flow (1) SOI Substrate Si Buried oxide Si substrate Initial SOI substrate SON Substrate SOC Substrate Si Si:C Si substrate Initial bulk substrate Si:C epitaxial growth Si epitaxial growth SOG Substrate Si n-well Si substrate Initial bulk substrate Buried n-well implantation p-body implantation 24 Si Si:Ge Si substrate Initial bulk substrate Si:Ge epitaxial growth Si epitaxial growth

25 Process Flow (2) fin Hole barrier layer Si substrate Puntch stop implantation Active fin lithography Photoresist trimming Fin patterning fin SiO 2 SiO 2 Hole barrier layer Si substrate HDP oxide deposition Oxide CMP Oxide recess formation 25

26 Process Flow (3) fin SiO 2 SiO 2 Hole barrier layer Si substrate fin SiO 2 SiO 2 Hole barrier layer Si substrate O/N/O formation Poly-Si deposition patterning S/D implantation Activation Forming gas annealing 26

27 URAM on SOI 27

28 Cross sectional view of URAMs URAM on SOI URAM on SiC URAM on Buried N-well URAM On SiGe 28

29 I D -V G Characteristics 10-5 V D = 1V Drain current, V D (A) I D SOI SOC SOG SON voltage, V G (V) Superior device performances are result of the 3D nature. 29

30 I D -V D Characteristics (Kink) SOI SOC SON SOG 30

31 P/E in NVM Program Erase P/E sensing windows are acceptable. 31

32 Reliability in NVM Retention Endurance Data retention and endurance are acceptable. 32

33 Capacitorless 1T-DRAM in SOI FD URAM PD URAM V 0.7V 0.6V Source current, I S (µa) I s =20µΑ I s =7µΑ SOI URAM 20 80msec 10 Conventional FinFET SONOS Time, t (msec) < Potential Profile > < Measurement Results > Proposed SOI URAM exhibits wider sensing current window. Y.-K. Choi et. al., IEDM 2007

34 Capacitorless 1T-DRAM in SON bulk MOSFET Y.-K. Choi et. al., VLSI 2008 SON URAM Sensing current, I S (µa) V SUB =0.5V V SUB =0.3V I S =7µA I 8 S =4µA V SUB =0V Time, t (msec) < Excess Hole Concentration > < Measurement Results > Capacitorless 1T-DRAM works in SON floating substrate. 34

35 Capacitorless 1T-DRAM at SOC SON URAM SOC URAM 28 Y.-K. Choi et. al., VLSI 2008 Source current, I S (µa) V SUB =0.3V V SUB =0V I S =7µA I S =11µA Time, t (msec) < Excess Hole Concentration > < Measurement Results > Capacitorless 1T-DRAM works in SOC floating substrate. 35

36 Summary IT only NT only NT IT 3nm MOSFET and 8nm non-volatile memory device were demonstrated. Close to scaling limit. Multi-function URAM was demonstrated. Continuously increased density 36

37 Built-in Potential for Buried n-well SIMS profile of the buried n-well Simulation Result of Energy Band 0.9 ev Built-in potential confines excess holes. 37

38 Band-Offset for Si:C & Si:Ge (2) 1.0 C-V for Band Engineered Substrate Energy Band Diagram Normalized capacitance Si/Si 0.94 C 0.06 /Si E V =-180 mev Si/Si 0.7 Ge 0.3 /Si E V = 200 mev voltage, V G (V) Double slopes appear in weak accumulation region. 38

39 Scaling Issue (Why capacitorless DRAM?) µ-processor Cache memory SRAM (32F 2 ) Cache portion 50% in 2006 Capacitorless DRAM is a promising candidate for embedded memory % in % in 2011 Is this memory or µ-processor? Cell capacitance in DRAM > 25fF (non-scalable) Cell area (~8F 2 ) is continuously reduced.

40 Soft-Program Issue voltage capacitorless 1T-DRAM erase flash program capacitorless 1T-DRAM program Drain voltage Disturbance Issue - Periodical refresh 1T-DRAM mode Initialization : Set V T of all cells to 0.2V by adjustment of trapped charges Capacitorless 1T-DRAM operation refresh yes Verification V T =0.2V? no 40

41 GIDL Program Method Bias (V) Source current, I S (µa) voltage Drain voltage Impact ionization 100 nsec 100 nsec 12µA Time, t (µsec) < 1T-DRAM Measurement > Threshold voltage, V T (V) GIDL Impact ionization program V G =1, V D =2V GIDL program V G =-2V, V D =2V Stress time, t (sec) < Soft-program test > GIDL program method mitigates soft-programming. [J.-W. Han et. al., EDL, Apr. 2009]

42 G-to-S/D Underlap Structure S Buried oxide Substrate D 50nm G-to-S/D Overlap junction S Buried oxide Substrate D S Buried oxide D G-to-S/D Underlap [J.-W. Han et. al., EDL, May 2009] 42

43 G-to-S/D Underlap Structure Bias (V) Source current, I S (µa/µm) V G V D 50 nsec G-to-S/D underlap 8 µa G-to-S/D overlap 50 nsec 11 µa Time, t (msec) < 1T-DRAM Measurement > Threshold voltage, V T (V) Stress bais : V G =1V, V D =2.5V G-to-S/D overlap G-to-S/D underlap Stress time, t (sec) < Soft-program test > G-to-S/D underlap structure mitigates soft-programming. [J.-W. Han et. al., EDL, May 2009] 43

44 S S Issue and Solution of G-to-S/D Underlap Device Structure Buried oxide Substrate SiO 2 Spacer Buried oxide Substrate SiO 2 D High-k D Source current (µa/µm) underlap with HfO 2 spacer I S,HfO2 =55µA 20 0 underlap with I S,SiO2 =20µA -20 SiO 2 spacer read hold erase hold read Time (nsec) 44 overlap with SiO 2 spacer I S =11µA High-k Spacer < Simulation Results > High-k spacer countervails the parasitic series resistance of the G-to-S/D underlap. [J.-W. Han et. al., EDL, May 2009]